ReactOS  0.4.14-dev-49-gfb4591c
cpu.h
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1 /*
2  * Copyright (c) 2018-present, Facebook, Inc.
3  * All rights reserved.
4  *
5  * This source code is licensed under both the BSD-style license (found in the
6  * LICENSE file in the root directory of this source tree) and the GPLv2 (found
7  * in the COPYING file in the root directory of this source tree).
8  * You may select, at your option, one of the above-listed licenses.
9  */
10 
11 #ifndef ZSTD_COMMON_CPU_H
12 #define ZSTD_COMMON_CPU_H
13 
19 #include <string.h>
20 
21 #include "mem.h"
22 
23 #ifdef _MSC_VER
24 #include <intrin.h>
25 #endif
26 
27 typedef struct {
32 } ZSTD_cpuid_t;
33 
35  U32 f1c = 0;
36  U32 f1d = 0;
37  U32 f7b = 0;
38  U32 f7c = 0;
39 #if defined(_MSC_VER) && (defined(_M_X64) || defined(_M_IX86))
40  int reg[4];
41  __cpuid((int*)reg, 0);
42  {
43  int const n = reg[0];
44  if (n >= 1) {
45  __cpuid((int*)reg, 1);
46  f1c = (U32)reg[2];
47  f1d = (U32)reg[3];
48  }
49  if (n >= 7) {
50  __cpuidex((int*)reg, 7, 0);
51  f7b = (U32)reg[1];
52  f7c = (U32)reg[2];
53  }
54  }
55 #elif defined(__i386__) && defined(__PIC__) && !defined(__clang__) && defined(__GNUC__)
56  /* The following block like the normal cpuid branch below, but gcc
57  * reserves ebx for use of its pic register so we must specially
58  * handle the save and restore to avoid clobbering the register
59  */
60  U32 n;
61  __asm__(
62  "pushl %%ebx\n\t"
63  "cpuid\n\t"
64  "popl %%ebx\n\t"
65  : "=a"(n)
66  : "a"(0)
67  : "ecx", "edx");
68  if (n >= 1) {
69  U32 f1a;
70  __asm__(
71  "pushl %%ebx\n\t"
72  "cpuid\n\t"
73  "popl %%ebx\n\t"
74  : "=a"(f1a), "=c"(f1c), "=d"(f1d)
75  : "a"(1));
76  }
77  if (n >= 7) {
78  __asm__(
79  "pushl %%ebx\n\t"
80  "cpuid\n\t"
81  "movl %%ebx, %%eax\n\r"
82  "popl %%ebx"
83  : "=a"(f7b), "=c"(f7c)
84  : "a"(7), "c"(0)
85  : "edx");
86  }
87 #elif defined(__x86_64__) || defined(_M_X64) || defined(__i386__)
88  U32 n;
89  __asm__("cpuid" : "=a"(n) : "a"(0) : "ebx", "ecx", "edx");
90  if (n >= 1) {
91  U32 f1a;
92  __asm__("cpuid" : "=a"(f1a), "=c"(f1c), "=d"(f1d) : "a"(1) : "ebx");
93  }
94  if (n >= 7) {
95  U32 f7a;
96  __asm__("cpuid"
97  : "=a"(f7a), "=b"(f7b), "=c"(f7c)
98  : "a"(7), "c"(0)
99  : "edx");
100  }
101 #endif
102  {
103  ZSTD_cpuid_t cpuid;
104  cpuid.f1c = f1c;
105  cpuid.f1d = f1d;
106  cpuid.f7b = f7b;
107  cpuid.f7c = f7c;
108  return cpuid;
109  }
110 }
111 
112 #define X(name, r, bit) \
113  MEM_STATIC int ZSTD_cpuid_##name(ZSTD_cpuid_t const cpuid) { \
114  return ((cpuid.r) & (1U << bit)) != 0; \
115  }
116 
117 /* cpuid(1): Processor Info and Feature Bits. */
118 #define C(name, bit) X(name, f1c, bit)
119  C(sse3, 0)
120  C(pclmuldq, 1)
121  C(dtes64, 2)
122  C(monitor, 3)
123  C(dscpl, 4)
124  C(vmx, 5)
125  C(smx, 6)
126  C(eist, 7)
127  C(tm2, 8)
128  C(ssse3, 9)
129  C(cnxtid, 10)
130  C(fma, 12)
131  C(cx16, 13)
132  C(xtpr, 14)
133  C(pdcm, 15)
134  C(pcid, 17)
135  C(dca, 18)
136  C(sse41, 19)
137  C(sse42, 20)
138  C(x2apic, 21)
139  C(movbe, 22)
140  C(popcnt, 23)
141  C(tscdeadline, 24)
142  C(aes, 25)
143  C(xsave, 26)
144  C(osxsave, 27)
145  C(avx, 28)
146  C(f16c, 29)
147  C(rdrand, 30)
148 #undef C
149 #define D(name, bit) X(name, f1d, bit)
150  D(fpu, 0)
151  D(vme, 1)
152  D(de, 2)
153  D(pse, 3)
154  D(tsc, 4)
155  D(msr, 5)
156  D(pae, 6)
157  D(mce, 7)
158  D(cx8, 8)
159  D(apic, 9)
160  D(sep, 11)
161  D(mtrr, 12)
162  D(pge, 13)
163  D(mca, 14)
164  D(cmov, 15)
165  D(pat, 16)
166  D(pse36, 17)
167  D(psn, 18)
168  D(clfsh, 19)
169  D(ds, 21)
170  D(acpi, 22)
171  D(mmx, 23)
172  D(fxsr, 24)
173  D(sse, 25)
174  D(sse2, 26)
175  D(ss, 27)
176  D(htt, 28)
177  D(tm, 29)
178  D(pbe, 31)
179 #undef D
180 
181 /* cpuid(7): Extended Features. */
182 #define B(name, bit) X(name, f7b, bit)
183  B(bmi1, 3)
184  B(hle, 4)
185  B(avx2, 5)
186  B(smep, 7)
187  B(bmi2, 8)
188  B(erms, 9)
189  B(invpcid, 10)
190  B(rtm, 11)
191  B(mpx, 14)
192  B(avx512f, 16)
193  B(avx512dq, 17)
194  B(rdseed, 18)
195  B(adx, 19)
196  B(smap, 20)
197  B(avx512ifma, 21)
198  B(pcommit, 22)
199  B(clflushopt, 23)
200  B(clwb, 24)
201  B(avx512pf, 26)
202  B(avx512er, 27)
203  B(avx512cd, 28)
204  B(sha, 29)
205  B(avx512bw, 30)
206  B(avx512vl, 31)
207 #undef B
208 #define C(name, bit) X(name, f7c, bit)
209  C(prefetchwt1, 0)
210  C(avx512vbmi, 1)
211 #undef C
212 
213 #undef X
214 
215 #endif /* ZSTD_COMMON_CPU_H */
static const WCHAR sha[]
Definition: oid.c:1218
#define C(name, bit)
Definition: cpu.h:208
Definition: optimize.h:107
int f1c(const S1 &)
unsigned int U32
Definition: mem.h:77
GLdouble n
Definition: glext.h:7729
#define ds
Definition: i386-dis.c:434
U32 f7b
Definition: cpu.h:30
MEM_STATIC ZSTD_cpuid_t ZSTD_cpuid(void)
Definition: cpu.h:34
Definition: optimize.h:112
#define B(name, bit)
Definition: cpu.h:182
__asm__("\t.globl GetPhys\n" "GetPhys:\t\n" "mflr 0\n\t" "stwu 0,-16(1)\n\t" "mfmsr 5\n\t" "andi. 6,5,0xffef\n\t" "mtmsr 6\n\t" "isync\n\t" "sync\n\t" "lwz 3,0(3)\n\t" "mtmsr 5\n\t" "isync\n\t" "sync\n\t" "lwz 0,0(1)\n\t" "addi 1,1,16\n\t" "mtlr 0\n\t" "blr")
U32 f7c
Definition: cpu.h:31
U32 f1c
Definition: cpu.h:28
double __cdecl fma(double, double, double)
#define MEM_STATIC
Definition: mem.h:39
Definition: time.h:76
__INTRIN_INLINE void __cpuidex(int CPUInfo[4], int InfoType, int ECXValue)
Definition: intrin_x86.h:1530
PPC_QUAL void __cpuid(int CPUInfo[], const int InfoType)
Definition: intrin_ppc.h:682
#define D(name, bit)
Definition: ttei6.cpp:27
static int reg
Definition: i386-dis.c:1275
Definition: optimize.h:103
#define ss
Definition: i386-dis.c:432
U32 f1d
Definition: cpu.h:29