ReactOS 0.4.15-dev-7942-gd23573b
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#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ |
#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ |
#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ |
#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ |
#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ |
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ |
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ |
#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ |
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ |
#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ |
#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ |
#define PCI_CLASS_REVISION |
#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ |
#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ |
#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ |
#define PCI_PM_PMC 2 /* PM Capabilities Register */ |
#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ |
#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ |
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ |
#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ |
#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ |