ReactOS  0.4.14-dev-608-gd495a4f
pcidef.h File Reference

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Macros

#define PCI_VENDOR_ID   0x00 /* 16 bits */
 
#define PCI_DEVICE_ID   0x02 /* 16 bits */
 
#define PCI_COMMAND   0x04 /* 16 bits */
 
#define PCI_COMMAND_IO   0x1 /* Enable response in I/O space */
 
#define PCI_COMMAND_MEMORY   0x2 /* Enable response in Memory space */
 
#define PCI_COMMAND_MASTER   0x4 /* Enable bus mastering */
 
#define PCI_COMMAND_SPECIAL   0x8 /* Enable response to special cycles */
 
#define PCI_COMMAND_INVALIDATE   0x10 /* Use memory write and invalidate */
 
#define PCI_COMMAND_VGA_PALETTE   0x20 /* Enable palette snooping */
 
#define PCI_COMMAND_PARITY   0x40 /* Enable parity checking */
 
#define PCI_COMMAND_WAIT   0x80 /* Enable address/data stepping */
 
#define PCI_COMMAND_SERR   0x100 /* Enable SERR */
 
#define PCI_COMMAND_FAST_BACK   0x200 /* Enable back-to-back writes */
 
#define PCI_STATUS   0x06 /* 16 bits */
 
#define PCI_STATUS_CAP_LIST   0x10 /* Support Capability List */
 
#define PCI_STATUS_66MHZ   0x20 /* Support 66 Mhz PCI 2.1 bus */
 
#define PCI_STATUS_UDF   0x40 /* Support User Definable Features [obsolete] */
 
#define PCI_STATUS_FAST_BACK   0x80 /* Accept fast-back to back */
 
#define PCI_STATUS_PARITY   0x100 /* Detected parity error */
 
#define PCI_STATUS_DEVSEL_MASK   0x600 /* DEVSEL timing */
 
#define PCI_STATUS_DEVSEL_FAST   0x000
 
#define PCI_STATUS_DEVSEL_MEDIUM   0x200
 
#define PCI_STATUS_DEVSEL_SLOW   0x400
 
#define PCI_STATUS_SIG_TARGET_ABORT   0x800 /* Set on target abort */
 
#define PCI_STATUS_REC_TARGET_ABORT   0x1000 /* Master ack of " */
 
#define PCI_STATUS_REC_MASTER_ABORT   0x2000 /* Set on master abort */
 
#define PCI_STATUS_SIG_SYSTEM_ERROR   0x4000 /* Set when we drive SERR */
 
#define PCI_STATUS_DETECTED_PARITY   0x8000 /* Set on parity error */
 
#define PCI_CLASS_REVISION
 
#define PCI_REVISION_ID   0x08 /* Revision ID */
 
#define PCI_CLASS_PROG   0x09 /* Reg. Level Programming Interface */
 
#define PCI_CLASS_DEVICE   0x0a /* Device class */
 
#define PCI_CACHE_LINE_SIZE   0x0c /* 8 bits */
 
#define PCI_LATENCY_TIMER   0x0d /* 8 bits */
 
#define PCI_HEADER_TYPE   0x0e /* 8 bits */
 
#define PCI_HEADER_TYPE_NORMAL   0
 
#define PCI_HEADER_TYPE_BRIDGE   1
 
#define PCI_HEADER_TYPE_CARDBUS   2
 
#define PCI_BIST   0x0f /* 8 bits */
 
#define PCI_BIST_CODE_MASK   0x0f /* Return result */
 
#define PCI_BIST_START   0x40 /* 1 to start BIST, 2 secs or less */
 
#define PCI_BIST_CAPABLE   0x80 /* 1 if BIST capable */
 
#define PCI_BASE_ADDRESS_0   0x10 /* 32 bits */
 
#define PCI_BASE_ADDRESS_1   0x14 /* 32 bits [htype 0,1 only] */
 
#define PCI_BASE_ADDRESS_2   0x18 /* 32 bits [htype 0 only] */
 
#define PCI_BASE_ADDRESS_3   0x1c /* 32 bits */
 
#define PCI_BASE_ADDRESS_4   0x20 /* 32 bits */
 
#define PCI_BASE_ADDRESS_5   0x24 /* 32 bits */
 
#define PCI_BASE_ADDRESS_SPACE   0x01 /* 0 = memory, 1 = I/O */
 
#define PCI_BASE_ADDRESS_SPACE_IO   0x01
 
#define PCI_BASE_ADDRESS_SPACE_MEMORY   0x00
 
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK   0x06
 
#define PCI_BASE_ADDRESS_MEM_TYPE_32   0x00 /* 32 bit address */
 
#define PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02 /* Below 1M [obsolete] */
 
#define PCI_BASE_ADDRESS_MEM_TYPE_64   0x04 /* 64 bit address */
 
#define PCI_BASE_ADDRESS_MEM_PREFETCH   0x08 /* prefetchable? */
 
#define PCI_BASE_ADDRESS_MEM_MASK   (~0x0fUL)
 
#define PCI_BASE_ADDRESS_IO_MASK   (~0x03UL)
 
#define PCI_CARDBUS_CIS   0x28
 
#define PCI_SUBSYSTEM_VENDOR_ID   0x2c
 
#define PCI_SUBSYSTEM_ID   0x2e
 
#define PCI_ROM_ADDRESS   0x30 /* Bits 31..11 are address, 10..1 reserved */
 
#define PCI_ROM_ADDRESS_ENABLE   0x01
 
#define PCI_ROM_ADDRESS_MASK   (~0x7ffUL)
 
#define PCI_CAPABILITY_LIST   0x34 /* Offset of first capability list entry */
 
#define PCI_INTERRUPT_LINE   0x3c /* 8 bits */
 
#define PCI_INTERRUPT_PIN   0x3d /* 8 bits */
 
#define PCI_MIN_GNT   0x3e /* 8 bits */
 
#define PCI_MAX_LAT   0x3f /* 8 bits */
 
#define PCI_PRIMARY_BUS   0x18 /* Primary bus number */
 
#define PCI_SECONDARY_BUS   0x19 /* Secondary bus number */
 
#define PCI_SUBORDINATE_BUS   0x1a /* Highest bus number behind the bridge */
 
#define PCI_SEC_LATENCY_TIMER   0x1b /* Latency timer for secondary interface */
 
#define PCI_IO_BASE   0x1c /* I/O range behind the bridge */
 
#define PCI_IO_LIMIT   0x1d
 
#define PCI_IO_RANGE_TYPE_MASK   0x0f /* I/O bridging type */
 
#define PCI_IO_RANGE_TYPE_16   0x00
 
#define PCI_IO_RANGE_TYPE_32   0x01
 
#define PCI_IO_RANGE_MASK   ~0x0f
 
#define PCI_SEC_STATUS   0x1e /* Secondary status register, only bit 14 used */
 
#define PCI_MEMORY_BASE   0x20 /* Memory range behind */
 
#define PCI_MEMORY_LIMIT   0x22
 
#define PCI_MEMORY_RANGE_TYPE_MASK   0x0f
 
#define PCI_MEMORY_RANGE_MASK   ~0x0f
 
#define PCI_PREF_MEMORY_BASE   0x24 /* Prefetchable memory range behind */
 
#define PCI_PREF_MEMORY_LIMIT   0x26
 
#define PCI_PREF_RANGE_TYPE_MASK   0x0f
 
#define PCI_PREF_RANGE_TYPE_32   0x00
 
#define PCI_PREF_RANGE_TYPE_64   0x01
 
#define PCI_PREF_RANGE_MASK   ~0x0f
 
#define PCI_PREF_BASE_UPPER32   0x28 /* Upper half of prefetchable memory range */
 
#define PCI_PREF_LIMIT_UPPER32   0x2c
 
#define PCI_IO_BASE_UPPER16   0x30 /* Upper half of I/O addresses */
 
#define PCI_IO_LIMIT_UPPER16   0x32
 
#define PCI_ROM_ADDRESS1   0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
 
#define PCI_BRIDGE_CONTROL   0x3e
 
#define PCI_BRIDGE_CTL_PARITY   0x01 /* Enable parity detection on secondary interface */
 
#define PCI_BRIDGE_CTL_SERR   0x02 /* The same for SERR forwarding */
 
#define PCI_BRIDGE_CTL_NO_ISA   0x04 /* Disable bridging of ISA ports */
 
#define PCI_BRIDGE_CTL_VGA   0x08 /* Forward VGA addresses */
 
#define PCI_BRIDGE_CTL_MASTER_ABORT   0x20 /* Report master aborts */
 
#define PCI_BRIDGE_CTL_BUS_RESET   0x40 /* Secondary bus reset */
 
#define PCI_BRIDGE_CTL_FAST_BACK   0x80 /* Fast Back2Back enabled on secondary interface */
 
#define PCI_CB_CAPABILITY_LIST   0x14
 
#define PCI_CB_SEC_STATUS   0x16 /* Secondary status */
 
#define PCI_CB_PRIMARY_BUS   0x18 /* PCI bus number */
 
#define PCI_CB_CARD_BUS   0x19 /* CardBus bus number */
 
#define PCI_CB_SUBORDINATE_BUS   0x1a /* Subordinate bus number */
 
#define PCI_CB_LATENCY_TIMER   0x1b /* CardBus latency timer */
 
#define PCI_CB_MEMORY_BASE_0   0x1c
 
#define PCI_CB_MEMORY_LIMIT_0   0x20
 
#define PCI_CB_MEMORY_BASE_1   0x24
 
#define PCI_CB_MEMORY_LIMIT_1   0x28
 
#define PCI_CB_IO_BASE_0   0x2c
 
#define PCI_CB_IO_BASE_0_HI   0x2e
 
#define PCI_CB_IO_LIMIT_0   0x30
 
#define PCI_CB_IO_LIMIT_0_HI   0x32
 
#define PCI_CB_IO_BASE_1   0x34
 
#define PCI_CB_IO_BASE_1_HI   0x36
 
#define PCI_CB_IO_LIMIT_1   0x38
 
#define PCI_CB_IO_LIMIT_1_HI   0x3a
 
#define PCI_CB_IO_RANGE_MASK   ~0x03
 
#define PCI_CB_BRIDGE_CONTROL   0x3e
 
#define PCI_CB_BRIDGE_CTL_PARITY   0x01 /* Similar to standard bridge control register */
 
#define PCI_CB_BRIDGE_CTL_SERR   0x02
 
#define PCI_CB_BRIDGE_CTL_ISA   0x04
 
#define PCI_CB_BRIDGE_CTL_VGA   0x08
 
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT   0x20
 
#define PCI_CB_BRIDGE_CTL_CB_RESET   0x40 /* CardBus reset */
 
#define PCI_CB_BRIDGE_CTL_16BIT_INT   0x80 /* Enable interrupt for 16-bit cards */
 
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0   0x100 /* Prefetch enable for both memory regions */
 
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1   0x200
 
#define PCI_CB_BRIDGE_CTL_POST_WRITES   0x400
 
#define PCI_CB_SUBSYSTEM_VENDOR_ID   0x40
 
#define PCI_CB_SUBSYSTEM_ID   0x42
 
#define PCI_CB_LEGACY_MODE_BASE   0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
 
#define PCI_CAP_LIST_ID   0 /* Capability ID */
 
#define PCI_CAP_ID_PM   0x01 /* Power Management */
 
#define PCI_CAP_ID_AGP   0x02 /* Accelerated Graphics Port */
 
#define PCI_CAP_ID_VPD   0x03 /* Vital Product Data */
 
#define PCI_CAP_ID_SLOTID   0x04 /* Slot Identification */
 
#define PCI_CAP_ID_MSI   0x05 /* Message Signalled Interrupts */
 
#define PCI_CAP_ID_CHSWP   0x06 /* CompactPCI HotSwap */
 
#define PCI_CAP_LIST_NEXT   1 /* Next capability in the list */
 
#define PCI_CAP_FLAGS   2 /* Capability defined flags (16 bits) */
 
#define PCI_CAP_SIZEOF   4
 
#define PCI_PM_PMC   2 /* PM Capabilities Register */
 
#define PCI_PM_CAP_VER_MASK   0x0007 /* Version */
 
#define PCI_PM_CAP_PME_CLOCK   0x0008 /* PME clock required */
 
#define PCI_PM_CAP_RESERVED   0x0010 /* Reserved field */
 
#define PCI_PM_CAP_DSI   0x0020 /* Device specific initialization */
 
#define PCI_PM_CAP_AUX_POWER   0x01C0 /* Auxiliary power support mask */
 
#define PCI_PM_CAP_D1   0x0200 /* D1 power state support */
 
#define PCI_PM_CAP_D2   0x0400 /* D2 power state support */
 
#define PCI_PM_CAP_PME   0x0800 /* PME pin supported */
 
#define PCI_PM_CAP_PME_MASK   0xF800 /* PME Mask of all supported states */
 
#define PCI_PM_CAP_PME_D0   0x0800 /* PME# from D0 */
 
#define PCI_PM_CAP_PME_D1   0x1000 /* PME# from D1 */
 
#define PCI_PM_CAP_PME_D2   0x2000 /* PME# from D2 */
 
#define PCI_PM_CAP_PME_D3   0x4000 /* PME# from D3 (hot) */
 
#define PCI_PM_CAP_PME_D3cold   0x8000 /* PME# from D3 (cold) */
 
#define PCI_PM_CTRL   4 /* PM control and status register */
 
#define PCI_PM_CTRL_STATE_MASK   0x0003 /* Current power state (D0 to D3) */
 
#define PCI_PM_CTRL_PME_ENABLE   0x0100 /* PME pin enable */
 
#define PCI_PM_CTRL_DATA_SEL_MASK   0x1e00 /* Data select (??) */
 
#define PCI_PM_CTRL_DATA_SCALE_MASK   0x6000 /* Data scale (??) */
 
#define PCI_PM_CTRL_PME_STATUS   0x8000 /* PME pin status */
 
#define PCI_PM_PPB_EXTENSIONS   6 /* PPB support extensions (??) */
 
#define PCI_PM_PPB_B2_B3   0x40 /* Stop clock when in D3hot (??) */
 
#define PCI_PM_BPCC_ENABLE   0x80 /* Bus power/clock control enable (??) */
 
#define PCI_PM_DATA_REGISTER   7 /* (??) */
 
#define PCI_PM_SIZEOF   8
 
#define PCI_AGP_VERSION   2 /* BCD version number */
 
#define PCI_AGP_RFU   3 /* Rest of capability flags */
 
#define PCI_AGP_STATUS   4 /* Status register */
 
#define PCI_AGP_STATUS_RQ_MASK   0xff000000 /* Maximum number of requests - 1 */
 
#define PCI_AGP_STATUS_SBA   0x0200 /* Sideband addressing supported */
 
#define PCI_AGP_STATUS_64BIT   0x0020 /* 64-bit addressing supported */
 
#define PCI_AGP_STATUS_FW   0x0010 /* FW transfers supported */
 
#define PCI_AGP_STATUS_RATE4   0x0004 /* 4x transfer rate supported */
 
#define PCI_AGP_STATUS_RATE2   0x0002 /* 2x transfer rate supported */
 
#define PCI_AGP_STATUS_RATE1   0x0001 /* 1x transfer rate supported */
 
#define PCI_AGP_COMMAND   8 /* Control register */
 
#define PCI_AGP_COMMAND_RQ_MASK   0xff000000 /* Master: Maximum number of requests */
 
#define PCI_AGP_COMMAND_SBA   0x0200 /* Sideband addressing enabled */
 
#define PCI_AGP_COMMAND_AGP   0x0100 /* Allow processing of AGP transactions */
 
#define PCI_AGP_COMMAND_64BIT   0x0020 /* Allow processing of 64-bit addresses */
 
#define PCI_AGP_COMMAND_FW   0x0010 /* Force FW transfers */
 
#define PCI_AGP_COMMAND_RATE4   0x0004 /* Use 4x rate */
 
#define PCI_AGP_COMMAND_RATE2   0x0002 /* Use 4x rate */
 
#define PCI_AGP_COMMAND_RATE1   0x0001 /* Use 4x rate */
 
#define PCI_AGP_SIZEOF   12
 
#define PCI_SID_ESR   2 /* Expansion Slot Register */
 
#define PCI_SID_ESR_NSLOTS   0x1f /* Number of expansion slots available */
 
#define PCI_SID_ESR_FIC   0x20 /* First In Chassis Flag */
 
#define PCI_SID_CHASSIS_NR   3 /* Chassis Number */
 
#define PCI_MSI_FLAGS   2 /* Various flags */
 
#define PCI_MSI_FLAGS_64BIT   0x80 /* 64-bit addresses allowed */
 
#define PCI_MSI_FLAGS_QSIZE   0x70 /* Message queue size configured */
 
#define PCI_MSI_FLAGS_QMASK   0x0e /* Maximum queue size available */
 
#define PCI_MSI_FLAGS_ENABLE   0x01 /* MSI feature enabled */
 
#define PCI_MSI_RFU   3 /* Rest of capability flags */
 
#define PCI_MSI_ADDRESS_LO   4 /* Lower 32 bits */
 
#define PCI_MSI_ADDRESS_HI   8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
 
#define PCI_MSI_DATA_32   8 /* 16 bits of data for 32-bit devices */
 
#define PCI_MSI_DATA_64   12 /* 16 bits of data for 64-bit devices */
 
#define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
 
#define PCI_SLOT(devfn)   (((devfn) >> 3) & 0x1f)
 
#define PCI_FUNC(devfn)   ((devfn) & 0x07)
 
#define PCI_ROM_RESOURCE   6
 
#define PCI_BRIDGE_RESOURCES   7
 
#define PCI_NUM_RESOURCES   11
 
#define PCI_REGION_FLAG_MASK   0x0f /* These bits of resource flags tell us the PCI region flags */
 

Macro Definition Documentation

◆ PCI_AGP_COMMAND

#define PCI_AGP_COMMAND   8 /* Control register */

Definition at line 243 of file pcidef.h.

◆ PCI_AGP_COMMAND_64BIT

#define PCI_AGP_COMMAND_64BIT   0x0020 /* Allow processing of 64-bit addresses */

Definition at line 247 of file pcidef.h.

◆ PCI_AGP_COMMAND_AGP

#define PCI_AGP_COMMAND_AGP   0x0100 /* Allow processing of AGP transactions */

Definition at line 246 of file pcidef.h.

◆ PCI_AGP_COMMAND_FW

#define PCI_AGP_COMMAND_FW   0x0010 /* Force FW transfers */

Definition at line 248 of file pcidef.h.

◆ PCI_AGP_COMMAND_RATE1

#define PCI_AGP_COMMAND_RATE1   0x0001 /* Use 4x rate */

Definition at line 251 of file pcidef.h.

◆ PCI_AGP_COMMAND_RATE2

#define PCI_AGP_COMMAND_RATE2   0x0002 /* Use 4x rate */

Definition at line 250 of file pcidef.h.

◆ PCI_AGP_COMMAND_RATE4

#define PCI_AGP_COMMAND_RATE4   0x0004 /* Use 4x rate */

Definition at line 249 of file pcidef.h.

◆ PCI_AGP_COMMAND_RQ_MASK

#define PCI_AGP_COMMAND_RQ_MASK   0xff000000 /* Master: Maximum number of requests */

Definition at line 244 of file pcidef.h.

◆ PCI_AGP_COMMAND_SBA

#define PCI_AGP_COMMAND_SBA   0x0200 /* Sideband addressing enabled */

Definition at line 245 of file pcidef.h.

◆ PCI_AGP_RFU

#define PCI_AGP_RFU   3 /* Rest of capability flags */

Definition at line 234 of file pcidef.h.

◆ PCI_AGP_SIZEOF

#define PCI_AGP_SIZEOF   12

Definition at line 252 of file pcidef.h.

◆ PCI_AGP_STATUS

#define PCI_AGP_STATUS   4 /* Status register */

Definition at line 235 of file pcidef.h.

◆ PCI_AGP_STATUS_64BIT

#define PCI_AGP_STATUS_64BIT   0x0020 /* 64-bit addressing supported */

Definition at line 238 of file pcidef.h.

◆ PCI_AGP_STATUS_FW

#define PCI_AGP_STATUS_FW   0x0010 /* FW transfers supported */

Definition at line 239 of file pcidef.h.

◆ PCI_AGP_STATUS_RATE1

#define PCI_AGP_STATUS_RATE1   0x0001 /* 1x transfer rate supported */

Definition at line 242 of file pcidef.h.

◆ PCI_AGP_STATUS_RATE2

#define PCI_AGP_STATUS_RATE2   0x0002 /* 2x transfer rate supported */

Definition at line 241 of file pcidef.h.

◆ PCI_AGP_STATUS_RATE4

#define PCI_AGP_STATUS_RATE4   0x0004 /* 4x transfer rate supported */

Definition at line 240 of file pcidef.h.

◆ PCI_AGP_STATUS_RQ_MASK

#define PCI_AGP_STATUS_RQ_MASK   0xff000000 /* Maximum number of requests - 1 */

Definition at line 236 of file pcidef.h.

◆ PCI_AGP_STATUS_SBA

#define PCI_AGP_STATUS_SBA   0x0200 /* Sideband addressing supported */

Definition at line 237 of file pcidef.h.

◆ PCI_AGP_VERSION

#define PCI_AGP_VERSION   2 /* BCD version number */

Definition at line 233 of file pcidef.h.

◆ PCI_BASE_ADDRESS_0

#define PCI_BASE_ADDRESS_0   0x10 /* 32 bits */

Definition at line 78 of file pcidef.h.

◆ PCI_BASE_ADDRESS_1

#define PCI_BASE_ADDRESS_1   0x14 /* 32 bits [htype 0,1 only] */

Definition at line 79 of file pcidef.h.

◆ PCI_BASE_ADDRESS_2

#define PCI_BASE_ADDRESS_2   0x18 /* 32 bits [htype 0 only] */

Definition at line 80 of file pcidef.h.

◆ PCI_BASE_ADDRESS_3

#define PCI_BASE_ADDRESS_3   0x1c /* 32 bits */

Definition at line 81 of file pcidef.h.

◆ PCI_BASE_ADDRESS_4

#define PCI_BASE_ADDRESS_4   0x20 /* 32 bits */

Definition at line 82 of file pcidef.h.

◆ PCI_BASE_ADDRESS_5

#define PCI_BASE_ADDRESS_5   0x24 /* 32 bits */

Definition at line 83 of file pcidef.h.

◆ PCI_BASE_ADDRESS_IO_MASK

#define PCI_BASE_ADDRESS_IO_MASK   (~0x03UL)

Definition at line 93 of file pcidef.h.

◆ PCI_BASE_ADDRESS_MEM_MASK

#define PCI_BASE_ADDRESS_MEM_MASK   (~0x0fUL)

Definition at line 92 of file pcidef.h.

◆ PCI_BASE_ADDRESS_MEM_PREFETCH

#define PCI_BASE_ADDRESS_MEM_PREFETCH   0x08 /* prefetchable? */

Definition at line 91 of file pcidef.h.

◆ PCI_BASE_ADDRESS_MEM_TYPE_1M

#define PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02 /* Below 1M [obsolete] */

Definition at line 89 of file pcidef.h.

◆ PCI_BASE_ADDRESS_MEM_TYPE_32

#define PCI_BASE_ADDRESS_MEM_TYPE_32   0x00 /* 32 bit address */

Definition at line 88 of file pcidef.h.

◆ PCI_BASE_ADDRESS_MEM_TYPE_64

#define PCI_BASE_ADDRESS_MEM_TYPE_64   0x04 /* 64 bit address */

Definition at line 90 of file pcidef.h.

◆ PCI_BASE_ADDRESS_MEM_TYPE_MASK

#define PCI_BASE_ADDRESS_MEM_TYPE_MASK   0x06

Definition at line 87 of file pcidef.h.

◆ PCI_BASE_ADDRESS_SPACE

#define PCI_BASE_ADDRESS_SPACE   0x01 /* 0 = memory, 1 = I/O */

Definition at line 84 of file pcidef.h.

◆ PCI_BASE_ADDRESS_SPACE_IO

#define PCI_BASE_ADDRESS_SPACE_IO   0x01

Definition at line 85 of file pcidef.h.

◆ PCI_BASE_ADDRESS_SPACE_MEMORY

#define PCI_BASE_ADDRESS_SPACE_MEMORY   0x00

Definition at line 86 of file pcidef.h.

◆ PCI_BIST

#define PCI_BIST   0x0f /* 8 bits */

Definition at line 67 of file pcidef.h.

◆ PCI_BIST_CAPABLE

#define PCI_BIST_CAPABLE   0x80 /* 1 if BIST capable */

Definition at line 70 of file pcidef.h.

◆ PCI_BIST_CODE_MASK

#define PCI_BIST_CODE_MASK   0x0f /* Return result */

Definition at line 68 of file pcidef.h.

◆ PCI_BIST_START

#define PCI_BIST_START   0x40 /* 1 to start BIST, 2 secs or less */

Definition at line 69 of file pcidef.h.

◆ PCI_BRIDGE_CONTROL

#define PCI_BRIDGE_CONTROL   0x3e

Definition at line 142 of file pcidef.h.

◆ PCI_BRIDGE_CTL_BUS_RESET

#define PCI_BRIDGE_CTL_BUS_RESET   0x40 /* Secondary bus reset */

Definition at line 148 of file pcidef.h.

◆ PCI_BRIDGE_CTL_FAST_BACK

#define PCI_BRIDGE_CTL_FAST_BACK   0x80 /* Fast Back2Back enabled on secondary interface */

Definition at line 149 of file pcidef.h.

◆ PCI_BRIDGE_CTL_MASTER_ABORT

#define PCI_BRIDGE_CTL_MASTER_ABORT   0x20 /* Report master aborts */

Definition at line 147 of file pcidef.h.

◆ PCI_BRIDGE_CTL_NO_ISA

#define PCI_BRIDGE_CTL_NO_ISA   0x04 /* Disable bridging of ISA ports */

Definition at line 145 of file pcidef.h.

◆ PCI_BRIDGE_CTL_PARITY

#define PCI_BRIDGE_CTL_PARITY   0x01 /* Enable parity detection on secondary interface */

Definition at line 143 of file pcidef.h.

◆ PCI_BRIDGE_CTL_SERR

#define PCI_BRIDGE_CTL_SERR   0x02 /* The same for SERR forwarding */

Definition at line 144 of file pcidef.h.

◆ PCI_BRIDGE_CTL_VGA

#define PCI_BRIDGE_CTL_VGA   0x08 /* Forward VGA addresses */

Definition at line 146 of file pcidef.h.

◆ PCI_BRIDGE_RESOURCES

#define PCI_BRIDGE_RESOURCES   7

Definition at line 296 of file pcidef.h.

◆ PCI_CACHE_LINE_SIZE

#define PCI_CACHE_LINE_SIZE   0x0c /* 8 bits */

Definition at line 60 of file pcidef.h.

◆ PCI_CAP_FLAGS

#define PCI_CAP_FLAGS   2 /* Capability defined flags (16 bits) */

Definition at line 199 of file pcidef.h.

◆ PCI_CAP_ID_AGP

#define PCI_CAP_ID_AGP   0x02 /* Accelerated Graphics Port */

Definition at line 193 of file pcidef.h.

◆ PCI_CAP_ID_CHSWP

#define PCI_CAP_ID_CHSWP   0x06 /* CompactPCI HotSwap */

Definition at line 197 of file pcidef.h.

◆ PCI_CAP_ID_MSI

#define PCI_CAP_ID_MSI   0x05 /* Message Signalled Interrupts */

Definition at line 196 of file pcidef.h.

◆ PCI_CAP_ID_PM

#define PCI_CAP_ID_PM   0x01 /* Power Management */

Definition at line 192 of file pcidef.h.

◆ PCI_CAP_ID_SLOTID

#define PCI_CAP_ID_SLOTID   0x04 /* Slot Identification */

Definition at line 195 of file pcidef.h.

◆ PCI_CAP_ID_VPD

#define PCI_CAP_ID_VPD   0x03 /* Vital Product Data */

Definition at line 194 of file pcidef.h.

◆ PCI_CAP_LIST_ID

#define PCI_CAP_LIST_ID   0 /* Capability ID */

Definition at line 191 of file pcidef.h.

◆ PCI_CAP_LIST_NEXT

#define PCI_CAP_LIST_NEXT   1 /* Next capability in the list */

Definition at line 198 of file pcidef.h.

◆ PCI_CAP_SIZEOF

#define PCI_CAP_SIZEOF   4

Definition at line 200 of file pcidef.h.

◆ PCI_CAPABILITY_LIST

#define PCI_CAPABILITY_LIST   0x34 /* Offset of first capability list entry */

Definition at line 104 of file pcidef.h.

◆ PCI_CARDBUS_CIS

#define PCI_CARDBUS_CIS   0x28

Definition at line 97 of file pcidef.h.

◆ PCI_CB_BRIDGE_CONTROL

#define PCI_CB_BRIDGE_CONTROL   0x3e

Definition at line 173 of file pcidef.h.

◆ PCI_CB_BRIDGE_CTL_16BIT_INT

#define PCI_CB_BRIDGE_CTL_16BIT_INT   0x80 /* Enable interrupt for 16-bit cards */

Definition at line 180 of file pcidef.h.

◆ PCI_CB_BRIDGE_CTL_CB_RESET

#define PCI_CB_BRIDGE_CTL_CB_RESET   0x40 /* CardBus reset */

Definition at line 179 of file pcidef.h.

◆ PCI_CB_BRIDGE_CTL_ISA

#define PCI_CB_BRIDGE_CTL_ISA   0x04

Definition at line 176 of file pcidef.h.

◆ PCI_CB_BRIDGE_CTL_MASTER_ABORT

#define PCI_CB_BRIDGE_CTL_MASTER_ABORT   0x20

Definition at line 178 of file pcidef.h.

◆ PCI_CB_BRIDGE_CTL_PARITY

#define PCI_CB_BRIDGE_CTL_PARITY   0x01 /* Similar to standard bridge control register */

Definition at line 174 of file pcidef.h.

◆ PCI_CB_BRIDGE_CTL_POST_WRITES

#define PCI_CB_BRIDGE_CTL_POST_WRITES   0x400

Definition at line 183 of file pcidef.h.

◆ PCI_CB_BRIDGE_CTL_PREFETCH_MEM0

#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0   0x100 /* Prefetch enable for both memory regions */

Definition at line 181 of file pcidef.h.

◆ PCI_CB_BRIDGE_CTL_PREFETCH_MEM1

#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1   0x200

Definition at line 182 of file pcidef.h.

◆ PCI_CB_BRIDGE_CTL_SERR

#define PCI_CB_BRIDGE_CTL_SERR   0x02

Definition at line 175 of file pcidef.h.

◆ PCI_CB_BRIDGE_CTL_VGA

#define PCI_CB_BRIDGE_CTL_VGA   0x08

Definition at line 177 of file pcidef.h.

◆ PCI_CB_CAPABILITY_LIST

#define PCI_CB_CAPABILITY_LIST   0x14

Definition at line 152 of file pcidef.h.

◆ PCI_CB_CARD_BUS

#define PCI_CB_CARD_BUS   0x19 /* CardBus bus number */

Definition at line 156 of file pcidef.h.

◆ PCI_CB_IO_BASE_0

#define PCI_CB_IO_BASE_0   0x2c

Definition at line 163 of file pcidef.h.

◆ PCI_CB_IO_BASE_0_HI

#define PCI_CB_IO_BASE_0_HI   0x2e

Definition at line 164 of file pcidef.h.

◆ PCI_CB_IO_BASE_1

#define PCI_CB_IO_BASE_1   0x34

Definition at line 167 of file pcidef.h.

◆ PCI_CB_IO_BASE_1_HI

#define PCI_CB_IO_BASE_1_HI   0x36

Definition at line 168 of file pcidef.h.

◆ PCI_CB_IO_LIMIT_0

#define PCI_CB_IO_LIMIT_0   0x30

Definition at line 165 of file pcidef.h.

◆ PCI_CB_IO_LIMIT_0_HI

#define PCI_CB_IO_LIMIT_0_HI   0x32

Definition at line 166 of file pcidef.h.

◆ PCI_CB_IO_LIMIT_1

#define PCI_CB_IO_LIMIT_1   0x38

Definition at line 169 of file pcidef.h.

◆ PCI_CB_IO_LIMIT_1_HI

#define PCI_CB_IO_LIMIT_1_HI   0x3a

Definition at line 170 of file pcidef.h.

◆ PCI_CB_IO_RANGE_MASK

#define PCI_CB_IO_RANGE_MASK   ~0x03

Definition at line 171 of file pcidef.h.

◆ PCI_CB_LATENCY_TIMER

#define PCI_CB_LATENCY_TIMER   0x1b /* CardBus latency timer */

Definition at line 158 of file pcidef.h.

◆ PCI_CB_LEGACY_MODE_BASE

#define PCI_CB_LEGACY_MODE_BASE   0x44 /* 16-bit PC Card legacy mode base address (ExCa) */

Definition at line 186 of file pcidef.h.

◆ PCI_CB_MEMORY_BASE_0

#define PCI_CB_MEMORY_BASE_0   0x1c

Definition at line 159 of file pcidef.h.

◆ PCI_CB_MEMORY_BASE_1

#define PCI_CB_MEMORY_BASE_1   0x24

Definition at line 161 of file pcidef.h.

◆ PCI_CB_MEMORY_LIMIT_0

#define PCI_CB_MEMORY_LIMIT_0   0x20

Definition at line 160 of file pcidef.h.

◆ PCI_CB_MEMORY_LIMIT_1

#define PCI_CB_MEMORY_LIMIT_1   0x28

Definition at line 162 of file pcidef.h.

◆ PCI_CB_PRIMARY_BUS

#define PCI_CB_PRIMARY_BUS   0x18 /* PCI bus number */

Definition at line 155 of file pcidef.h.

◆ PCI_CB_SEC_STATUS

#define PCI_CB_SEC_STATUS   0x16 /* Secondary status */

Definition at line 154 of file pcidef.h.

◆ PCI_CB_SUBORDINATE_BUS

#define PCI_CB_SUBORDINATE_BUS   0x1a /* Subordinate bus number */

Definition at line 157 of file pcidef.h.

◆ PCI_CB_SUBSYSTEM_ID

#define PCI_CB_SUBSYSTEM_ID   0x42

Definition at line 185 of file pcidef.h.

◆ PCI_CB_SUBSYSTEM_VENDOR_ID

#define PCI_CB_SUBSYSTEM_VENDOR_ID   0x40

Definition at line 184 of file pcidef.h.

◆ PCI_CLASS_DEVICE

#define PCI_CLASS_DEVICE   0x0a /* Device class */

Definition at line 58 of file pcidef.h.

◆ PCI_CLASS_PROG

#define PCI_CLASS_PROG   0x09 /* Reg. Level Programming Interface */

Definition at line 57 of file pcidef.h.

◆ PCI_CLASS_REVISION

#define PCI_CLASS_REVISION
Value:
0x08 /* High 24 bits are class, low 8
revision */

Definition at line 54 of file pcidef.h.

◆ PCI_COMMAND

#define PCI_COMMAND   0x04 /* 16 bits */

Definition at line 26 of file pcidef.h.

◆ PCI_COMMAND_FAST_BACK

#define PCI_COMMAND_FAST_BACK   0x200 /* Enable back-to-back writes */

Definition at line 36 of file pcidef.h.

◆ PCI_COMMAND_INVALIDATE

#define PCI_COMMAND_INVALIDATE   0x10 /* Use memory write and invalidate */

Definition at line 31 of file pcidef.h.

◆ PCI_COMMAND_IO

#define PCI_COMMAND_IO   0x1 /* Enable response in I/O space */

Definition at line 27 of file pcidef.h.

◆ PCI_COMMAND_MASTER

#define PCI_COMMAND_MASTER   0x4 /* Enable bus mastering */

Definition at line 29 of file pcidef.h.

◆ PCI_COMMAND_MEMORY

#define PCI_COMMAND_MEMORY   0x2 /* Enable response in Memory space */

Definition at line 28 of file pcidef.h.

◆ PCI_COMMAND_PARITY

#define PCI_COMMAND_PARITY   0x40 /* Enable parity checking */

Definition at line 33 of file pcidef.h.

◆ PCI_COMMAND_SERR

#define PCI_COMMAND_SERR   0x100 /* Enable SERR */

Definition at line 35 of file pcidef.h.

◆ PCI_COMMAND_SPECIAL

#define PCI_COMMAND_SPECIAL   0x8 /* Enable response to special cycles */

Definition at line 30 of file pcidef.h.

◆ PCI_COMMAND_VGA_PALETTE

#define PCI_COMMAND_VGA_PALETTE   0x20 /* Enable palette snooping */

Definition at line 32 of file pcidef.h.

◆ PCI_COMMAND_WAIT

#define PCI_COMMAND_WAIT   0x80 /* Enable address/data stepping */

Definition at line 34 of file pcidef.h.

◆ PCI_DEVFN

#define PCI_DEVFN (   slot,
  func 
)    ((((slot) & 0x1f) << 3) | ((func) & 0x07))

Definition at line 282 of file pcidef.h.

◆ PCI_DEVICE_ID

#define PCI_DEVICE_ID   0x02 /* 16 bits */

Definition at line 25 of file pcidef.h.

◆ PCI_FUNC

#define PCI_FUNC (   devfn)    ((devfn) & 0x07)

Definition at line 284 of file pcidef.h.

◆ PCI_HEADER_TYPE

#define PCI_HEADER_TYPE   0x0e /* 8 bits */

Definition at line 62 of file pcidef.h.

◆ PCI_HEADER_TYPE_BRIDGE

#define PCI_HEADER_TYPE_BRIDGE   1

Definition at line 64 of file pcidef.h.

◆ PCI_HEADER_TYPE_CARDBUS

#define PCI_HEADER_TYPE_CARDBUS   2

Definition at line 65 of file pcidef.h.

◆ PCI_HEADER_TYPE_NORMAL

#define PCI_HEADER_TYPE_NORMAL   0

Definition at line 63 of file pcidef.h.

◆ PCI_INTERRUPT_LINE

#define PCI_INTERRUPT_LINE   0x3c /* 8 bits */

Definition at line 107 of file pcidef.h.

◆ PCI_INTERRUPT_PIN

#define PCI_INTERRUPT_PIN   0x3d /* 8 bits */

Definition at line 108 of file pcidef.h.

◆ PCI_IO_BASE

#define PCI_IO_BASE   0x1c /* I/O range behind the bridge */

Definition at line 117 of file pcidef.h.

◆ PCI_IO_BASE_UPPER16

#define PCI_IO_BASE_UPPER16   0x30 /* Upper half of I/O addresses */

Definition at line 136 of file pcidef.h.

◆ PCI_IO_LIMIT

#define PCI_IO_LIMIT   0x1d

Definition at line 118 of file pcidef.h.

◆ PCI_IO_LIMIT_UPPER16

#define PCI_IO_LIMIT_UPPER16   0x32

Definition at line 137 of file pcidef.h.

◆ PCI_IO_RANGE_MASK

#define PCI_IO_RANGE_MASK   ~0x0f

Definition at line 122 of file pcidef.h.

◆ PCI_IO_RANGE_TYPE_16

#define PCI_IO_RANGE_TYPE_16   0x00

Definition at line 120 of file pcidef.h.

◆ PCI_IO_RANGE_TYPE_32

#define PCI_IO_RANGE_TYPE_32   0x01

Definition at line 121 of file pcidef.h.

◆ PCI_IO_RANGE_TYPE_MASK

#define PCI_IO_RANGE_TYPE_MASK   0x0f /* I/O bridging type */

Definition at line 119 of file pcidef.h.

◆ PCI_LATENCY_TIMER

#define PCI_LATENCY_TIMER   0x0d /* 8 bits */

Definition at line 61 of file pcidef.h.

◆ PCI_MAX_LAT

#define PCI_MAX_LAT   0x3f /* 8 bits */

Definition at line 110 of file pcidef.h.

◆ PCI_MEMORY_BASE

#define PCI_MEMORY_BASE   0x20 /* Memory range behind */

Definition at line 124 of file pcidef.h.

◆ PCI_MEMORY_LIMIT

#define PCI_MEMORY_LIMIT   0x22

Definition at line 125 of file pcidef.h.

◆ PCI_MEMORY_RANGE_MASK

#define PCI_MEMORY_RANGE_MASK   ~0x0f

Definition at line 127 of file pcidef.h.

◆ PCI_MEMORY_RANGE_TYPE_MASK

#define PCI_MEMORY_RANGE_TYPE_MASK   0x0f

Definition at line 126 of file pcidef.h.

◆ PCI_MIN_GNT

#define PCI_MIN_GNT   0x3e /* 8 bits */

Definition at line 109 of file pcidef.h.

◆ PCI_MSI_ADDRESS_HI

#define PCI_MSI_ADDRESS_HI   8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */

Definition at line 270 of file pcidef.h.

◆ PCI_MSI_ADDRESS_LO

#define PCI_MSI_ADDRESS_LO   4 /* Lower 32 bits */

Definition at line 269 of file pcidef.h.

◆ PCI_MSI_DATA_32

#define PCI_MSI_DATA_32   8 /* 16 bits of data for 32-bit devices */

Definition at line 271 of file pcidef.h.

◆ PCI_MSI_DATA_64

#define PCI_MSI_DATA_64   12 /* 16 bits of data for 64-bit devices */

Definition at line 272 of file pcidef.h.

◆ PCI_MSI_FLAGS

#define PCI_MSI_FLAGS   2 /* Various flags */

Definition at line 263 of file pcidef.h.

◆ PCI_MSI_FLAGS_64BIT

#define PCI_MSI_FLAGS_64BIT   0x80 /* 64-bit addresses allowed */

Definition at line 264 of file pcidef.h.

◆ PCI_MSI_FLAGS_ENABLE

#define PCI_MSI_FLAGS_ENABLE   0x01 /* MSI feature enabled */

Definition at line 267 of file pcidef.h.

◆ PCI_MSI_FLAGS_QMASK

#define PCI_MSI_FLAGS_QMASK   0x0e /* Maximum queue size available */

Definition at line 266 of file pcidef.h.

◆ PCI_MSI_FLAGS_QSIZE

#define PCI_MSI_FLAGS_QSIZE   0x70 /* Message queue size configured */

Definition at line 265 of file pcidef.h.

◆ PCI_MSI_RFU

#define PCI_MSI_RFU   3 /* Rest of capability flags */

Definition at line 268 of file pcidef.h.

◆ PCI_NUM_RESOURCES

#define PCI_NUM_RESOURCES   11

Definition at line 297 of file pcidef.h.

◆ PCI_PM_BPCC_ENABLE

#define PCI_PM_BPCC_ENABLE   0x80 /* Bus power/clock control enable (??) */

Definition at line 227 of file pcidef.h.

◆ PCI_PM_CAP_AUX_POWER

#define PCI_PM_CAP_AUX_POWER   0x01C0 /* Auxiliary power support mask */

Definition at line 209 of file pcidef.h.

◆ PCI_PM_CAP_D1

#define PCI_PM_CAP_D1   0x0200 /* D1 power state support */

Definition at line 210 of file pcidef.h.

◆ PCI_PM_CAP_D2

#define PCI_PM_CAP_D2   0x0400 /* D2 power state support */

Definition at line 211 of file pcidef.h.

◆ PCI_PM_CAP_DSI

#define PCI_PM_CAP_DSI   0x0020 /* Device specific initialization */

Definition at line 208 of file pcidef.h.

◆ PCI_PM_CAP_PME

#define PCI_PM_CAP_PME   0x0800 /* PME pin supported */

Definition at line 212 of file pcidef.h.

◆ PCI_PM_CAP_PME_CLOCK

#define PCI_PM_CAP_PME_CLOCK   0x0008 /* PME clock required */

Definition at line 206 of file pcidef.h.

◆ PCI_PM_CAP_PME_D0

#define PCI_PM_CAP_PME_D0   0x0800 /* PME# from D0 */

Definition at line 214 of file pcidef.h.

◆ PCI_PM_CAP_PME_D1

#define PCI_PM_CAP_PME_D1   0x1000 /* PME# from D1 */

Definition at line 215 of file pcidef.h.

◆ PCI_PM_CAP_PME_D2

#define PCI_PM_CAP_PME_D2   0x2000 /* PME# from D2 */

Definition at line 216 of file pcidef.h.

◆ PCI_PM_CAP_PME_D3

#define PCI_PM_CAP_PME_D3   0x4000 /* PME# from D3 (hot) */

Definition at line 217 of file pcidef.h.

◆ PCI_PM_CAP_PME_D3cold

#define PCI_PM_CAP_PME_D3cold   0x8000 /* PME# from D3 (cold) */

Definition at line 218 of file pcidef.h.

◆ PCI_PM_CAP_PME_MASK

#define PCI_PM_CAP_PME_MASK   0xF800 /* PME Mask of all supported states */

Definition at line 213 of file pcidef.h.

◆ PCI_PM_CAP_RESERVED

#define PCI_PM_CAP_RESERVED   0x0010 /* Reserved field */

Definition at line 207 of file pcidef.h.

◆ PCI_PM_CAP_VER_MASK

#define PCI_PM_CAP_VER_MASK   0x0007 /* Version */

Definition at line 205 of file pcidef.h.

◆ PCI_PM_CTRL

#define PCI_PM_CTRL   4 /* PM control and status register */

Definition at line 219 of file pcidef.h.

◆ PCI_PM_CTRL_DATA_SCALE_MASK

#define PCI_PM_CTRL_DATA_SCALE_MASK   0x6000 /* Data scale (??) */

Definition at line 223 of file pcidef.h.

◆ PCI_PM_CTRL_DATA_SEL_MASK

#define PCI_PM_CTRL_DATA_SEL_MASK   0x1e00 /* Data select (??) */

Definition at line 222 of file pcidef.h.

◆ PCI_PM_CTRL_PME_ENABLE

#define PCI_PM_CTRL_PME_ENABLE   0x0100 /* PME pin enable */

Definition at line 221 of file pcidef.h.

◆ PCI_PM_CTRL_PME_STATUS

#define PCI_PM_CTRL_PME_STATUS   0x8000 /* PME pin status */

Definition at line 224 of file pcidef.h.

◆ PCI_PM_CTRL_STATE_MASK

#define PCI_PM_CTRL_STATE_MASK   0x0003 /* Current power state (D0 to D3) */

Definition at line 220 of file pcidef.h.

◆ PCI_PM_DATA_REGISTER

#define PCI_PM_DATA_REGISTER   7 /* (??) */

Definition at line 228 of file pcidef.h.

◆ PCI_PM_PMC

#define PCI_PM_PMC   2 /* PM Capabilities Register */

Definition at line 204 of file pcidef.h.

◆ PCI_PM_PPB_B2_B3

#define PCI_PM_PPB_B2_B3   0x40 /* Stop clock when in D3hot (??) */

Definition at line 226 of file pcidef.h.

◆ PCI_PM_PPB_EXTENSIONS

#define PCI_PM_PPB_EXTENSIONS   6 /* PPB support extensions (??) */

Definition at line 225 of file pcidef.h.

◆ PCI_PM_SIZEOF

#define PCI_PM_SIZEOF   8

Definition at line 229 of file pcidef.h.

◆ PCI_PREF_BASE_UPPER32

#define PCI_PREF_BASE_UPPER32   0x28 /* Upper half of prefetchable memory range */

Definition at line 134 of file pcidef.h.

◆ PCI_PREF_LIMIT_UPPER32

#define PCI_PREF_LIMIT_UPPER32   0x2c

Definition at line 135 of file pcidef.h.

◆ PCI_PREF_MEMORY_BASE

#define PCI_PREF_MEMORY_BASE   0x24 /* Prefetchable memory range behind */

Definition at line 128 of file pcidef.h.

◆ PCI_PREF_MEMORY_LIMIT

#define PCI_PREF_MEMORY_LIMIT   0x26

Definition at line 129 of file pcidef.h.

◆ PCI_PREF_RANGE_MASK

#define PCI_PREF_RANGE_MASK   ~0x0f

Definition at line 133 of file pcidef.h.

◆ PCI_PREF_RANGE_TYPE_32

#define PCI_PREF_RANGE_TYPE_32   0x00

Definition at line 131 of file pcidef.h.

◆ PCI_PREF_RANGE_TYPE_64

#define PCI_PREF_RANGE_TYPE_64   0x01

Definition at line 132 of file pcidef.h.

◆ PCI_PREF_RANGE_TYPE_MASK

#define PCI_PREF_RANGE_TYPE_MASK   0x0f

Definition at line 130 of file pcidef.h.

◆ PCI_PRIMARY_BUS

#define PCI_PRIMARY_BUS   0x18 /* Primary bus number */

Definition at line 113 of file pcidef.h.

◆ PCI_REGION_FLAG_MASK

#define PCI_REGION_FLAG_MASK   0x0f /* These bits of resource flags tell us the PCI region flags */

Definition at line 299 of file pcidef.h.

◆ PCI_REVISION_ID

#define PCI_REVISION_ID   0x08 /* Revision ID */

Definition at line 56 of file pcidef.h.

◆ PCI_ROM_ADDRESS

#define PCI_ROM_ADDRESS   0x30 /* Bits 31..11 are address, 10..1 reserved */

Definition at line 100 of file pcidef.h.

◆ PCI_ROM_ADDRESS1

#define PCI_ROM_ADDRESS1   0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */

Definition at line 140 of file pcidef.h.

◆ PCI_ROM_ADDRESS_ENABLE

#define PCI_ROM_ADDRESS_ENABLE   0x01

Definition at line 101 of file pcidef.h.

◆ PCI_ROM_ADDRESS_MASK

#define PCI_ROM_ADDRESS_MASK   (~0x7ffUL)

Definition at line 102 of file pcidef.h.

◆ PCI_ROM_RESOURCE

#define PCI_ROM_RESOURCE   6

Definition at line 295 of file pcidef.h.

◆ PCI_SEC_LATENCY_TIMER

#define PCI_SEC_LATENCY_TIMER   0x1b /* Latency timer for secondary interface */

Definition at line 116 of file pcidef.h.

◆ PCI_SEC_STATUS

#define PCI_SEC_STATUS   0x1e /* Secondary status register, only bit 14 used */

Definition at line 123 of file pcidef.h.

◆ PCI_SECONDARY_BUS

#define PCI_SECONDARY_BUS   0x19 /* Secondary bus number */

Definition at line 114 of file pcidef.h.

◆ PCI_SID_CHASSIS_NR

#define PCI_SID_CHASSIS_NR   3 /* Chassis Number */

Definition at line 259 of file pcidef.h.

◆ PCI_SID_ESR

#define PCI_SID_ESR   2 /* Expansion Slot Register */

Definition at line 256 of file pcidef.h.

◆ PCI_SID_ESR_FIC

#define PCI_SID_ESR_FIC   0x20 /* First In Chassis Flag */

Definition at line 258 of file pcidef.h.

◆ PCI_SID_ESR_NSLOTS

#define PCI_SID_ESR_NSLOTS   0x1f /* Number of expansion slots available */

Definition at line 257 of file pcidef.h.

◆ PCI_SLOT

#define PCI_SLOT (   devfn)    (((devfn) >> 3) & 0x1f)

Definition at line 283 of file pcidef.h.

◆ PCI_STATUS

#define PCI_STATUS   0x06 /* 16 bits */

Definition at line 38 of file pcidef.h.

◆ PCI_STATUS_66MHZ

#define PCI_STATUS_66MHZ   0x20 /* Support 66 Mhz PCI 2.1 bus */

Definition at line 40 of file pcidef.h.

◆ PCI_STATUS_CAP_LIST

#define PCI_STATUS_CAP_LIST   0x10 /* Support Capability List */

Definition at line 39 of file pcidef.h.

◆ PCI_STATUS_DETECTED_PARITY

#define PCI_STATUS_DETECTED_PARITY   0x8000 /* Set on parity error */

Definition at line 52 of file pcidef.h.

◆ PCI_STATUS_DEVSEL_FAST

#define PCI_STATUS_DEVSEL_FAST   0x000

Definition at line 45 of file pcidef.h.

◆ PCI_STATUS_DEVSEL_MASK

#define PCI_STATUS_DEVSEL_MASK   0x600 /* DEVSEL timing */

Definition at line 44 of file pcidef.h.

◆ PCI_STATUS_DEVSEL_MEDIUM

#define PCI_STATUS_DEVSEL_MEDIUM   0x200

Definition at line 46 of file pcidef.h.

◆ PCI_STATUS_DEVSEL_SLOW

#define PCI_STATUS_DEVSEL_SLOW   0x400

Definition at line 47 of file pcidef.h.

◆ PCI_STATUS_FAST_BACK

#define PCI_STATUS_FAST_BACK   0x80 /* Accept fast-back to back */

Definition at line 42 of file pcidef.h.

◆ PCI_STATUS_PARITY

#define PCI_STATUS_PARITY   0x100 /* Detected parity error */

Definition at line 43 of file pcidef.h.

◆ PCI_STATUS_REC_MASTER_ABORT

#define PCI_STATUS_REC_MASTER_ABORT   0x2000 /* Set on master abort */

Definition at line 50 of file pcidef.h.

◆ PCI_STATUS_REC_TARGET_ABORT

#define PCI_STATUS_REC_TARGET_ABORT   0x1000 /* Master ack of " */

Definition at line 49 of file pcidef.h.

◆ PCI_STATUS_SIG_SYSTEM_ERROR

#define PCI_STATUS_SIG_SYSTEM_ERROR   0x4000 /* Set when we drive SERR */

Definition at line 51 of file pcidef.h.

◆ PCI_STATUS_SIG_TARGET_ABORT

#define PCI_STATUS_SIG_TARGET_ABORT   0x800 /* Set on target abort */

Definition at line 48 of file pcidef.h.

◆ PCI_STATUS_UDF

#define PCI_STATUS_UDF   0x40 /* Support User Definable Features [obsolete] */

Definition at line 41 of file pcidef.h.

◆ PCI_SUBORDINATE_BUS

#define PCI_SUBORDINATE_BUS   0x1a /* Highest bus number behind the bridge */

Definition at line 115 of file pcidef.h.

◆ PCI_SUBSYSTEM_ID

#define PCI_SUBSYSTEM_ID   0x2e

Definition at line 99 of file pcidef.h.

◆ PCI_SUBSYSTEM_VENDOR_ID

#define PCI_SUBSYSTEM_VENDOR_ID   0x2c

Definition at line 98 of file pcidef.h.

◆ PCI_VENDOR_ID

#define PCI_VENDOR_ID   0x00 /* 16 bits */

Definition at line 24 of file pcidef.h.