ReactOS 0.4.15-dev-5666-gc548b97
nic.c File Reference
#include "nvnet.h"
#include "debug.h"
Include dependency graph for nic.c:

Go to the source code of this file.

Macros

#define NDEBUG
 

Functions

static VOID NvNetClearStatisticsCounters (_In_ PNVNET_ADAPTER Adapter)
 
static VOID NvNetResetMac (_In_ PNVNET_ADAPTER Adapter)
 
VOID NvNetResetReceiverAndTransmitter (_In_ PNVNET_ADAPTER Adapter)
 
VOID NvNetStartReceiver (_In_ PNVNET_ADAPTER Adapter)
 
VOID NvNetStartTransmitter (_In_ PNVNET_ADAPTER Adapter)
 
VOID NvNetStopReceiver (_In_ PNVNET_ADAPTER Adapter)
 
VOID NvNetStopTransmitter (_In_ PNVNET_ADAPTER Adapter)
 
VOID NvNetIdleTransmitter (_In_ PNVNET_ADAPTER Adapter, _In_ BOOLEAN ClearPhyControl)
 
VOID NvNetUpdatePauseFrame (_Inout_ PNVNET_ADAPTER Adapter, _In_ ULONG PauseFlags)
 
VOID NvNetToggleClockPowerGating (_In_ PNVNET_ADAPTER Adapter, _In_ BOOLEAN Gate)
 
VOID NTAPI NvNetMediaDetectionDpc (_In_ PVOID SystemSpecific1, _In_ PVOID FunctionContext, _In_ PVOID SystemSpecific2, _In_ PVOID SystemSpecific3)
 
BOOLEAN NTAPI NvNetInitPhaseSynchronized (_In_ PVOID SynchronizeContext)
 
NDIS_STATUS NvNetInitNIC (_In_ PNVNET_ADAPTER Adapter, _In_ BOOLEAN InitPhy)
 
NDIS_STATUS NvNetGetPermanentMacAddress (_Inout_ PNVNET_ADAPTER Adapter, _Out_writes_bytes_all_(ETH_LENGTH_OF_ADDRESS) PUCHAR MacAddress)
 
VOID NvNetSetupMacAddress (_In_ PNVNET_ADAPTER Adapter, _In_reads_bytes_(ETH_LENGTH_OF_ADDRESS) PUCHAR MacAddress)
 
static VOID NvNetValidateConfiguration (_Inout_ PNVNET_ADAPTER Adapter)
 
NDIS_STATUS NvNetRecognizeHardware (_Inout_ PNVNET_ADAPTER Adapter)
 

Macro Definition Documentation

◆ NDEBUG

#define NDEBUG

Definition at line 20 of file nic.c.

Function Documentation

◆ NvNetClearStatisticsCounters()

static VOID NvNetClearStatisticsCounters ( _In_ PNVNET_ADAPTER  Adapter)
static

Definition at line 28 of file nic.c.

30{
31 NVNET_REGISTER Counter, CounterEnd;
32
33 PAGED_CODE();
34
35 NDIS_DbgPrint(MIN_TRACE, ("()\n"));
36
37 if (Adapter->Features & DEV_HAS_STATISTICS_V2)
38 CounterEnd = NvRegRxDropFrame;
39 else
40 CounterEnd = NvRegRxBroadcast;
41
42 for (Counter = NvRegTxCnt; Counter <= CounterEnd; Counter += sizeof(ULONG))
43 {
44 NV_READ(Adapter, Counter);
45 }
46
47 if (Adapter->Features & DEV_HAS_STATISTICS_V3)
48 {
49 NV_READ(Adapter, NvRegTxUnicast);
50 NV_READ(Adapter, NvRegTxMulticast);
51 NV_READ(Adapter, NvRegTxBroadcast);
52 }
53}
#define PAGED_CODE()
#define MIN_TRACE
Definition: debug.h:14
#define NDIS_DbgPrint(_t_, _x_)
Definition: debug.h:40
unsigned int ULONG
Definition: retypes.h:1
#define DEV_HAS_STATISTICS_V2
Definition: nic.h:28
enum _NVNET_REGISTER NVNET_REGISTER
#define DEV_HAS_STATISTICS_V3
Definition: nic.h:29
@ NvRegRxDropFrame
Definition: nic.h:325
@ NvRegTxCnt
Definition: nic.h:299
@ NvRegTxMulticast
Definition: nic.h:252
@ NvRegTxUnicast
Definition: nic.h:251
@ NvRegTxBroadcast
Definition: nic.h:253
@ NvRegRxBroadcast
Definition: nic.h:319
FORCEINLINE ULONG NV_READ(_In_ PNVNET_ADAPTER Adapter, _In_ NVNET_REGISTER Register)
Definition: nvnet.h:656
static LARGE_INTEGER Counter
Definition: clock.c:43

Referenced by NvNetInitNIC().

◆ NvNetGetPermanentMacAddress()

NDIS_STATUS NvNetGetPermanentMacAddress ( _Inout_ PNVNET_ADAPTER  Adapter,
_Out_writes_bytes_all_(ETH_LENGTH_OF_ADDRESS) PUCHAR  MacAddress 
)

Definition at line 541 of file nic.c.

544{
545 ULONG Temp[2], TxPoll;
546
547 PAGED_CODE();
548
549 NDIS_DbgPrint(MIN_TRACE, ("()\n"));
550
551 Temp[0] = NV_READ(Adapter, NvRegMacAddrA);
552 Temp[1] = NV_READ(Adapter, NvRegMacAddrB);
553
554 TxPoll = NV_READ(Adapter, NvRegTransmitPoll);
555
556 if (Adapter->Features & DEV_HAS_CORRECT_MACADDR)
557 {
558 /* MAC address is already in the correct order */
559 MacAddress[0] = (Temp[0] >> 0) & 0xFF;
560 MacAddress[1] = (Temp[0] >> 8) & 0xFF;
561 MacAddress[2] = (Temp[0] >> 16) & 0xFF;
562 MacAddress[3] = (Temp[0] >> 24) & 0xFF;
563 MacAddress[4] = (Temp[1] >> 0) & 0xFF;
564 MacAddress[5] = (Temp[1] >> 8) & 0xFF;
565 }
566 /* Handle the special flag for the correct MAC address order */
567 else if (TxPoll & NVREG_TRANSMITPOLL_MAC_ADDR_REV)
568 {
569 /* MAC address is already in the correct order */
570 MacAddress[0] = (Temp[0] >> 0) & 0xFF;
571 MacAddress[1] = (Temp[0] >> 8) & 0xFF;
572 MacAddress[2] = (Temp[0] >> 16) & 0xFF;
573 MacAddress[3] = (Temp[0] >> 24) & 0xFF;
574 MacAddress[4] = (Temp[1] >> 0) & 0xFF;
575 MacAddress[5] = (Temp[1] >> 8) & 0xFF;
576
577 /*
578 * Set original MAC address back to the reversed version.
579 * This flag will be cleared during low power transition.
580 * Therefore, we should always put back the reversed address.
581 */
582 Temp[0] = (MacAddress[5] << 0) | (MacAddress[4] << 8) |
583 (MacAddress[3] << 16) | (MacAddress[2] << 24);
584 Temp[1] = (MacAddress[1] << 0) | (MacAddress[0] << 8);
585 }
586 else
587 {
588 /* Need to reverse MAC address to the correct order */
589 MacAddress[0] = (Temp[1] >> 8) & 0xFF;
590 MacAddress[1] = (Temp[1] >> 0) & 0xFF;
591 MacAddress[2] = (Temp[0] >> 24) & 0xFF;
592 MacAddress[3] = (Temp[0] >> 16) & 0xFF;
593 MacAddress[4] = (Temp[0] >> 8) & 0xFF;
594 MacAddress[5] = (Temp[0] >> 0) & 0xFF;
595
596 /*
597 * Use a flag to signal the driver whether the MAC address was already corrected,
598 * so that it is not reversed again on a subsequent initialize.
599 */
601 }
602
603 Adapter->OriginalMacAddress[0] = Temp[0];
604 Adapter->OriginalMacAddress[1] = Temp[1];
605
606 NDIS_DbgPrint(MIN_TRACE, ("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
607 MacAddress[0],
608 MacAddress[1],
609 MacAddress[2],
610 MacAddress[3],
611 MacAddress[4],
612 MacAddress[5]));
613
614 if (ETH_IS_MULTICAST(MacAddress) || ETH_IS_EMPTY(MacAddress))
616
617 return NDIS_STATUS_SUCCESS;
618}
#define ETH_IS_EMPTY(Address)
Definition: ethernetutils.h:38
#define NDIS_STATUS_INVALID_ADDRESS
Definition: ndis.h:500
#define NDIS_STATUS_SUCCESS
Definition: ndis.h:346
#define NVREG_TRANSMITPOLL_MAC_ADDR_REV
Definition: nic.h:183
#define DEV_HAS_CORRECT_MACADDR
Definition: nic.h:32
@ NvRegTransmitPoll
Definition: nic.h:182
@ NvRegMacAddrB
Definition: nic.h:151
@ NvRegMacAddrA
Definition: nic.h:150
FORCEINLINE VOID NV_WRITE(_In_ PNVNET_ADAPTER Adapter, _In_ NVNET_REGISTER Register, _In_ ULONG Value)
Definition: nvnet.h:646
#define ETH_IS_MULTICAST(Address)
Definition: xfilter.h:35

Referenced by MiniportInitialize().

◆ NvNetIdleTransmitter()

VOID NvNetIdleTransmitter ( _In_ PNVNET_ADAPTER  Adapter,
_In_ BOOLEAN  ClearPhyControl 
)

Definition at line 211 of file nic.c.

214{
215 ULONG i;
216
217 PAGED_CODE();
218
219 if (ClearPhyControl)
220 {
223 }
224 else
225 {
227 (Adapter->PhyAddress << NVREG_ADAPTCTL_PHYSHIFT) |
229 }
230
231 NV_WRITE(Adapter, NvRegTxRxControl, Adapter->TxRxControl | NVREG_TXRXCTL_BIT2);
232 for (i = 0; i < NV_TXIDLE_ATTEMPTS; ++i)
233 {
235 break;
236
238 }
239}
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
#define NdisStallExecution
Definition: ndis.h:4453
#define NV_TXIDLE_DELAY
Definition: nic.h:448
#define NVREG_TXRXCTL_BIT2
Definition: nic.h:203
#define NVREG_ADAPTCTL_PHYVALID
Definition: nic.h:237
#define NVREG_ADAPTCTL_RUNNING
Definition: nic.h:238
#define NVREG_ADAPTCTL_PHYSHIFT
Definition: nic.h:239
#define NVREG_TXRXCTL_IDLE
Definition: nic.h:204
#define NV_TXIDLE_ATTEMPTS
Definition: nic.h:449
@ NvRegAdapterControl
Definition: nic.h:234
@ NvRegTxRxControl
Definition: nic.h:200

Referenced by MiniportHalt(), MiniportShutdown(), NvNetPowerWorker(), and NvNetResetWorker().

◆ NvNetInitNIC()

NDIS_STATUS NvNetInitNIC ( _In_ PNVNET_ADAPTER  Adapter,
_In_ BOOLEAN  InitPhy 
)

Definition at line 401 of file nic.c.

404{
405 ULONG MiiControl, i;
407
408 PAGED_CODE();
409
410 NDIS_DbgPrint(MIN_TRACE, ("()\n"));
411
412 /* Disable WOL */
413 NV_WRITE(Adapter, NvRegWakeUpFlags, 0);
414
415 if (InitPhy)
416 {
417 Status = NvNetPhyInit(Adapter);
419 {
420 return Status;
421 }
422 }
423
424 if (Adapter->PauseFlags & NV_PAUSEFRAME_TX_CAPABLE)
425 {
427 }
428
429 /* Power up PHY */
430 MiiRead(Adapter, Adapter->PhyAddress, MII_CONTROL, &MiiControl);
431 MiiControl &= ~MII_CR_POWER_DOWN;
432 MiiWrite(Adapter, Adapter->PhyAddress, MII_CONTROL, MiiControl);
433
435
436 NvNetResetMac(Adapter);
437
438 /* Clear multicast masks and addresses */
439 NV_WRITE(Adapter, NvRegMulticastAddrA, 0);
440 NV_WRITE(Adapter, NvRegMulticastAddrB, 0);
443
445 NV_WRITE(Adapter, NvRegReceiverControl, 0);
446
447 NV_WRITE(Adapter, NvRegAdapterControl, 0);
448
449 NV_WRITE(Adapter, NvRegLinkSpeed, 0);
453 NV_WRITE(Adapter, NvRegUnknownSetupReg6, 0);
454
455 /* Receive descriptor ring buffer */
457 NdisGetPhysicalAddressLow(Adapter->RbdPhys));
458 if (Adapter->Features & DEV_HAS_HIGH_DMA)
459 {
461 NdisGetPhysicalAddressHigh(Adapter->RbdPhys));
462 }
463
464 /* Transmit descriptor ring buffer */
466 NdisGetPhysicalAddressLow(Adapter->TbdPhys));
467 if (Adapter->Features & DEV_HAS_HIGH_DMA)
468 {
470 NdisGetPhysicalAddressHigh(Adapter->TbdPhys));
471 }
472
473 /* Ring sizes */
474 NV_WRITE(Adapter, NvRegRingSizes,
477
478 /* Set default link speed settings */
480
481 if (Adapter->Features & (DEV_HAS_HIGH_DMA | DEV_HAS_LARGEDESC))
483 else
485
486 NV_WRITE(Adapter, NvRegTxRxControl, Adapter->TxRxControl);
487 NV_WRITE(Adapter, NvRegVlanControl, Adapter->VlanControl);
488 NV_WRITE(Adapter, NvRegTxRxControl, Adapter->TxRxControl | NVREG_TXRXCTL_BIT1);
489
490 for (i = 0; i < NV_SETUP5_DELAYMAX; ++i)
491 {
493 break;
494
496 }
497
498 NV_WRITE(Adapter, NvRegMIIMask, 0);
501
506 + NV_RX_HEADERS);
507
509
511
514
515 if (Adapter->OptimizationMode == NV_OPTIMIZATION_MODE_THROUGHPUT)
517 else
520
522 (Adapter->PhyAddress << NVREG_ADAPTCTL_PHYSHIFT) |
526
528 NV_WRITE(Adapter, NvRegPowerState,
530
531 if (Adapter->Features & DEV_HAS_STATISTICS_COUNTERS)
532 {
534 }
535
536 return NDIS_STATUS_SUCCESS;
537}
VOID NvNetBackoffSetSlotTime(_In_ PNVNET_ADAPTER Adapter)
Definition: backoff.c:58
#define FALSE
Definition: types.h:117
Status
Definition: gdiplustypes.h:25
#define NdisGetPhysicalAddressLow(PhysicalAddress)
Definition: ndis.h:3847
#define NdisGetPhysicalAddressHigh(PhysicalAddress)
Definition: ndis.h:3830
static VOID NvNetResetMac(_In_ PNVNET_ADAPTER Adapter)
Definition: nic.c:58
VOID NvNetToggleClockPowerGating(_In_ PNVNET_ADAPTER Adapter, _In_ BOOLEAN Gate)
Definition: nic.c:294
VOID NvNetResetReceiverAndTransmitter(_In_ PNVNET_ADAPTER Adapter)
Definition: nic.c:91
static VOID NvNetClearStatisticsCounters(_In_ PNVNET_ADAPTER Adapter)
Definition: nic.c:28
int NDIS_STATUS
Definition: ntddndis.h:475
#define NVREG_IRQSTAT_MASK
Definition: nic.h:53
#define NVREG_POWERSTATE_VALID
Definition: nic.h:289
#define NVREG_MCASTMASKB_NONE
Definition: nic.h:161
#define NVREG_PFF_ALWAYS
Definition: nic.h:115
#define NVREG_MISC1_FORCE
Definition: nic.h:92
#define NV_SETUP5_DELAYMAX
Definition: nic.h:454
#define NVREG_TX_WM_DESC1_DEFAULT
Definition: nic.h:196
#define DEV_HAS_LARGEDESC
Definition: nic.h:20
#define NVREG_TXRXCTL_BIT1
Definition: nic.h:202
#define NVREG_UNKSETUP6_VAL
Definition: nic.h:74
#define NV_RX_HEADERS
Definition: nic.h:471
#define NVREG_TX_DEFERRAL_DEFAULT
Definition: nic.h:140
#define DEV_HAS_STATISTICS_COUNTERS
Definition: nic.h:44
#define NV_SETUP5_DELAY
Definition: nic.h:453
#define NVREG_POLL_DEFAULT_THROUGHPUT
Definition: nic.h:77
#define NVREG_MIIDELAY
Definition: nic.h:243
#define NVREG_POLL_DEFAULT_CPU
Definition: nic.h:78
#define NVREG_TX_WM_DESC2_3_DEFAULT
Definition: nic.h:197
#define NV_PAUSEFRAME_TX_CAPABLE
Definition: nic.h:544
#define NVREG_MIISTAT_MASK_ALL
Definition: nic.h:229
#define NVREG_PFF_MYADDR
Definition: nic.h:117
#define NVREG_RX_DEFERRAL_DEFAULT
Definition: nic.h:148
#define NVREG_MCASTMASKA_NONE
Definition: nic.h:158
#define DEV_HAS_HIGH_DMA
Definition: nic.h:21
#define NVREG_UNKSETUP5_BIT31
Definition: nic.h:193
#define NVREG_RINGSZ_RXSHIFT
Definition: nic.h:180
#define NVREG_MII_LINKCHANGE
Definition: nic.h:232
#define NVREG_MIISPEED_BIT8
Definition: nic.h:242
#define NVREG_LINKSPEED_FORCE
Definition: nic.h:186
#define NVREG_MISC1_HD
Definition: nic.h:91
#define NVREG_LINKSPEED_10
Definition: nic.h:187
@ NvRegRxDeferral
Definition: nic.h:147
@ NvRegRxRingPhysAddr
Definition: nic.h:176
@ NvRegReceiverStatus
Definition: nic.h:128
@ NvRegMulticastAddrA
Definition: nic.h:153
@ NvRegTxWatermark
Definition: nic.h:195
@ NvRegRxRingPhysAddrHigh
Definition: nic.h:214
@ NvRegWakeUpFlags
Definition: nic.h:255
@ NvRegMulticastMaskA
Definition: nic.h:157
@ NvRegRingSizes
Definition: nic.h:178
@ NvRegTxDeferral
Definition: nic.h:139
@ NvRegReceiverControl
Definition: nic.h:124
@ NvRegIrqStatus
Definition: nic.h:51
@ NvRegLinkSpeed
Definition: nic.h:185
@ NvRegTxRingPhysAddrHigh
Definition: nic.h:213
@ NvRegMIIStatus
Definition: nic.h:225
@ NvRegTxPauseFrame
Definition: nic.h:216
@ NvRegVlanControl
Definition: nic.h:327
@ NvRegPollingInterval
Definition: nic.h:76
@ NvRegMIIMask
Definition: nic.h:231
@ NvRegTransmitterControl
Definition: nic.h:94
@ NvRegPacketFilterFlags
Definition: nic.h:113
@ NvRegPowerState
Definition: nic.h:287
@ NvRegUnknownSetupReg5
Definition: nic.h:192
@ NvRegMulticastMaskB
Definition: nic.h:160
@ NvRegTransmitterStatus
Definition: nic.h:110
@ NvRegUnknownSetupReg6
Definition: nic.h:73
@ NvRegMIISpeed
Definition: nic.h:241
@ NvRegMulticastAddrB
Definition: nic.h:154
@ NvRegOffloadConfig
Definition: nic.h:120
@ NvRegTxRingPhysAddr
Definition: nic.h:175
@ NvRegMisc1
Definition: nic.h:89
#define NVREG_RINGSZ_TXSHIFT
Definition: nic.h:179
#define NVREG_TX_PAUSEFRAME_DISABLE
Definition: nic.h:217
BOOLEAN MiiRead(_In_ PNVNET_ADAPTER Adapter, _In_ ULONG PhyAddress, _In_ ULONG RegAddress, _Out_ PULONG Data)
Definition: phy.c:62
#define NVNET_RECEIVE_DESCRIPTORS
Definition: nvnet.h:34
@ NV_OPTIMIZATION_MODE_THROUGHPUT
Definition: nvnet.h:82
#define NVNET_MAXIMUM_FRAME_SIZE
Definition: nvnet.h:60
#define NVNET_TRANSMIT_DESCRIPTORS
Definition: nvnet.h:32
BOOLEAN MiiWrite(_In_ PNVNET_ADAPTER Adapter, _In_ ULONG PhyAddress, _In_ ULONG RegAddress, _In_ ULONG Data)
Definition: phy.c:26
NDIS_STATUS NvNetPhyInit(_In_ PNVNET_ADAPTER Adapter)
Definition: phy.c:1036
#define MII_CONTROL
Definition: phyreg.h:11
Definition: lan.h:33

Referenced by MiniportInitialize(), NvNetPowerWorker(), and NvNetResetWorker().

◆ NvNetInitPhaseSynchronized()

BOOLEAN NTAPI NvNetInitPhaseSynchronized ( _In_ PVOID  SynchronizeContext)

Definition at line 369 of file nic.c.

371{
373
374 NDIS_DbgPrint(MIN_TRACE, ("()\n"));
375
376 /* Enable interrupts on the NIC */
378
379 /*
380 * One manual link speed update: Interrupts are enabled,
381 * future link speed changes cause interrupts.
382 */
383 NV_READ(Adapter, NvRegMIIStatus);
385
386 /* Set link speed to invalid value, thus force NvNetUpdateLinkSpeed() to init HW */
387 Adapter->LinkSpeed = 0xFFFFFFFF;
388
389 Adapter->Connected = NvNetUpdateLinkSpeed(Adapter);
390
391 NvNetStartReceiver(Adapter);
392 NvNetStartTransmitter(Adapter);
393
394 Adapter->Flags |= NV_ACTIVE;
395
396 return TRUE;
397}
#define TRUE
Definition: types.h:120
VOID NvNetStartTransmitter(_In_ PNVNET_ADAPTER Adapter)
Definition: nic.c:130
VOID NvNetStartReceiver(_In_ PNVNET_ADAPTER Adapter)
Definition: nic.c:104
#define NV_ACTIVE
Definition: nvnet.h:286
BOOLEAN NvNetUpdateLinkSpeed(_In_ PNVNET_ADAPTER Adapter)
Definition: phy.c:990
#define NvNetApplyInterruptMask(Adapter)
Definition: nvnet.h:669
BOOLEAN Connected
Definition: nvnet.h:334
ULONG Flags
Definition: nvnet.h:285
ULONG LinkSpeed
Definition: nvnet.h:333
_In_ PKSYNCHRONIZE_ROUTINE _In_opt_ __drv_aliasesMem PVOID SynchronizeContext
Definition: kefuncs.h:539

◆ NvNetMediaDetectionDpc()

VOID NTAPI NvNetMediaDetectionDpc ( _In_ PVOID  SystemSpecific1,
_In_ PVOID  FunctionContext,
_In_ PVOID  SystemSpecific2,
_In_ PVOID  SystemSpecific3 
)

Definition at line 314 of file nic.c.

319{
321 BOOLEAN Connected, Report = FALSE;
322
323 UNREFERENCED_PARAMETER(SystemSpecific1);
326
327 NDIS_DbgPrint(MIN_TRACE, ("()\n"));
328
329 NdisDprAcquireSpinLock(&Adapter->Lock);
330
331 Connected = NvNetUpdateLinkSpeed(Adapter);
332 if (Adapter->Connected != Connected)
333 {
334 Adapter->Connected = Connected;
335 Report = TRUE;
336
337 if (Connected)
338 {
339 /* Link up */
342 NvNetStartReceiver(Adapter);
343 }
344 else
345 {
346 /* Link down */
349 NvNetStopReceiver(Adapter);
350 }
351
353 }
354
355 NdisDprReleaseSpinLock(&Adapter->Lock);
356
357 if (Report)
358 {
361 NULL,
362 0);
364 }
365}
unsigned char BOOLEAN
#define NULL
Definition: types.h:112
#define NDIS_STATUS_MEDIA_CONNECT
Definition: ndis.h:361
#define NdisMIndicateStatusComplete(MiniportAdapterHandle)
Definition: ndis.h:5580
_In_ PVOID _In_ PVOID SystemSpecific2
Definition: ndis.h:638
#define NdisDprReleaseSpinLock(_SpinLock)
Definition: ndis.h:4133
#define NDIS_STATUS_MEDIA_DISCONNECT
Definition: ndis.h:362
_In_ PVOID FunctionContext
Definition: ndis.h:637
#define NdisDprAcquireSpinLock(_SpinLock)
Definition: ndis.h:4124
#define NdisMIndicateStatus(MiniportAdapterHandle, GeneralStatus, StatusBuffer, StatusBufferSize)
Definition: ndis.h:5570
_In_ PVOID _In_ PVOID _In_ PVOID SystemSpecific3
Definition: ndis.h:639
VOID NvNetStopReceiver(_In_ PNVNET_ADAPTER Adapter)
Definition: nic.c:147
#define UNREFERENCED_PARAMETER(P)
Definition: ntbasedef.h:317
NDIS_HANDLE AdapterHandle
Definition: nvnet.h:283
NDIS_SPIN_LOCK Lock
Definition: nvnet.h:320
NVNET_RECEIVE Receive
Definition: nvnet.h:312
NDIS_SPIN_LOCK Lock
Definition: nvnet.h:255

◆ NvNetRecognizeHardware()

NDIS_STATUS NvNetRecognizeHardware ( _Inout_ PNVNET_ADAPTER  Adapter)

Definition at line 675 of file nic.c.

677{
678 ULONG Bytes;
679 PCI_COMMON_CONFIG PciConfig;
680
681 PAGED_CODE();
682
683 NDIS_DbgPrint(MIN_TRACE, ("()\n"));
684
685 Bytes = NdisReadPciSlotInformation(Adapter->AdapterHandle,
686 0,
688 &PciConfig,
692
693 if (PciConfig.VendorID != 0x10DE)
695
696 Adapter->DeviceId = PciConfig.DeviceID;
697 Adapter->RevisionId = PciConfig.RevisionID;
698
699 switch (PciConfig.DeviceID)
700 {
701 case 0x01C3: /* nForce */
702 case 0x0066: /* nForce2 */
703 case 0x00D6: /* nForce2 */
704 Adapter->Features = DEV_NEED_TIMERIRQ | DEV_NEED_LINKTIMER;
705 break;
706
707 case 0x0086: /* nForce3 */
708 case 0x008C: /* nForce3 */
709 case 0x00E6: /* nForce3 */
710 case 0x00DF: /* nForce3 */
711 Adapter->Features = DEV_NEED_TIMERIRQ | DEV_NEED_LINKTIMER |
713 break;
714
715 case 0x0056: /* CK804 */
716 case 0x0057: /* CK804 */
717 case 0x0037: /* MCP04 */
718 case 0x0038: /* MCP04 */
721 break;
722
723 case 0x0268: /* MCP51 */
724 case 0x0269: /* MCP51 */
727 break;
728
729 case 0x0372: /* MCP55 */
730 case 0x0373: /* MCP55 */
737 break;
738
739 case 0x03E5: /* MCP61 */
740 case 0x03E6: /* MCP61 */
741 case 0x03EE: /* MCP61 */
742 case 0x03EF: /* MCP61 */
747 break;
748
749 case 0x0450: /* MCP65 */
750 case 0x0451: /* MCP65 */
751 case 0x0452: /* MCP65 */
752 case 0x0453: /* MCP65 */
759 break;
760
761 case 0x054C: /* MCP67 */
762 case 0x054D: /* MCP67 */
763 case 0x054E: /* MCP67 */
764 case 0x054F: /* MCP67 */
769 break;
770
771 case 0x07DC: /* MCP73 */
772 case 0x07DD: /* MCP73 */
773 case 0x07DE: /* MCP73 */
774 case 0x07DF: /* MCP73 */
780 break;
781
782 case 0x0760: /* MCP77 */
783 case 0x0761: /* MCP77 */
784 case 0x0762: /* MCP77 */
785 case 0x0763: /* MCP77 */
793 break;
794
795 case 0x0AB0: /* MCP79 */
796 case 0x0AB1: /* MCP79 */
797 case 0x0AB2: /* MCP79 */
798 case 0x0AB3: /* MCP79 */
806 break;
807
808 case 0x0D7D: /* MCP89 */
815 break;
816
817 default:
819 }
820
821 /* Normalize all .INF parameters */
823
824 /* FIXME: Disable some NIC features, we don't support these yet */
825#if 1
826 Adapter->VlanControl = 0;
827 Adapter->Flags &= ~(NV_SEND_CHECKSUM | NV_SEND_LARGE_SEND |
829#endif
830
831 /* For code paths debugging (32-bit descriptors work on all hardware variants) */
832#if 0
833 Adapter->Features &= ~(DEV_HAS_HIGH_DMA | DEV_HAS_LARGEDESC);
834#endif
835
836 if (Adapter->Features & DEV_HAS_POWER_CNTRL)
837 Adapter->WakeFrameBitmap = ~(0xFFFFFFFF << NV_WAKEUPPATTERNS_V2);
838 else
839 Adapter->WakeFrameBitmap = ~(0xFFFFFFFF << NV_WAKEUPPATTERNS);
840
841 /* 64-bit descriptors */
842 if (Adapter->Features & DEV_HAS_HIGH_DMA)
843 {
844 /* Note: Some devices here also support Jumbo Frames */
845 Adapter->TxRxControl = NVREG_TXRXCTL_DESC_3;
846 }
847 /* 32-bit descriptors */
848 else
849 {
850 if (Adapter->Features & DEV_HAS_LARGEDESC)
851 {
852 /* Jumbo Frames */
853 Adapter->TxRxControl = NVREG_TXRXCTL_DESC_2;
854 }
855 else
856 {
857 /* Original packet format */
858 Adapter->TxRxControl = NVREG_TXRXCTL_DESC_1;
859 }
860 }
861
862 /* Flow control */
864 if (Adapter->Features & DEV_HAS_TX_PAUSEFRAME)
865 {
866 Adapter->PauseFlags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
867 }
868 if (Adapter->FlowControlMode != NV_FLOW_CONTROL_AUTO)
869 {
870 Adapter->PauseFlags &= ~(NV_PAUSEFRAME_AUTONEG | NV_PAUSEFRAME_RX_REQ |
872 switch (Adapter->FlowControlMode)
873 {
875 Adapter->PauseFlags |= NV_PAUSEFRAME_RX_REQ;
876 break;
878 Adapter->PauseFlags |= NV_PAUSEFRAME_TX_REQ;
879 break;
881 Adapter->PauseFlags |= NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_TX_REQ;
882 break;
883
884 default:
885 break;
886 }
887 }
888
889 /* Work around errata in some NICs */
890 if (Adapter->Features & (DEV_NEED_TX_LIMIT | DEV_NEED_TX_LIMIT2))
891 {
892 Adapter->Flags |= NV_SEND_ERRATA_PRESENT;
893
894 if ((Adapter->Features & DEV_NEED_TX_LIMIT2) && Adapter->RevisionId >= 0xA2)
895 {
896 Adapter->Flags &= ~NV_SEND_ERRATA_PRESENT;
897 }
898 }
899 if (Adapter->Flags & NV_SEND_ERRATA_PRESENT)
900 {
901 NDIS_DbgPrint(MIN_TRACE, ("Transmit workaround active\n"));
902 }
903
904 /* Initialize the interrupt mask */
905 if (Adapter->OptimizationMode == NV_OPTIMIZATION_MODE_CPU)
906 {
907 Adapter->InterruptMask = NVREG_IRQMASK_CPU;
908 }
909 else
910 {
911 Adapter->InterruptMask = NVREG_IRQMASK_THROUGHPUT;
912 }
913 if (Adapter->Features & DEV_NEED_TIMERIRQ)
914 {
915 Adapter->InterruptMask |= NVREG_IRQ_TIMER;
916 }
917
918 if (Adapter->Features & DEV_NEED_LINKTIMER)
919 {
920 NdisMInitializeTimer(&Adapter->MediaDetectionTimer,
921 Adapter->AdapterHandle,
923 Adapter);
924 }
925
926 return NDIS_STATUS_SUCCESS;
927}
ULONG EXPORT NdisReadPciSlotInformation(IN NDIS_HANDLE NdisAdapterHandle, IN ULONG SlotNumber, IN ULONG Offset, IN PVOID Buffer, IN ULONG Length)
Definition: hardware.c:180
VOID EXPORT NdisMInitializeTimer(IN OUT PNDIS_MINIPORT_TIMER Timer, IN NDIS_HANDLE MiniportAdapterHandle, IN PNDIS_TIMER_FUNCTION TimerFunction, IN PVOID FunctionContext)
Definition: time.c:192
_In_ UINT Bytes
Definition: mmcopy.h:9
#define NDIS_STATUS_NOT_RECOGNIZED
Definition: ndis.h:348
#define NDIS_STATUS_ADAPTER_NOT_FOUND
Definition: ndis.h:470
static VOID NvNetValidateConfiguration(_Inout_ PNVNET_ADAPTER Adapter)
Definition: nic.c:638
#define NVREG_TXRXCTL_DESC_2
Definition: nic.h:208
#define DEV_HAS_TEST_EXTENDED
Definition: nic.h:30
#define DEV_HAS_VLAN
Definition: nic.h:23
#define DEV_HAS_POWER_CNTRL
Definition: nic.h:26
#define DEV_HAS_MSI
Definition: nic.h:24
#define DEV_HAS_TX_PAUSEFRAME
Definition: nic.h:46
#define NVREG_TXRXCTL_DESC_3
Definition: nic.h:209
#define NV_PAUSEFRAME_TX_REQ
Definition: nic.h:548
#define DEV_HAS_STATISTICS_V1
Definition: nic.h:27
#define NV_WAKEUPPATTERNS_V2
Definition: nic.h:466
#define DEV_NEED_PHY_INIT_FIX
Definition: nic.h:40
#define NV_PAUSEFRAME_AUTONEG
Definition: nic.h:549
#define DEV_HAS_MSI_X
Definition: nic.h:25
#define NV_PAUSEFRAME_RX_CAPABLE
Definition: nic.h:543
#define DEV_HAS_PAUSEFRAME_TX_V1
Definition: nic.h:34
#define DEV_HAS_COLLISION_FIX
Definition: nic.h:33
#define DEV_NEED_LINKTIMER
Definition: nic.h:19
#define DEV_HAS_PAUSEFRAME_TX_V3
Definition: nic.h:36
#define DEV_NEED_MSI_FIX
Definition: nic.h:42
#define DEV_HAS_GEAR_MODE
Definition: nic.h:39
#define NVREG_IRQMASK_CPU
Definition: nic.h:67
#define NVREG_IRQMASK_THROUGHPUT
Definition: nic.h:66
#define DEV_NEED_TX_LIMIT
Definition: nic.h:37
#define DEV_HAS_MGMT_UNIT
Definition: nic.h:31
#define DEV_HAS_PAUSEFRAME_TX_V2
Definition: nic.h:35
#define NVREG_IRQ_TIMER
Definition: nic.h:61
#define DEV_NEED_TX_LIMIT2
Definition: nic.h:38
#define NV_WAKEUPPATTERNS
Definition: nic.h:465
#define DEV_HAS_CHECKSUM
Definition: nic.h:22
#define DEV_NEED_LOW_POWER_FIX
Definition: nic.h:41
#define NVREG_TXRXCTL_DESC_1
Definition: nic.h:207
#define DEV_NEED_TIMERIRQ
Definition: nic.h:18
#define NV_PAUSEFRAME_RX_REQ
Definition: nic.h:547
@ NV_OPTIMIZATION_MODE_CPU
Definition: nvnet.h:81
#define NV_PACKET_PRIORITY
Definition: nvnet.h:298
@ NV_FLOW_CONTROL_RX
Definition: nvnet.h:89
@ NV_FLOW_CONTROL_AUTO
Definition: nvnet.h:88
@ NV_FLOW_CONTROL_TX
Definition: nvnet.h:90
@ NV_FLOW_CONTROL_RX_TX
Definition: nvnet.h:91
#define NV_SEND_LARGE_SEND
Definition: nvnet.h:288
#define NV_SEND_CHECKSUM
Definition: nvnet.h:287
#define NV_VLAN_TAGGING
Definition: nvnet.h:299
NDIS_TIMER_FUNCTION NvNetMediaDetectionDpc
Definition: nvnet.h:471
#define NV_SEND_ERRATA_PRESENT
Definition: nvnet.h:289
#define FIELD_OFFSET(t, f)
Definition: typedefs.h:255
#define PCI_COMMON_HDR_LENGTH
Definition: iotypes.h:3594

Referenced by MiniportInitialize().

◆ NvNetResetMac()

static VOID NvNetResetMac ( _In_ PNVNET_ADAPTER  Adapter)
static

Definition at line 58 of file nic.c.

60{
61 ULONG Temp[3];
62
63 NDIS_DbgPrint(MIN_TRACE, ("()\n"));
64
65 if (!(Adapter->Features & DEV_HAS_POWER_CNTRL))
66 return;
67
69 Adapter->TxRxControl | NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET);
70
71 /* Save registers since they will be cleared on reset */
72 Temp[0] = NV_READ(Adapter, NvRegMacAddrA);
73 Temp[1] = NV_READ(Adapter, NvRegMacAddrB);
74 Temp[2] = NV_READ(Adapter, NvRegTransmitPoll);
75
78 NV_WRITE(Adapter, NvRegMacReset, 0);
80
81 /* Restore saved registers */
82 NV_WRITE(Adapter, NvRegMacAddrA, Temp[0]);
83 NV_WRITE(Adapter, NvRegMacAddrB, Temp[1]);
84 NV_WRITE(Adapter, NvRegTransmitPoll, Temp[2]);
85
87 Adapter->TxRxControl | NVREG_TXRXCTL_BIT2);
88}
#define NVREG_MAC_RESET_ASSERT
Definition: nic.h:87
#define NVREG_TXRXCTL_RESET
Definition: nic.h:205
#define NV_MAC_RESET_DELAY
Definition: nic.h:463
@ NvRegMacReset
Definition: nic.h:86

Referenced by NvNetInitNIC().

◆ NvNetResetReceiverAndTransmitter()

VOID NvNetResetReceiverAndTransmitter ( _In_ PNVNET_ADAPTER  Adapter)

Definition at line 91 of file nic.c.

93{
95 Adapter->TxRxControl | NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET);
96
98
100 Adapter->TxRxControl | NVREG_TXRXCTL_BIT2);
101}
#define NV_TXRX_RESET_DELAY
Definition: nic.h:444

Referenced by NvNetInitNIC().

◆ NvNetSetupMacAddress()

VOID NvNetSetupMacAddress ( _In_ PNVNET_ADAPTER  Adapter,
_In_reads_bytes_(ETH_LENGTH_OF_ADDRESS) PUCHAR  MacAddress 
)

Definition at line 622 of file nic.c.

625{
626 PAGED_CODE();
627
628 NDIS_DbgPrint(MIN_TRACE, ("()\n"));
629
630 NV_WRITE(Adapter, NvRegMacAddrA,
631 MacAddress[3] << 24 | MacAddress[2] << 16 | MacAddress[1] << 8 | MacAddress[0]);
632 NV_WRITE(Adapter, NvRegMacAddrB, MacAddress[5] << 8 | MacAddress[4]);
633}

Referenced by MiniportInitialize().

◆ NvNetStartReceiver()

VOID NvNetStartReceiver ( _In_ PNVNET_ADAPTER  Adapter)

Definition at line 104 of file nic.c.

106{
107 ULONG RxControl;
108
109 NDIS_DbgPrint(MIN_TRACE, ("()\n"));
110
111 RxControl = NV_READ(Adapter, NvRegReceiverControl);
113 !(Adapter->Flags & NV_MAC_IN_USE))
114 {
115 /* Already running? Stop it */
116 RxControl &= ~NVREG_RCVCTL_START;
117 NV_WRITE(Adapter, NvRegReceiverControl, RxControl);
118 }
119 NV_WRITE(Adapter, NvRegLinkSpeed, Adapter->LinkSpeed | NVREG_LINKSPEED_FORCE);
120
121 RxControl |= NVREG_RCVCTL_START;
122 if (Adapter->Flags & NV_MAC_IN_USE)
123 {
124 RxControl &= ~NVREG_RCVCTL_RX_PATH_EN;
125 }
126 NV_WRITE(Adapter, NvRegReceiverControl, RxControl);
127}
#define NVREG_RCVCTL_START
Definition: nic.h:125
#define NV_MAC_IN_USE
Definition: nvnet.h:291

Referenced by HandleLinkStateChange(), NvNetApplyPacketFilter(), NvNetBackoffReseed(), NvNetInitPhaseSynchronized(), NvNetMediaDetectionDpc(), NvNetSetPowerState(), and NvNetSetSpeedAndDuplex().

◆ NvNetStartTransmitter()

VOID NvNetStartTransmitter ( _In_ PNVNET_ADAPTER  Adapter)

Definition at line 130 of file nic.c.

132{
133 ULONG TxControl;
134
135 NDIS_DbgPrint(MIN_TRACE, ("()\n"));
136
137 TxControl = NV_READ(Adapter, NvRegTransmitterControl);
138 TxControl |= NVREG_XMITCTL_START;
139 if (Adapter->Flags & NV_MAC_IN_USE)
140 {
141 TxControl &= ~NVREG_XMITCTL_TX_PATH_EN;
142 }
143 NV_WRITE(Adapter, NvRegTransmitterControl, TxControl);
144}
#define NVREG_XMITCTL_START
Definition: nic.h:95

Referenced by NvNetBackoffReseed(), NvNetInitPhaseSynchronized(), and NvNetSetSpeedAndDuplex().

◆ NvNetStopReceiver()

VOID NvNetStopReceiver ( _In_ PNVNET_ADAPTER  Adapter)

Definition at line 147 of file nic.c.

149{
150 ULONG RxControl, i;
151
152 NDIS_DbgPrint(MIN_TRACE, ("()\n"));
153
154 RxControl = NV_READ(Adapter, NvRegReceiverControl);
155 if (!(Adapter->Flags & NV_MAC_IN_USE))
156 RxControl &= ~NVREG_RCVCTL_START;
157 else
158 RxControl |= NVREG_RCVCTL_RX_PATH_EN;
159 NV_WRITE(Adapter, NvRegReceiverControl, RxControl);
160
161 for (i = 0; i < NV_RXSTOP_DELAY1MAX; ++i)
162 {
164 break;
165
167 }
168
170
171 if (!(Adapter->Flags & NV_MAC_IN_USE))
172 {
173 NV_WRITE(Adapter, NvRegLinkSpeed, 0);
174 }
175}
#define NVREG_RCVCTL_RX_PATH_EN
Definition: nic.h:126
#define NV_RXSTOP_DELAY1MAX
Definition: nic.h:451
#define NV_RXSTOP_DELAY2
Definition: nic.h:452
#define NVREG_RCVSTAT_BUSY
Definition: nic.h:129
#define NV_RXSTOP_DELAY1
Definition: nic.h:450

Referenced by HandleLinkStateChange(), MiniportHalt(), MiniportShutdown(), NvNetApplyPacketFilter(), NvNetBackoffReseed(), NvNetMediaDetectionDpc(), NvNetPowerWorker(), NvNetResetWorker(), and NvNetSetSpeedAndDuplex().

◆ NvNetStopTransmitter()

VOID NvNetStopTransmitter ( _In_ PNVNET_ADAPTER  Adapter)

Definition at line 178 of file nic.c.

180{
181 ULONG TxControl, i;
182
183 NDIS_DbgPrint(MIN_TRACE, ("()\n"));
184
185 TxControl = NV_READ(Adapter, NvRegTransmitterControl);
186 if (!(Adapter->Flags & NV_MAC_IN_USE))
187 TxControl &= ~NVREG_XMITCTL_START;
188 else
189 TxControl |= NVREG_XMITCTL_TX_PATH_EN;
190 NV_WRITE(Adapter, NvRegTransmitterControl, TxControl);
191
192 for (i = 0; i < NV_TXSTOP_DELAY1MAX; ++i)
193 {
195 break;
196
198 }
199
201
202 if (!(Adapter->Flags & NV_MAC_IN_USE))
203 {
206 }
207}
#define NV_TXSTOP_DELAY2
Definition: nic.h:447
#define NV_TXSTOP_DELAY1MAX
Definition: nic.h:446
#define NVREG_XMITCTL_TX_PATH_EN
Definition: nic.h:105
#define NVREG_XMITSTAT_BUSY
Definition: nic.h:111
#define NV_TXSTOP_DELAY1
Definition: nic.h:445

Referenced by MiniportHalt(), MiniportShutdown(), NvNetBackoffReseed(), NvNetPowerWorker(), NvNetResetWorker(), and NvNetSetSpeedAndDuplex().

◆ NvNetToggleClockPowerGating()

VOID NvNetToggleClockPowerGating ( _In_ PNVNET_ADAPTER  Adapter,
_In_ BOOLEAN  Gate 
)

Definition at line 294 of file nic.c.

297{
298 NDIS_DbgPrint(MIN_TRACE, ("()\n"));
299
300 if (!(Adapter->Flags & NV_MAC_IN_USE) && (Adapter->Features & DEV_HAS_POWER_CNTRL))
301 {
303
304 if (Gate)
306 else
307 PowerState &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
309 }
310}
#define NVREG_POWERSTATE2_GATE_CLOCKS
Definition: nic.h:341
@ NvRegPowerState2
Definition: nic.h:334
_Must_inspect_result_ _In_ PWDFDEVICE_INIT _In_ WDF_DEVICE_POWER_STATE PowerState
Definition: wdfdevice.h:3034

Referenced by HandleLinkStateChange(), MiniportHalt(), NvNetInitNIC(), and NvNetMediaDetectionDpc().

◆ NvNetUpdatePauseFrame()

VOID NvNetUpdatePauseFrame ( _Inout_ PNVNET_ADAPTER  Adapter,
_In_ ULONG  PauseFlags 
)

Definition at line 242 of file nic.c.

245{
246 NDIS_DbgPrint(MIN_TRACE, ("()\n"));
247
248 Adapter->PauseFlags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
249
250 if (Adapter->PauseFlags & NV_PAUSEFRAME_RX_CAPABLE)
251 {
252 ULONG PacketFilter = NV_READ(Adapter, NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
253
254 if (PauseFlags & NV_PAUSEFRAME_RX_ENABLE)
255 {
256 PacketFilter |= NVREG_PFF_PAUSE_RX;
257 Adapter->PauseFlags |= NV_PAUSEFRAME_RX_ENABLE;
258 }
259 NV_WRITE(Adapter, NvRegPacketFilterFlags, PacketFilter);
260 }
261
262 if (Adapter->PauseFlags & NV_PAUSEFRAME_TX_CAPABLE)
263 {
264 ULONG Mics = NV_READ(Adapter, NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
265
266 if (PauseFlags & NV_PAUSEFRAME_TX_ENABLE)
267 {
269
270 if (Adapter->Features & DEV_HAS_PAUSEFRAME_TX_V2)
271 PauseEnable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
272 if (Adapter->Features & DEV_HAS_PAUSEFRAME_TX_V3)
273 {
274 PauseEnable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
275 /* Limit the number of TX pause frames to a default of 8 */
276 NV_WRITE(Adapter,
280 }
281 NV_WRITE(Adapter, NvRegTxPauseFrame, PauseEnable);
282 NV_WRITE(Adapter, NvRegMisc1, Mics | NVREG_MISC1_PAUSE_TX);
283 Adapter->PauseFlags |= NV_PAUSEFRAME_TX_ENABLE;
284 }
285 else
286 {
288 NV_WRITE(Adapter, NvRegMisc1, Mics);
289 }
290 }
291}
#define NVREG_MISC1_PAUSE_TX
Definition: nic.h:90
#define NV_PAUSEFRAME_RX_ENABLE
Definition: nic.h:545
#define NVREG_TX_PAUSEFRAME_ENABLE_V3
Definition: nic.h:220
#define NVREG_TX_PAUSEFRAMELIMIT_ENABLE
Definition: nic.h:223
#define NV_PAUSEFRAME_TX_ENABLE
Definition: nic.h:546
#define NVREG_TX_PAUSEFRAME_ENABLE_V2
Definition: nic.h:219
#define NVREG_TX_PAUSEFRAME_ENABLE_V1
Definition: nic.h:218
@ NvRegTxPauseFrameLimit
Definition: nic.h:222
#define NVREG_PFF_PAUSE_RX
Definition: nic.h:114

Referenced by NvNetSetSpeedAndDuplex().

◆ NvNetValidateConfiguration()

static VOID NvNetValidateConfiguration ( _Inout_ PNVNET_ADAPTER  Adapter)
static

Definition at line 638 of file nic.c.

640{
641 PAGED_CODE();
642
643 if (!(Adapter->Features & DEV_HAS_LARGEDESC))
644 {
645 Adapter->MaximumFrameSize = NVNET_MAXIMUM_FRAME_SIZE;
646 }
647 if (!(Adapter->Features & DEV_HAS_CHECKSUM))
648 {
649 Adapter->Flags &= ~(NV_SEND_CHECKSUM | NV_SEND_LARGE_SEND);
650 }
651 if (!(Adapter->Features & DEV_HAS_VLAN))
652 {
653 Adapter->Flags &= ~(NV_PACKET_PRIORITY | NV_VLAN_TAGGING);
654 }
655 if ((Adapter->Features & DEV_NEED_TIMERIRQ) &&
656 (Adapter->OptimizationMode == NV_OPTIMIZATION_MODE_DYNAMIC))
657 {
658 Adapter->OptimizationMode = NV_OPTIMIZATION_MODE_THROUGHPUT;
659 }
660 if (!(Adapter->Features & DEV_HAS_TX_PAUSEFRAME))
661 {
662 if (Adapter->FlowControlMode == NV_FLOW_CONTROL_TX)
663 {
664 Adapter->FlowControlMode = NV_FLOW_CONTROL_AUTO;
665 }
666 else if (Adapter->FlowControlMode == NV_FLOW_CONTROL_RX_TX)
667 {
668 Adapter->FlowControlMode = NV_FLOW_CONTROL_RX;
669 }
670 }
671}
@ NV_OPTIMIZATION_MODE_DYNAMIC
Definition: nvnet.h:80

Referenced by NvNetRecognizeHardware().