ReactOS 0.4.15-dev-7931-gfd331f1
dc21x4hw.h
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1/*
2 * PROJECT: ReactOS DC21x4 Driver
3 * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
4 * PURPOSE: Hardware specific definitions
5 * COPYRIGHT: Copyright 2023 Dmitry Borisov <di.sean@protonmail.com>
6 */
7
8#pragma once
9
10typedef enum _DC_CHIP_TYPE
11{
18
19/*
20 * PCI Vendor and Device IDs
21 */
22#define DC_DEV_DECCHIP_21040 0x00021011
23#define DC_DEV_DECCHIP_21041 0x00141011
24#define DC_DEV_DECCHIP_21140 0x00091011
25#define DC_DEV_INTEL_21143 0x00191011
26#define DC_DEV_INTEL_21145 0x00398086
27
28#define DC_DESCRIPTOR_ALIGNMENT 4
29#define DC_SETUP_FRAME_ALIGNMENT 4
30#define DC_RECEIVE_BUFFER_ALIGNMENT 4
31#define DC_RECEIVE_BUFFER_SIZE_MULTIPLE 4
32
33#define DC_IO_LENGTH 128
34
35#define DC_SETUP_FRAME_SIZE 192
36
37/* Multicast perfect filter */
38#define DC_SETUP_FRAME_PERFECT_FILTER_ADDRESSES 16
39
40/* -1 for physical address and -1 for broadcast address */
41#define DC_SETUP_FRAME_ADDRESSES (16 - 2)
42
43/* Computed hash of FF:FF:FF:FF:FF:FF */
44#define DC_SETUP_FRAME_BROADCAST_HASH 0xFF
45
46#if (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)
47#define DC_SETUP_FRAME_ENTRY(Value) (Value)
48#else
49#define DC_SETUP_FRAME_ENTRY(Value) ((Value) << 16)
50#endif
51
52#include <pshpack1.h>
53
54/*
55 * Transmit Buffer Descriptor
56 */
57typedef struct _DC_TBD
58{
60#define DC_TBD_STATUS_DEFFERED 0x00000001
61#define DC_TBD_STATUS_UNDERFLOW 0x00000002
62#define DC_TBD_STATUS_LINK_FAIL 0x00000004
63#define DC_TBD_STATUS_COLLISIONS_MASK 0x00000078
64#define DC_TBD_STATUS_HEARTBEAT_FAIL 0x00000080
65#define DC_TBD_STATUS_RETRY_ERROR 0x00000100
66#define DC_TBD_STATUS_LATE_COLLISION 0x00000200
67#define DC_TBD_STATUS_NO_CARRIER 0x00000400
68#define DC_TBD_STATUS_CARRIER_LOST 0x00000800
69#define DC_TBD_STATUS_JABBER_TIMEOUT 0x00004000
70#define DC_TBD_STATUS_ERROR_SUMMARY 0x00008000
71#define DC_TBD_STATUS_OWNED 0x80000000
72
73#define DC_TBD_STATUS_SETUP_FRAME 0x7FFFFFFF
74
75#define DC_TBD_STATUS_COLLISIONS_SHIFT 3
76
78#define DC_TBD_CONTROL_LENGTH_MASK_1 0x000007FF
79#define DC_TBD_CONTROL_LENGTH_MASK_2 0x003FF800
80#define DC_TBD_CONTROL_NO_PAD 0x00800000
81#define DC_TBD_CONTROL_CHAINED 0x01000000
82#define DC_TBD_CONTROL_END_OF_RING 0x02000000
83#define DC_TBD_CONTROL_NO_CRC 0x04000000
84#define DC_TBD_CONTROL_SETUP_FRAME 0x08000000
85#define DC_TBD_CONTROL_FIRST_FRAGMENT 0x20000000
86#define DC_TBD_CONTROL_LAST_FRAGMENT 0x40000000
87#define DC_TBD_CONTROL_REQUEST_INTERRUPT 0x80000000
88#define DC_TBD_CONTROL_PERFECT_FILTER 0x00000000
89#define DC_TBD_CONTROL_HASH_PERFECT_FILTER 0x00400000
90#define DC_TBD_CONTROL_INVERSE_FILTER 0x10000000
91#define DC_TBD_CONTROL_IMPERFECT_FILTER 0x10400000
92
93#define DC_TBD_CONTROL_LENGTH_2_SHIFT 11
94
98
99C_ASSERT(sizeof(DC_TBD) == 16);
100
101/*
102 * Receive Buffer Descriptor
103 */
104typedef struct _DC_RBD
105{
107#define DC_RBD_STATUS_OVERRUN 0x00000001
108#define DC_RBD_STATUS_CRC_ERROR 0x00000002
109#define DC_RBD_STATUS_DRIBBLE 0x00000004
110#define DC_RBD_STATUS_MII_ERROR 0x00000008
111#define DC_RBD_STATUS_WDT_EXPIRED 0x00000010
112#define DC_RBD_STATUS_FRAME_TYPE 0x00000020
113#define DC_RBD_STATUS_COLLISION_SEEN 0x00000040
114#define DC_RBD_STATUS_TOO_LONG 0x00000080
115#define DC_RBD_STATUS_LAST_DESCRIPTOR 0x00000100
116#define DC_RBD_STATUS_FIRST_DESCRIPTOR 0x00000200
117#define DC_RBD_STATUS_MULTICAST 0x00000400
118#define DC_RBD_STATUS_RUNT 0x00000800
119#define DC_RBD_STATUS_DATA_TYPE_MASK 0x00003000
120#define DC_RBD_STATUS_LENGTH_ERROR 0x00004000
121#define DC_RBD_STATUS_ERROR_SUMMARY 0x00008000
122#define DC_RBD_STATUS_FRAME_LENGTH_MASK 0x3FFF0000
123#define DC_RBD_STATUS_FILTERING_FAIL 0x40000000
124#define DC_RBD_STATUS_OWNED 0x80000000
125
126#define DC_RBD_STATUS_FRAME_LENGTH_SHIFT 16
127
129#define DC_RBD_CONTROL_BUFFER_LENGTH_MASK_1 0x000007FF
130#define DC_RBD_CONTROL_BUFFER_LENGTH_MASK_2 0x003FF800
131#define DC_RBD_CONTROL_CHAINED 0x01000000
132#define DC_RBD_CONTROL_END_OF_RING 0x02000000
133
137
138C_ASSERT(sizeof(DC_RBD) == 16);
139
140#define DC_PATTERN_FILTERS 4
141
142/*
143 * Wake-Up Filter Register Block
144 */
146{
147 struct
148 {
150
152#define DC_PATTERN_FILTER_CMD_ENABLE 0x01
153#define DC_PATTERN_FILTER_CMD_INVERSE_MODE 0x02
154#define DC_PATTERN_FILTER_CMD_ADD_PREV 0x04
155#define DC_PATTERN_FILTER_CMD_MULTICAST 0x08
156
159 };
162
164
165#include <poppack.h>
166
167/*
168 * NIC Control and Status Registers
169 */
170typedef enum _DC_CSR
171{
193
194/*
195 * CSR0 Bus Mode
196 */
197#define DC_BUS_MODE_SOFT_RESET 0x00000001
198#define DC_BUS_MODE_BUS_ARB 0x00000002
199#define DC_BUS_MODE_DESC_SKIP_LENGTH_MASK 0x0000007C
200#define DC_BUS_MODE_BUFFERS_BIG_ENDIAN 0x00000080
201#define DC_BUS_MODE_BURST_LENGTH_MASK 0x00003F00
202#define DC_BUS_MODE_CACHE_ALIGNMENT_MASK 0x0000C000
203#define DC_BUS_MODE_DIAGNOSTIC_ADDRESS_SPACE 0x00010000
204#define DC_BUS_MODE_TX_POLL_MASK 0x000E0000
205#define DC_BUS_MODE_DESC_BIG_ENDIAN 0x00100000
206#define DC_BUS_MODE_READ_MULTIPLE 0x00200000
207#define DC_BUS_MODE_READ_LINE 0x00800000
208#define DC_BUS_MODE_WRITE_INVALIDATE 0x01000000
209#define DC_BUS_MODE_ON_NOW_UNLOCK 0x04000000
210
211#define DC_BUS_MODE_BURST_LENGTH_NO_LIMIT 0x00000000
212#define DC_BUS_MODE_BURST_LENGTH_1 0x00000100
213#define DC_BUS_MODE_BURST_LENGTH_2 0x00000200
214#define DC_BUS_MODE_BURST_LENGTH_4 0x00000400
215#define DC_BUS_MODE_BURST_LENGTH_8 0x00000800
216#define DC_BUS_MODE_BURST_LENGTH_16 0x00001000
217#define DC_BUS_MODE_BURST_LENGTH_32 0x00002000
218
219#define DC_BUS_MODE_CACHE_ALIGNMENT_NONE 0x00000000
220#define DC_BUS_MODE_CACHE_ALIGNMENT_8 0x00004000
221#define DC_BUS_MODE_CACHE_ALIGNMENT_16 0x00008000
222#define DC_BUS_MODE_CACHE_ALIGNMENT_32 0x0000C000
223
224#define DC_BUS_MODE_TX_POLL_DISABLED 0x00000000
225#define DC_BUS_MODE_TX_POLL_1 0x00020000
226#define DC_BUS_MODE_TX_POLL_2 0x00040000
227#define DC_BUS_MODE_TX_POLL_3 0x00060000
228#define DC_BUS_MODE_TX_POLL_4 0x00080000
229#define DC_BUS_MODE_TX_POLL_5 0x000A0000
230#define DC_BUS_MODE_TX_POLL_6 0x000C0000
231#define DC_BUS_MODE_TX_POLL_7 0x000E0000
232
233#define DC_BUS_MODE_DESC_SKIP_LENGTH_0 0x00000000
234#define DC_BUS_MODE_DESC_SKIP_LENGTH_1 0x00000004
235#define DC_BUS_MODE_DESC_SKIP_LENGTH_2 0x00000008
236#define DC_BUS_MODE_DESC_SKIP_LENGTH_4 0x00000010
237#define DC_BUS_MODE_DESC_SKIP_LENGTH_8 0x00000020
238#define DC_BUS_MODE_DESC_SKIP_LENGTH_16 0x00000040
239#define DC_BUS_MODE_DESC_SKIP_LENGTH_32 0x00000080
240
241/*
242 * CSR1 Transmit Poll Demand
243 */
244#define DC_TX_POLL_DOORBELL 0x00000001
245
246/*
247 * CSR2 Receive Poll Demand
248 */
249#define DC_RX_POLL_DOORBELL 0x00000001
250
251/*
252 * CSR2 Wake Up Control
253 */
254#define DC_WAKE_UP_CONTROL_LINK_CHANGE 0x00000001
255#define DC_WAKE_UP_CONTROL_MAGIC_PACKET 0x00000002
256#define DC_WAKE_UP_CONTROL_PATTERN_MATCH 0x00000004
257#define DC_WAKE_UP_STATUS_LINK_CHANGE 0x00000010
258#define DC_WAKE_UP_STATUS_MAGIC_PACKET 0x00000020
259#define DC_WAKE_UP_STATUS_PATTERN_MATCH 0x00000040
260#define DC_WAKE_UP_CONTROL_GLOBAL_UNICAST 0x00000200
261#define DC_WAKE_UP_CONTROL_VLAN_ENABLE 0x00000800
262#define DC_WAKE_UP_CONTROL_VLAN_TYPE_MASK 0xFFFF0000
263
264/*
265 * CSR5 Status, CSR7 Irq Mask
266 */
267#define DC_IRQ_TX_OK 0x00000001
268#define DC_IRQ_TX_STOPPED 0x00000002
269#define DC_IRQ_TX_NO_BUFFER 0x00000004
270#define DC_IRQ_TX_JABBER_TIMEOUT 0x00000008
271#define DC_IRQ_LINK_PASS 0x00000010
272#define DC_IRQ_TX_UNDERFLOW 0x00000020
273#define DC_IRQ_RX_OK 0x00000040
274#define DC_IRQ_RX_NO_BUFFER 0x00000080
275#define DC_IRQ_RX_STOPPED 0x00000100
276#define DC_IRQ_RX_WDT_TIMEOUT 0x00000200
277#define DC_IRQ_AUI 0x00000400
278#define DC_IRQ_TX_EARLY 0x00000400
279#define DC_IRQ_FD_FRAME_RECEIVED 0x00000800
280#define DC_IRQ_TIMER_TIMEOUT 0x00000800
281#define DC_IRQ_LINK_FAIL 0x00001000
282#define DC_IRQ_SYSTEM_ERROR 0x00002000
283#define DC_IRQ_RX_EARLY 0x00004000
284#define DC_IRQ_ABNORMAL_SUMMARY 0x00008000
285#define DC_IRQ_NORMAL_SUMMARY 0x00010000
286#define DC_STATUS_RX_STATE_MASK 0x000E0000
287#define DC_STATUS_TX_STATE_MASK 0x00700000
288#define DC_STATUS_SYSTEM_ERROR_MASK 0x03800000
289#define DC_IRQ_GPIO_PORT 0x04000000
290#define DC_IRQ_LINK_CHANGED 0x08000000
291#define DC_IRQ_HPNA_PHY 0x10000000
292
293#define DC_STATUS_TX_STATE_STOPPED 0x00000000
294#define DC_STATUS_TX_STATE_FETCH 0x00100000
295#define DC_STATUS_TX_STATE_WAIT_FOR_END 0x00200000
296#define DC_STATUS_TX_STATE_READ 0x00300000
297#define DC_STATUS_TX_STATE_RESERVED 0x00400000
298#define DC_STATUS_TX_STATE_SETUP_PACKET 0x00500000
299#define DC_STATUS_TX_STATE_SUSPENDED 0x00600000
300#define DC_STATUS_TX_STATE_CLOSE 0x00700000
301
302#define DC_STATUS_RX_STATE_STOPPED 0x00000000
303#define DC_STATUS_RX_STATE_FETCH 0x00020000
304#define DC_STATUS_RX_STATE_CHECK_END 0x00040000
305#define DC_STATUS_RX_STATE_WAIT_FOR_RCV 0x00060000
306#define DC_STATUS_RX_STATE_SUSPENDED 0x00080000
307#define DC_STATUS_RX_STATE_CLOSE_DESC 0x000A0000
308#define DC_STATUS_RX_STATE_FLUSH 0x000C0000
309#define DC_STATUS_RX_STATE_DEQUEUE 0x000E0000
310
311#define DC_STATUS_SYSTEM_ERROR_PARITY 0x00000000
312#define DC_STATUS_SYSTEM_ERROR_MASTER_ABORT 0x00800000
313#define DC_STATUS_SYSTEM_ERROR_TARGET_ABORT 0x01000000
314
315/*
316 * CSR6 Operation Mode
317 */
318#define DC_OPMODE_RX_HASH_PERFECT_FILT 0x00000001
319#define DC_OPMODE_RX_ENABLE 0x00000002
320#define DC_OPMODE_RX_HASH_ONLY_FILT 0x00000004
321#define DC_OPMODE_RX_RUNTS 0x00000008
322#define DC_OPMODE_RX_INVERSE_FILT 0x00000010
323#define DC_OPMODE_BACKOFF_COUNTER 0x00000020
324#define DC_OPMODE_RX_PROMISCUOUS 0x00000040
325#define DC_OPMODE_RX_ALL_MULTICAST 0x00000080
326#define DC_OPMODE_FKD 0x00000100
327#define DC_OPMODE_FULL_DUPLEX 0x00000200
328#define DC_OPMODE_LOOPBACK_MASK 0x00000C00
329#define DC_OPMODE_FORCE_COLLISIONS 0x00001000
330#define DC_OPMODE_TX_ENABLE 0x00002000
331#define DC_OPMODE_TX_THRESHOLD_CTRL_MASK 0x0000C000
332#define DC_OPMODE_TX_BACK_PRESSURE 0x00010000
333#define DC_OPMODE_TX_CAPTURE_EFFECT 0x00020000
334#define DC_OPMODE_PORT_SELECT 0x00040000
335#define DC_OPMODE_PORT_HEARTBEAT_DISABLE 0x00080000
336#define DC_OPMODE_STORE_AND_FORWARD 0x00200000
337#define DC_OPMODE_PORT_XMIT_10 0x00400000
338#define DC_OPMODE_PORT_PCS 0x00800000
339#define DC_OPMODE_PORT_SCRAMBLER 0x01000000
340#define DC_OPMODE_PORT_ALWAYS 0x02000000
341#define DC_OPMODE_ADDR_LSB_IGNORE 0x04000000
342#define DC_OPMODE_RX_RECEIVE_ALL 0x40000000
343#define DC_OPMODE_TX_SPECIAL_CAPTURE_EFFECT 0x80000000
344
345#define DC_OPMODE_LOOPBACK_NORMAL 0x00000000
346#define DC_OPMODE_LOOPBACK_INTERNAL 0x00000400
347#define DC_OPMODE_LOOPBACK_EXTERNAL 0x00000800
348
349#define DC_OPMODE_TX_THRESHOLD_LEVEL 0x00004000
350#define DC_OPMODE_TX_THRESHOLD_MAX 0x0000C000
351
352#define DC_OPMODE_MEDIA_MASK ( \
353 DC_OPMODE_TX_THRESHOLD_CTRL_MASK | \
354 DC_OPMODE_LOOPBACK_MASK | \
355 DC_OPMODE_FULL_DUPLEX | \
356 DC_OPMODE_PORT_SELECT | \
357 DC_OPMODE_PORT_HEARTBEAT_DISABLE | \
358 DC_OPMODE_PORT_XMIT_10 | \
359 DC_OPMODE_PORT_PCS | \
360 DC_OPMODE_PORT_SCRAMBLER)
361
362/*
363 * CSR8 Receive Counters
364 */
365#define DC_COUNTER_RX_NO_BUFFER_MASK 0x0001FFFF
366#define DC_COUNTER_RX_OVERFLOW_MASK 0x1FFE0000
367
368#define DC_COUNTER_RX_OVERFLOW_SHIFT 17
369
370/*
371 * CSR9 Serial Interface
372 */
373#define DC_SERIAL_EE_CS 0x00000001
374#define DC_SERIAL_EE_SK 0x00000002
375#define DC_SERIAL_EE_DI 0x00000004
376#define DC_SERIAL_EE_DO 0x00000008
377#define DC_SERIAL_EE_REG 0x00000400
378#define DC_SERIAL_EE_SR 0x00000800
379#define DC_SERIAL_EE_WR 0x00002000
380#define DC_SERIAL_EE_RD 0x00004000
381#define DC_SERIAL_EE_MOD 0x00008000
382#define DC_SERIAL_MII_MDC 0x00010000
383#define DC_SERIAL_MII_MDO 0x00020000
384#define DC_SERIAL_MII_MII 0x00040000
385#define DC_SERIAL_MII_MDI 0x00080000
386#define DC_SERIAL_EAR_DN 0x80000000
387#define DC_SERIAL_EAR_DT 0x000000FF
388#define DC_SERIAL_SPI_CS 0x00100000
389#define DC_SERIAL_SPI_SK 0x00200000
390#define DC_SERIAL_SPI_DI 0x00400000
391#define DC_SERIAL_SPI_DO 0x00800000
392
393#define DC_SERIAL_EE_DI_SHIFT 2
394#define DC_SERIAL_EE_DO_SHIFT 3
395#define DC_SERIAL_MII_MDO_SHIFT 17
396#define DC_SERIAL_MII_MDI_SHIFT 19
397#define DC_SERIAL_SPI_DI_SHIFT 22
398#define DC_SERIAL_SPI_DO_SHIFT 23
399
400/*
401 * CSR11 Timer
402 */
403#define DC_TIMER_VALUE_MASK 0x0000FFFF
404#define DC_TIMER_CONTINUOUS 0x00010000
405#define DC_TIMER_RX_NUMBER_MASK 0x000E0000
406#define DC_TIMER_RX_TIMER_MASK 0x00F00000
407#define DC_TIMER_TX_NUMBER_MASK 0x07000000
408#define DC_TIMER_TX_TIMER_MASK 0x78000000
409#define DC_TIMER_CYCLE_SIZE 0x80000000
410
411#define DC_TIMER_RX_NUMBER_SHIFT 17
412#define DC_TIMER_RX_TIMER_SHIFT 20
413#define DC_TIMER_TX_NUMBER_SHIFT 24
414#define DC_TIMER_TX_TIMER_SHIFT 27
415
416/*
417 * CSR12 SIA Status
418 */
419#define DC_SIA_STATUS_MII_RECEIVE_ACTIVITY 0x00000001
420#define DC_SIA_STATUS_NETWORK_CONNECTION_ERROR 0x00000002
421#define DC_SIA_STATUS_100T_LINK_FAIL 0x00000002
422#define DC_SIA_STATUS_10T_LINK_FAIL 0x00000004
423#define DC_SIA_STATUS_SELECTED_PORT_ACTIVITY 0x00000100
424#define DC_SIA_STATUS_AUI_ACTIVITY 0x00000100
425#define DC_SIA_STATUS_HPNA_ACTIVITY 0x00000100
426#define DC_SIA_STATUS_NONSEL_PORT_ACTIVITY 0x00000200
427#define DC_SIA_STATUS_10T_ACTIVITY 0x00000200
428#define DC_SIA_STATUS_NSN 0x00000400
429#define DC_SIA_STATUS_TX_REMOTE_FAULT 0x00000800
430#define DC_SIA_STATUS_ANS_MASK 0x00007000
431#define DC_SIA_STATUS_LP_AUTONED_SUPPORTED 0x00008000
432#define DC_SIA_STATUS_LP_CODE_WORD_MASK 0xFFFF0000
433
434#define DC_SIA_STATUS_ANS_AUTONEG_DISABLED 0x00000000
435#define DC_SIA_STATUS_ANS_TX_DISABLE 0x00001000
436#define DC_SIA_STATUS_ANS_ABILITY_DETECT 0x00002000
437#define DC_SIA_STATUS_ANS_ACK_DETECT 0x00003000
438#define DC_SIA_STATUS_ANS_ACK_COMPLETE 0x00004000
439#define DC_SIA_STATUS_ANS_AUTONEG_COMPLETE 0x00005000
440#define DC_SIA_STATUS_ANS_LINK_CHECK 0x00006000
441
442#define DC_SIA_STATUS_LP_CODE_WORD_SHIFT 16
443
444#define DC_GPIO_CONTROL 0x100
445
446/*
447 * CSR13 SIA Connectivity
448 */
449#define DC_SIA_CONN_RESET 0x00000000
450#define DC_SIA_CONN_HPNA 0x00000008
451
452/*
453 * CSR14 SIA Transmit and Receive
454 */
455#define DC_SIA_TXRX_ENCODER 0x00000001
456#define DC_SIA_TXRX_LOOPBACK 0x00000002
457#define DC_SIA_TXRX_DRIVER 0x00000004
458#define DC_SIA_TXRX_LINK_PULSE 0x00000008
459#define DC_SIA_TXRX_COMPENSATION 0x00000030
460#define DC_SIA_TXRX_ADV_10T_HD 0x00000040
461#define DC_SIA_TXRX_AUTONEG 0x00000080
462#define DC_SIA_TXRX_RX_SQUELCH 0x00000100
463#define DC_SIA_TXRX_COLLISION_SQUELCH 0x00000200
464#define DC_SIA_TXRX_COLLISION_DETECT 0x00000400
465#define DC_SIA_TXRX_HEARTBEAT 0x00000800
466#define DC_SIA_TXRX_LINK_TEST 0x00001000
467#define DC_SIA_TXRX_AUTOPOLARITY 0x00002000
468#define DC_SIA_TXRX_SET_POLARITY_PLUS 0x00004000
469#define DC_SIA_TXRX_10T_AUTOSENSE 0x00008000
470#define DC_SIA_TXRX_ADV_100TX_HD 0x00010000
471#define DC_SIA_TXRX_ADV_100TX_FD 0x00020000
472#define DC_SIA_TXRX_ADV_100T4 0x00040000
473
474/*
475 * CSR15 SIA and GPIO
476 */
477#define DC_SIA_GENERAL_JABBER_DISABLE 0x00000001
478#define DC_SIA_GENERAL_HOST_UNJAB 0x00000002
479#define DC_SIA_GENERAL_JABBER_CLOCK 0x00000004
480#define DC_SIA_GENERAL_AUI_BNC_MODE 0x00000008
481#define DC_SIA_GENERAL_RX_WDT_DISABLE 0x00000010
482#define DC_SIA_GENERAL_RX_WDT_RELEASE 0x00000020
483#define DC_SIA_GENERAL_LINK_EXTEND 0x00000800
484#define DC_SIA_GENERAL_RX_MAGIC_PACKET 0x00004000
485#define DC_SIA_GENERAL_HCKR 0x00008000
486#define DC_SIA_GENERAL_GPIO_MASK 0x000F0000
487#define DC_SIA_GENERAL_LGS3 0x00100000
488#define DC_SIA_GENERAL_LGS2 0x00200000
489#define DC_SIA_GENERAL_LGS1 0x00400000
490#define DC_SIA_GENERAL_LGS0 0x00800000
491#define DC_SIA_GENERAL_GEI0 0x01000000
492#define DC_SIA_GENERAL_GEI1 0x02000000
493#define DC_SIA_GENERAL_RECEIVE_MATCH 0x04000000
494#define DC_SIA_GENERAL_CONTROL_WRITE 0x08000000
495#define DC_SIA_GENERAL_GI0 0x10000000
496#define DC_SIA_GENERAL_GI1 0x20000000
497#define DC_SIA_GENERAL_IRQ_RX_MATCH 0x40000000
498
499#define DC_RBD_STATUS_INVALID \
500 (DC_RBD_STATUS_OVERRUN | \
501 DC_RBD_STATUS_CRC_ERROR | \
502 DC_RBD_STATUS_WDT_EXPIRED | \
503 DC_RBD_STATUS_COLLISION_SEEN | \
504 DC_RBD_STATUS_TOO_LONG | \
505 DC_RBD_STATUS_RUNT | \
506 DC_RBD_STATUS_LENGTH_ERROR)
507
508#define DC_GENERIC_IRQ_MASK \
509 (DC_IRQ_TX_OK | DC_IRQ_TX_STOPPED | DC_IRQ_TX_JABBER_TIMEOUT | \
510 DC_IRQ_RX_OK | DC_IRQ_TX_UNDERFLOW | \
511 DC_IRQ_RX_STOPPED | \
512 DC_IRQ_SYSTEM_ERROR | DC_IRQ_ABNORMAL_SUMMARY | DC_IRQ_NORMAL_SUMMARY)
513
514/* Errata: The programming guide incorrectly stated that CSR13 must be set to 0x30480009 */
515#define DC_HPNA_ANALOG_CTRL 0x708A0000
516
517/*
518 * PCI Configuration Registers
519 */
520#define DC_PCI_DEVICE_CONFIG 0x40
521#define DC_PCI_DEVICE_CONFIG_SNOOZE 0x40000000
522#define DC_PCI_DEVICE_CONFIG_SLEEP 0x80000000
523
524/*
525 * SPI Interface
526 */
527#define DC_SPI_BYTE_WRITE_OPERATION 2
528#define DC_SPI_BYTE_READ_OPERATION 3
529#define DC_SPI_CLEAR_WRITE_ENABLE 4
530#define DC_SPI_SET_WRITE_ENABLE 6
531
532/*
533 * HomePNA PHY Registers
534 */
535#define HPNA_CONTROL_LOW 0x00
536#define HPNA_CONTROL_HIGH 0x01
537#define HPNA_NOISE 0x10
538#define HPNA_NOISE_FLOOR 0x12
539#define HPNA_NOISE_CEILING 0x13
540#define HPNA_NOISE_ATTACK 0x14
541
542/*
543 * MDIO Protocol (IEEE 802.3)
544 */
545#define MDIO_START 0x01
546#define MDIO_WRITE 0x01
547#define MDIO_READ 0x02
548#define MDIO_TA 0x02
549#define MDIO_PREAMBLE 0xFFFFFFFF
550
551#define MII_MAX_PHY_ADDRESSES 32
552
553/*
554 * PHY register definitions (IEEE 802.3)
555 */
556#define MII_CONTROL 0x00
557#define MII_CR_COLLISION_TEST 0x0080
558#define MII_CR_FULL_DUPLEX 0x0100
559#define MII_CR_AUTONEG_RESTART 0x0200
560#define MII_CR_ISOLATE 0x0400
561#define MII_CR_POWER_DOWN 0x0800
562#define MII_CR_AUTONEG 0x1000
563#define MII_CR_SPEED_SELECTION 0x2000
564#define MII_CR_LOOPBACK 0x4000
565#define MII_CR_RESET 0x8000
566#define MII_STATUS 0x01
567#define MII_SR_LINK_STATUS 0x0004
568#define MII_SR_AUTONEG_COMPLETE 0x0020
569#define MII_PHY_ID1 0x02
570#define MII_PHY_ID2 0x03
571#define MII_AUTONEG_ADVERTISE 0x04
572#define MII_ADV_CSMA 0x0001
573#define MII_ADV_10T_HD 0x0020
574#define MII_ADV_10T_FD 0x0040
575#define MII_ADV_100T_HD 0x0080
576#define MII_ADV_100T_FD 0x0100
577#define MII_ADV_100T4 0x0200
578#define MII_ADV_PAUSE_SYM 0x0400
579#define MII_ADV_PAUSE_ASYM 0x0800
580#define MII_AUTONEG_LINK_PARTNER 0x05
581#define MII_LP_10T_HD 0x0020
582#define MII_LP_10T_FD 0x0040
583#define MII_LP_100T_HD 0x0080
584#define MII_LP_100T_FD 0x0100
585#define MII_LP_100T4 0x0200
586#define MII_LP_PAUSE_SYM 0x0400
587#define MII_LP_PAUSE_ASYM 0x0800
588#define MII_AUTONEG_EXPANSION 0x06
589#define MII_EXP_LP_AUTONEG 0x0001
590#define MII_MASTER_SLAVE_CONTROL 0x09
591#define MII_MS_CR_1000T_HD 0x0100
592#define MII_MS_CR_1000T_FD 0x0200
593#define MII_MASTER_SLAVE_STATUS 0x0A
594#define MII_MS_SR_1000T_FD 0x0800
595
596#define MII_ADV_100 \
597 (MII_ADV_100T_HD | MII_ADV_100T_FD | MII_ADV_100T4)
enum _DC_CSR DC_CSR
struct _DC_RBD * PDC_RBD
enum _DC_CHIP_TYPE DC_CHIP_TYPE
_DC_CHIP_TYPE
Definition: dc21x4hw.h:11
@ DC21145
Definition: dc21x4hw.h:16
@ DC21140
Definition: dc21x4hw.h:14
@ DC21041
Definition: dc21x4hw.h:13
@ DC21040
Definition: dc21x4hw.h:12
@ DC21143
Definition: dc21x4hw.h:15
struct _DC_TBD DC_TBD
_DC_CSR
Definition: dc21x4hw.h:171
@ DcCsr9_SerialInterface
Definition: dc21x4hw.h:183
@ DcCsr10_BootRom
Definition: dc21x4hw.h:184
@ DcCsr14_SiaTxRx
Definition: dc21x4hw.h:190
@ DcCsr6_OpMode
Definition: dc21x4hw.h:180
@ DcCsr15_SiaGeneral
Definition: dc21x4hw.h:191
@ DcCsr0_BusMode
Definition: dc21x4hw.h:172
@ DcCsr2_RxPoll
Definition: dc21x4hw.h:175
@ DcCsr1_WakeUpFilter
Definition: dc21x4hw.h:174
@ DcCsr4_TxRingAddress
Definition: dc21x4hw.h:178
@ DcCsr11_FullDuplex
Definition: dc21x4hw.h:185
@ DcCsr12_Gpio
Definition: dc21x4hw.h:187
@ DcCsr2_WakeUpControl
Definition: dc21x4hw.h:176
@ DcCsr5_Status
Definition: dc21x4hw.h:179
@ DcCsr13_SiaConnectivity
Definition: dc21x4hw.h:189
@ DcCsr1_TxPoll
Definition: dc21x4hw.h:173
@ DcCsr12_SiaStatus
Definition: dc21x4hw.h:188
@ DcCsr8_RxCounters
Definition: dc21x4hw.h:182
@ DcCsr7_IrqMask
Definition: dc21x4hw.h:181
@ DcCsr11_Timer
Definition: dc21x4hw.h:186
@ DcCsr3_RxRingAddress
Definition: dc21x4hw.h:177
union _DC_PATTERN_FILTER_BLOCK * PDC_PATTERN_FILTER_BLOCK
union _DC_PATTERN_FILTER_BLOCK DC_PATTERN_FILTER_BLOCK
struct _DC_TBD * PDC_TBD
#define DC_PATTERN_FILTERS
Definition: dc21x4hw.h:140
struct _DC_RBD DC_RBD
#define C_ASSERT(e)
Definition: intsafe.h:73
_In_ ULONG _In_ ULONG Offset
Definition: ntddpcm.h:101
unsigned short USHORT
Definition: pedump.c:61
Definition: shell.h:41
ULONG Control
Definition: dc21x4hw.h:128
ULONG Address1
Definition: dc21x4hw.h:134
ULONG Address2
Definition: dc21x4hw.h:135
ULONG Status
Definition: dc21x4hw.h:106
ULONG Status
Definition: dc21x4hw.h:59
ULONG Address1
Definition: dc21x4hw.h:95
ULONG Control
Definition: dc21x4hw.h:77
ULONG Address2
Definition: dc21x4hw.h:96
uint32_t ULONG
Definition: typedefs.h:59
ULONG Mask[DC_PATTERN_FILTERS]
Definition: dc21x4hw.h:149
USHORT Crc[DC_PATTERN_FILTERS]
Definition: dc21x4hw.h:158
unsigned char UCHAR
Definition: xmlstorage.h:181