131 if (!
MiiWrite(Adapter, Adapter->PhyAddress, Sequence[
i].Register, Sequence[
i].Data))
201 if (DisableCrossoverDetection)
207 MiiRegister &= ~PHY_REALTEK_INIT_MSK1;
277 MiiRegister &= ~PHY_VITESSE_INIT_MSK1;
289 MiiRegister &= ~PHY_VITESSE_INIT_MSK1;
309 MiiRegister &= ~PHY_VITESSE_INIT_MSK2;
361 ULONG PhyInterface, MiiRegister, MiiStatus, MiiControl;
371 MiiRegister &= ~PHY_MARVELL_E3016_INITMASK;
463 ULONG MiiControl1000;
468 MiiControl1000 &= ~MII_MS_CR_1000T_HD;
472 MiiControl1000 &= ~MII_MS_CR_1000T_FD;
481 Adapter->Flags &= ~NV_GIGABIT_PHY;
571 for (Phy = 1; Phy <= 32; ++Phy)
573 ULONG PhyAddress = Phy & 0x1F;
574 ULONG PhyIdLow, PhyIdHigh;
578 if (PhyIdLow == 0xFFFF)
583 if (PhyIdHigh == 0xFFFF)
586 Adapter->PhyAddress = PhyAddress;
630 for (
i = 10;
i > 0; --
i)
645 for (
i = 0;
i < 2; ++
i)
675 TxControl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
687 ULONG i, DataReady, DataReady2;
698 for (
i = 100000;
i > 0; --
i)
728 ULONG MiiStatus, AdvLpa;
731 *MiiLinkPartnerAbility = 0;
776 ULONG MiiControl1000, MiiStatus1000;
789 AdvLpa = (*MiiAdvertise) & (*MiiLinkPartnerAbility);
826 ULONG PhyRegister, TxDeferral, PauseFlags, MiiExpansion;
832 RestartTransmitter =
TRUE;
837 RestartReceiver =
TRUE;
844 PhyRegister &= ~NVREG_SLOTTIME_1000_FULL;
859 if (!Adapter->FullDuplex)
923 if (Adapter->FullDuplex)
974 PauseFlags = Adapter->PauseFlags;
979 if (RestartTransmitter)
993 ULONG MiiAdvertise, MiiLinkPartnerAbility, LinkSpeed;
1000 &MiiLinkPartnerAbility,
1003 if (Adapter->FullDuplex == FullDuplex && Adapter->LinkSpeed == LinkSpeed)
1010 Adapter->FullDuplex ?
"full" :
"half",
1012 FullDuplex ?
"full" :
"half"));
1014 Adapter->FullDuplex = FullDuplex;
1015 Adapter->LinkSpeed = LinkSpeed;
1051 PowerState &= ~NVREG_POWERSTATE2_POWERUP_MASK;
1064 RestorePhyState =
TRUE;
1066 PhyState &= ~NVREG_ADAPTCTL_RUNNING;
1081 if (UnitVersion > 0)
1086 Adapter->Flags &= ~NV_MAC_IN_USE;
1101 PhyInitialized =
TRUE;
1116 if (!PhyInitialized)
1138 if (RestorePhyState)
BOOLEAN MiiRead(_In_ PDC21X4_ADAPTER Adapter, _In_ ULONG PhyAddress, _In_ ULONG RegAddress, _Out_ PULONG Data)
BOOLEAN MiiWrite(_In_ PDC21X4_ADAPTER Adapter, _In_ ULONG PhyAddress, _In_ ULONG RegAddress, _In_ ULONG Data)
#define MII_EXP_LP_AUTONEG
#define MII_MASTER_SLAVE_STATUS
#define MII_SR_AUTONEG_COMPLETE
#define MII_MS_SR_1000T_FD
#define MII_ADV_PAUSE_SYM
#define MII_ADV_PAUSE_ASYM
#define MII_AUTONEG_ADVERTISE
#define MII_SR_LINK_STATUS
#define MII_CR_AUTONEG_RESTART
#define MII_MS_CR_1000T_FD
#define MII_AUTONEG_EXPANSION
#define MII_AUTONEG_LINK_PARTNER
#define MII_LP_PAUSE_ASYM
#define MII_MASTER_SLAVE_CONTROL
#define NDIS_DbgPrint(_t_, _x_)
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
#define NdisDprReleaseSpinLock(_SpinLock)
#define NDIS_STATUS_FAILURE
#define NdisStallExecution
#define NDIS_STATUS_SUCCESS
#define NdisDprAcquireSpinLock(_SpinLock)
VOID EXPORT NdisMSleep(IN ULONG MicrosecondsToSleep)
VOID NvNetStartTransmitter(_In_ PNVNET_ADAPTER Adapter)
VOID NvNetStartReceiver(_In_ PNVNET_ADAPTER Adapter)
VOID NvNetStopReceiver(_In_ PNVNET_ADAPTER Adapter)
VOID NvNetStopTransmitter(_In_ PNVNET_ADAPTER Adapter)
VOID NvNetUpdatePauseFrame(_Inout_ PNVNET_ADAPTER Adapter, _In_ ULONG PauseFlags)
#define NVREG_MGMTUNITVERSION
#define PHY_VITESSE_INIT8
#define PHY_MODEL_MARVELL_E3016
#define NVREG_MGMTUNITGETVERSION
#define DEV_HAS_POWER_CNTRL
#define PHY_REALTEK_INIT2
#define PHY_MODEL_REALTEK_8201
#define NVREG_XMITCTL_SYNC_MASK
#define PHY_REALTEK_INIT_REG3
#define PHY_VITESSE_INIT10
#define PHY_REALTEK_INIT_REG6
#define PHY_MODEL_REALTEK_8211
#define NVREG_RCVCTL_START
#define PHY_VITESSE_INIT_REG3
#define NVREG_MIISTAT_MASK_RW
#define PHY_REV_REALTEK_8211B
#define NV_PAUSEFRAME_TX_REQ
#define PHY_VITESSE_INIT1
#define NVREG_XMITCTL_DATA_START
#define PHY_VITESSE_INIT2
#define PHY_REALTEK_INIT5
#define PHY_CICADA_INIT_REG3
#define PHY_REALTEK_INIT4
#define DEV_NEED_PHY_INIT_FIX
#define PHY_REALTEK_INIT1
#define NVREG_MISC1_FORCE
#define NVREG_MIICTL_INUSE
#define NVREG_XMITCTL_START
#define NV_PAUSEFRAME_AUTONEG
#define PHY_MARVELL_INIT_REG1
#define NVREG_TX_WM_DESC1_DEFAULT
#define NVREG_LINKSPEED_1000
#define DEV_HAS_LARGEDESC
#define PHY_VITESSE_INIT5
#define NVREG_LINKSPEED_100
#define NVREG_SLOTTIME_1000_FULL
#define NVREG_SLOTTIME_10_100_FULL
#define PHY_REALTEK_INIT3
#define DEV_HAS_COLLISION_FIX
#define NVREG_TX_DEFERRAL_DEFAULT
#define NV_PAUSEFRAME_RX_ENABLE
#define PHY_REALTEK_REVISION
#define NVREG_XMITCTL_HOST_SEMA_ACQ
#define PHY_VITESSE_INIT_REG4
#define NV_MIIPHY_DELAYMAX
#define PHY_VITESSE_INIT7
#define PHY_REALTEK_INIT_REG2
#define PHY_REALTEK_INIT_REG1
#define NVREG_XMITCTL_HOST_SEMA_MASK
#define NVREG_XMITCTL_MGMT_ST
#define NVREG_XMITCTL_DATA_ERROR
#define PHY_REALTEK_INIT7
#define NVREG_POWERSTATE2_POWERUP_REV_A3
#define PHY_VITESSE_INIT6
#define PHY_VITESSE_INIT9
#define NVREG_MIICTL_ADDRSHIFT
#define PHY_REALTEK_INIT6
#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100
#define NVREG_TX_WM_DESC2_3_DEFAULT
#define NVREG_ADAPTCTL_RUNNING
#define PHY_REALTEK_INIT_REG4
#define PHY_VITESSE_INIT_REG1
#define NVREG_MGMTUNITCONTROL_INUSE
#define PHY_REALTEK_INIT11
#define NVREG_MIISTAT_MASK_ALL
#define NVREG_TX_WM_DESC2_3_1000
#define PHY_VITESSE_INIT3
#define PHY_REALTEK_INIT_REG7
#define PHYID2_MODEL_MASK
#define PHY_CICADA_INIT_REG1
#define NVREG_MIICTL_WRITE
#define PHY_VITESSE_INIT4
#define DEV_HAS_MGMT_UNIT
#define NVREG_XMITCTL_MGMT_SEMA_MASK
#define PHY_VITESSE_INIT_REG2
#define NV_PAUSEFRAME_TX_ENABLE
#define PHY_CICADA_INIT_REG2
#define NVREG_TX_DEFERRAL_MII_STRETCH
#define PHY_REV_REALTEK_8211C
#define NVREG_XMITCTL_MGMT_SEMA_FREE
#define NVREG_POWERSTATE2_PHY_RESET
#define PHY_REALTEK_INIT9
#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10
#define NVREG_MIISTAT_ERROR
#define NVREG_XMITCTL_SYNC_PHY_INIT
#define NVREG_LINKSPEED_FORCE
#define PHY_REALTEK_INIT10
#define DEV_NEED_LOW_POWER_FIX
#define NVREG_LINKSPEED_10
@ NvRegMgmtUnitGetVersion
@ NvRegTransmitterControl
#define NVREG_TX_DEFERRAL_RGMII_1000
#define PHY_REALTEK_INIT_REG5
#define NV_PAUSEFRAME_RX_REQ
#define NVREG_XMITCTL_DATA_READY
static VOID NvNetSetSpeedAndDuplex(_In_ PNVNET_ADAPTER Adapter, _In_ ULONG MiiAdvertise, _In_ ULONG MiiLinkPartnerAbility)
static BOOLEAN PhyInitRealtek8211c(_In_ PNVNET_ADAPTER Adapter)
VOID SidebandUnitReleaseSemaphore(_In_ PNVNET_ADAPTER Adapter)
static BOOLEAN PhyInitRealtek8211b(_In_ PNVNET_ADAPTER Adapter)
static BOOLEAN FindPhyDevice(_Inout_ PNVNET_ADAPTER Adapter)
static BOOLEAN SidebandUnitAcquireSemaphore(_Inout_ PNVNET_ADAPTER Adapter)
static BOOLEAN SidebandUnitGetVersion(_In_ PNVNET_ADAPTER Adapter, _Out_ PULONG Version)
static BOOLEAN PhyInitRealtek8201(_In_ PNVNET_ADAPTER Adapter, _In_ BOOLEAN DisableCrossoverDetection)
BOOLEAN NvNetUpdateLinkSpeed(_In_ PNVNET_ADAPTER Adapter)
static NDIS_STATUS PhyInit(_In_ PNVNET_ADAPTER Adapter)
static BOOLEAN PhyInitVitesseSemiconductor(_In_ PNVNET_ADAPTER Adapter)
static BOOLEAN PhyInitCicadaSemiconductor(_In_ PNVNET_ADAPTER Adapter, _In_ ULONG PhyInterface)
static BOOLEAN PhyReset(_In_ PNVNET_ADAPTER Adapter, _In_ ULONG ControlSetup)
static BOOLEAN MiiGetSpeedAndDuplex(_In_ PNVNET_ADAPTER Adapter, _Out_ PULONG MiiAdvertise, _Out_ PULONG MiiLinkPartnerAbility, _Out_ PULONG LinkSpeed, _Out_ PBOOLEAN FullDuplex)
NDIS_STATUS NvNetPhyInit(_In_ PNVNET_ADAPTER Adapter)
#define NV_UNIT_SEMAPHORE_ACQUIRED
#define NV_FORCE_SPEED_AND_DUPLEX
#define NV_FORCE_FULL_DUPLEX
FORCEINLINE VOID NV_WRITE(_In_ PNVNET_ADAPTER Adapter, _In_ NVNET_REGISTER Register, _In_ ULONG Value)
FORCEINLINE ULONG NV_READ(_In_ PNVNET_ADAPTER Adapter, _In_ NVNET_REGISTER Register)
#define NV_USER_SPEED_100
_Must_inspect_result_ _In_ PWDFDEVICE_INIT _In_ WDF_DEVICE_POWER_STATE PowerState
_Must_inspect_result_ _In_ WDFDEVICE _In_ LPCGUID _Out_ PINTERFACE _In_ USHORT _In_ USHORT Version