ReactOS  0.4.15-dev-5097-g328cc41
nic.h File Reference
#include <pshpack1.h>
#include <poppack.h>
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Classes

struct  _NVNET_DESCRIPTOR_32
 
struct  _NVNET_DESCRIPTOR_64
 

Macros

#define DEV_NEED_TIMERIRQ   0x00000001 /* Set the timer IRQ flag in the IRQ mask */
 
#define DEV_NEED_LINKTIMER   0x00000002 /* Poll link settings. Relies on the timer IRQ */
 
#define DEV_HAS_LARGEDESC
 
#define DEV_HAS_HIGH_DMA   0x00000008 /* Device supports 64-bit DMA */
 
#define DEV_HAS_CHECKSUM   0x00000010 /* Device supports TX and RX checksum offloads */
 
#define DEV_HAS_VLAN   0x00000020 /* Device supports VLAN tagging and striping */
 
#define DEV_HAS_MSI   0x00000040 /* Device supports MSI */
 
#define DEV_HAS_MSI_X   0x00000080 /* Device supports MSI-X */
 
#define DEV_HAS_POWER_CNTRL   0x00000100 /* Device supports power savings */
 
#define DEV_HAS_STATISTICS_V1   0x00000200 /* Device supports HW statistics version 1 */
 
#define DEV_HAS_STATISTICS_V2   0x00000400 /* Device supports HW statistics version 2 */
 
#define DEV_HAS_STATISTICS_V3   0x00000800 /* Device supports HW statistics version 3 */
 
#define DEV_HAS_TEST_EXTENDED   0x00001000 /* Device supports extended diagnostic test */
 
#define DEV_HAS_MGMT_UNIT   0x00002000 /* Device supports management unit */
 
#define DEV_HAS_CORRECT_MACADDR   0x00004000 /* Device supports correct MAC address order */
 
#define DEV_HAS_COLLISION_FIX   0x00008000 /* Device supports TX collision fix */
 
#define DEV_HAS_PAUSEFRAME_TX_V1   0x00010000 /* Device supports TX pause frames version 1 */
 
#define DEV_HAS_PAUSEFRAME_TX_V2   0x00020000 /* Device supports TX pause frames version 2 */
 
#define DEV_HAS_PAUSEFRAME_TX_V3   0x00040000 /* Device supports TX pause frames version 3 */
 
#define DEV_NEED_TX_LIMIT   0x00080000 /* Device needs to limit TX */
 
#define DEV_NEED_TX_LIMIT2   0x00100000 /* Device needs to limit TX, expect for some revs */
 
#define DEV_HAS_GEAR_MODE   0x00200000 /* Device supports gear mode */
 
#define DEV_NEED_PHY_INIT_FIX   0x00400000 /* Device needs specific PHY workaround */
 
#define DEV_NEED_LOW_POWER_FIX   0x00800000 /* Device needs special power up workaround */
 
#define DEV_NEED_MSI_FIX   0x01000000 /* Device needs MSI workaround */
 
#define DEV_HAS_STATISTICS_COUNTERS
 
#define DEV_HAS_TX_PAUSEFRAME
 
#define NVREG_IRQSTAT_MIIEVENT   0x040
 
#define NVREG_IRQSTAT_MASK   0x83ff
 
#define NVREG_IRQ_RX_ERROR   0x0001
 
#define NVREG_IRQ_RX   0x0002
 
#define NVREG_IRQ_RX_NOBUF   0x0004
 
#define NVREG_IRQ_TX_ERR   0x0008
 
#define NVREG_IRQ_TX_OK   0x0010
 
#define NVREG_IRQ_TIMER   0x0020
 
#define NVREG_IRQ_LINK   0x0040
 
#define NVREG_IRQ_RX_FORCED   0x0080
 
#define NVREG_IRQ_TX_FORCED   0x0100
 
#define NVREG_IRQ_RECOVER_ERROR   0x8200
 
#define NVREG_IRQMASK_THROUGHPUT   0x00df
 
#define NVREG_IRQMASK_CPU   0x0060
 
#define NVREG_IRQ_TX_ALL   (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 
#define NVREG_IRQ_RX_ALL
 
#define NVREG_IRQ_OTHER   (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 
#define NVREG_UNKSETUP6_VAL   3
 
#define NVREG_POLL_DEFAULT_THROUGHPUT   65535
 
#define NVREG_POLL_DEFAULT_CPU   13
 
#define NVREG_MSI_VECTOR_0_ENABLED   0x01
 
#define NVREG_MAC_RESET_ASSERT   0x0F3
 
#define NVREG_MISC1_PAUSE_TX   0x01
 
#define NVREG_MISC1_HD   0x02
 
#define NVREG_MISC1_FORCE   0x3b0f3c
 
#define NVREG_XMITCTL_START   0x01
 
#define NVREG_XMITCTL_MGMT_ST   0x40000000
 
#define NVREG_XMITCTL_SYNC_MASK   0x000f0000
 
#define NVREG_XMITCTL_SYNC_NOT_READY   0x0
 
#define NVREG_XMITCTL_SYNC_PHY_INIT   0x00040000
 
#define NVREG_XMITCTL_MGMT_SEMA_MASK   0x00000f00
 
#define NVREG_XMITCTL_MGMT_SEMA_FREE   0x0
 
#define NVREG_XMITCTL_HOST_SEMA_MASK   0x0000f000
 
#define NVREG_XMITCTL_HOST_SEMA_ACQ   0x0000f000
 
#define NVREG_XMITCTL_HOST_LOADED   0x00004000
 
#define NVREG_XMITCTL_TX_PATH_EN   0x01000000
 
#define NVREG_XMITCTL_DATA_START   0x00100000
 
#define NVREG_XMITCTL_DATA_READY   0x00010000
 
#define NVREG_XMITCTL_DATA_ERROR   0x00020000
 
#define NVREG_XMITSTAT_BUSY   0x01
 
#define NVREG_PFF_PAUSE_RX   0x08
 
#define NVREG_PFF_ALWAYS   0x7F0000
 
#define NVREG_PFF_PROMISC   0x80
 
#define NVREG_PFF_MYADDR   0x20
 
#define NVREG_PFF_LOOPBACK   0x10
 
#define NVREG_OFFLOAD_HOMEPHY   0x601
 
#define NVREG_OFFLOAD_NORMAL   RX_NIC_BUFSIZE
 
#define NVREG_RCVCTL_START   0x01
 
#define NVREG_RCVCTL_RX_PATH_EN   0x01000000
 
#define NVREG_RCVSTAT_BUSY   0x01
 
#define NVREG_SLOTTIME_LEGBF_ENABLED   0x80000000
 
#define NVREG_SLOTTIME_10_100_FULL   0x00007f00
 
#define NVREG_SLOTTIME_1000_FULL   0x0003ff00
 
#define NVREG_SLOTTIME_HALF   0x0000ff00
 
#define NVREG_SLOTTIME_DEFAULT   0x00007f00
 
#define NVREG_SLOTTIME_MASK   0x000000ff
 
#define NVREG_TX_DEFERRAL_DEFAULT   0x15050f
 
#define NVREG_TX_DEFERRAL_RGMII_10_100   0x16070f
 
#define NVREG_TX_DEFERRAL_RGMII_1000   0x14050f
 
#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10   0x16190f
 
#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100   0x16300f
 
#define NVREG_TX_DEFERRAL_MII_STRETCH   0x152000
 
#define NVREG_RX_DEFERRAL_DEFAULT   0x16
 
#define NVREG_MCASTADDRA_FORCE   0x01
 
#define NVREG_MCASTMASKA_NONE   0xffffffff
 
#define NVREG_MCASTMASKB_NONE   0xffff
 
#define PHY_100   0x1
 
#define PHY_1000   0x2
 
#define PHY_HALF   0x100
 
#define PHY_RGMII   0x10000000
 
#define NVREG_BKOFFCTRL_DEFAULT   0x70000000
 
#define NVREG_BKOFFCTRL_SEED_MASK   0x000003ff
 
#define NVREG_BKOFFCTRL_SELECT   24
 
#define NVREG_BKOFFCTRL_GEAR   12
 
#define NVREG_RINGSZ_TXSHIFT   0
 
#define NVREG_RINGSZ_RXSHIFT   16
 
#define NVREG_TRANSMITPOLL_MAC_ADDR_REV   0x00008000
 
#define NVREG_LINKSPEED_FORCE   0x10000
 
#define NVREG_LINKSPEED_10   1000
 
#define NVREG_LINKSPEED_100   100
 
#define NVREG_LINKSPEED_1000   50
 
#define NVREG_LINKSPEED_MASK   (0xFFF)
 
#define NVREG_UNKSETUP5_BIT31   (1<<31)
 
#define NVREG_TX_WM_DESC1_DEFAULT   0x0200010
 
#define NVREG_TX_WM_DESC2_3_DEFAULT   0x1e08000
 
#define NVREG_TX_WM_DESC2_3_1000   0xfe08000
 
#define NVREG_TXRXCTL_KICK   0x0001
 
#define NVREG_TXRXCTL_BIT1   0x0002
 
#define NVREG_TXRXCTL_BIT2   0x0004
 
#define NVREG_TXRXCTL_IDLE   0x0008
 
#define NVREG_TXRXCTL_RESET   0x0010
 
#define NVREG_TXRXCTL_RXCHECK   0x0400
 
#define NVREG_TXRXCTL_DESC_1   0
 
#define NVREG_TXRXCTL_DESC_2   0x002100
 
#define NVREG_TXRXCTL_DESC_3   0xc02200
 
#define NVREG_TXRXCTL_VLANSTRIP   0x00040
 
#define NVREG_TXRXCTL_VLANINS   0x00080
 
#define NVREG_TX_PAUSEFRAME_DISABLE   0x0fff0080
 
#define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 
#define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 
#define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 
#define NVREG_TX_PAUSEFRAMELIMIT_ENABLE   0x00010000
 
#define NVREG_MIISTAT_ERROR   0x0001
 
#define NVREG_MIISTAT_LINKCHANGE   0x0008
 
#define NVREG_MIISTAT_MASK_RW   0x0007
 
#define NVREG_MIISTAT_MASK_ALL   0x000f
 
#define NVREG_MII_LINKCHANGE   0x0008
 
#define NVREG_ADAPTCTL_START   0x02
 
#define NVREG_ADAPTCTL_LINKUP   0x04
 
#define NVREG_ADAPTCTL_PHYVALID   0x40000
 
#define NVREG_ADAPTCTL_RUNNING   0x100000
 
#define NVREG_ADAPTCTL_PHYSHIFT   24
 
#define NVREG_MIISPEED_BIT8   (1<<8)
 
#define NVREG_MIIDELAY   5
 
#define NVREG_MIICTL_INUSE   0x08000
 
#define NVREG_MIICTL_WRITE   0x00400
 
#define NVREG_MIICTL_ADDRSHIFT   5
 
#define NVREG_WAKEUPFLAGS_VAL   0x7770
 
#define NVREG_WAKEUPFLAGS_BUSYSHIFT   24
 
#define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 
#define NVREG_WAKEUPFLAGS_D3SHIFT   12
 
#define NVREG_WAKEUPFLAGS_D2SHIFT   8
 
#define NVREG_WAKEUPFLAGS_D1SHIFT   4
 
#define NVREG_WAKEUPFLAGS_D0SHIFT   0
 
#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT   0x01
 
#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT   0x02
 
#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE   0x04
 
#define NVREG_WAKEUPFLAGS_ENABLE_MAGPAT   0x1111
 
#define NVREG_WAKEUPFLAGS_ENABLE_WAKEUPPAT   0x2222
 
#define NVREG_WAKEUPFLAGS_ENABLE_LINKCHANGE   0x4444
 
#define NVREG_MGMTUNITGETVERSION   0x01
 
#define NVREG_MGMTUNITVERSION   0x08
 
#define NVREG_POWERCAP_D3SUPP   (1<<30)
 
#define NVREG_POWERCAP_D2SUPP   (1<<26)
 
#define NVREG_POWERCAP_D1SUPP   (1<<25)
 
#define NVREG_POWERSTATE_POWEREDUP   0x8000
 
#define NVREG_POWERSTATE_VALID   0x0100
 
#define NVREG_POWERSTATE_MASK   0x0003
 
#define NVREG_POWERSTATE_D0   0x0000
 
#define NVREG_POWERSTATE_D1   0x0001
 
#define NVREG_POWERSTATE_D2   0x0002
 
#define NVREG_POWERSTATE_D3   0x0003
 
#define NVREG_MGMTUNITCONTROL_INUSE   0x20000
 
#define NVREG_VLANCONTROL_ENABLE   0x2000
 
#define NVREG_POWERSTATE2_POWERUP_MASK   0x0F15
 
#define NVREG_POWERSTATE2_POWERUP_REV_A3   0x0001
 
#define NVREG_POWERSTATE2_PHY_RESET   0x0004
 
#define NVREG_POWERSTATE2_GATE_CLOCK_1   0x0100
 
#define NVREG_POWERSTATE2_GATE_CLOCK_2   0x0200
 
#define NVREG_POWERSTATE2_GATE_CLOCK_3   0x0400
 
#define NVREG_POWERSTATE2_GATE_CLOCKS   0x0F00
 
#define NVREG_POWERSTATE2_WAKEUPPAT_5   (1<<16)
 
#define NVREG_POWERSTATE2_WAKEUPPAT_6   (1<<17)
 
#define NVREG_POWERSTATE2_WAKEUPPAT_7   (1<<18)
 
#define FLAG_MASK_V1   0xffff0000
 
#define FLAG_MASK_V2   0xffffc000
 
#define LEN_MASK_V1   (0xffffffff ^ FLAG_MASK_V1)
 
#define LEN_MASK_V2   (0xffffffff ^ FLAG_MASK_V2)
 
#define NV_TX_LASTPACKET   (1<<16)
 
#define NV_TX_RETRYERROR   (1<<19)
 
#define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 
#define NV_TX_ONE_RETRY   (1<<20)
 
#define NV_TX_FORCED_INTERRUPT   (1<<24)
 
#define NV_TX_DEFERRED   (1<<26)
 
#define NV_TX_CARRIERLOST   (1<<27)
 
#define NV_TX_LATECOLLISION   (1<<28)
 
#define NV_TX_UNDERFLOW   (1<<29)
 
#define NV_TX_ERROR   (1<<30)
 
#define NV_TX_VALID   (1<<31)
 
#define NV_TX2_LASTPACKET   (1<<29)
 
#define NV_TX2_RETRYERROR   (1<<18)
 
#define NV_TX2_RETRYCOUNT_MASK   (0xF<<19)
 
#define NV_TX2_FORCED_INTERRUPT   (1<<30)
 
#define NV_TX2_DEFERRED   (1<<25)
 
#define NV_TX2_CARRIERLOST   (1<<26)
 
#define NV_TX2_LATECOLLISION   (1<<27)
 
#define NV_TX2_UNDERFLOW   (1<<28)
 
#define NV_TX2_ERROR   (1<<30)
 
#define NV_TX2_VALID   (1<<31)
 
#define NV_TX2_TSO   (1<<28)
 
#define NV_TX2_TSO_SHIFT   14
 
#define NV_TX2_TSO_MAX_SHIFT   14
 
#define NV_TX2_CHECKSUM_L3   (1<<27)
 
#define NV_TX2_CHECKSUM_L4   (1<<26)
 
#define NV_MAXIMUM_SG_SIZE   (1<<NV_TX2_TSO_MAX_SHIFT)
 
#define NV_TX3_VLAN_TAG_PRESENT   (1<<18)
 
#define NV_RX_DESCRIPTORVALID   (1<<16)
 
#define NV_RX_MISSEDFRAME   (1<<17)
 
#define NV_RX_SUBTRACT1   (1<<18)
 
#define NV_RX_ERROR1   (1<<23)
 
#define NV_RX_ERROR2   (1<<24)
 
#define NV_RX_ERROR3   (1<<25)
 
#define NV_RX_ERROR4   (1<<26)
 
#define NV_RX_CRCERR   (1<<27)
 
#define NV_RX_OVERFLOW   (1<<28)
 
#define NV_RX_FRAMINGERR   (1<<29)
 
#define NV_RX_ERROR   (1<<30)
 
#define NV_RX_AVAIL   (1<<31)
 
#define NV_RX_ERROR_MASK
 
#define NV_RX2_CHECKSUMMASK   (0x1C000000)
 
#define NV_RX2_CHECKSUM_IP   (0x10000000)
 
#define NV_RX2_CHECKSUM_IP_TCP   (0x14000000)
 
#define NV_RX2_CHECKSUM_IP_UDP   (0x18000000)
 
#define NV_RX2_DESCRIPTORVALID   (1<<29)
 
#define NV_RX2_SUBTRACT1   (1<<25)
 
#define NV_RX2_ERROR1   (1<<18)
 
#define NV_RX2_ERROR2   (1<<19)
 
#define NV_RX2_ERROR3   (1<<20)
 
#define NV_RX2_ERROR4   (1<<21)
 
#define NV_RX2_CRCERR   (1<<22)
 
#define NV_RX2_OVERFLOW   (1<<23)
 
#define NV_RX2_FRAMINGERR   (1<<24)
 
#define NV_RX2_ERROR   (1<<30)
 
#define NV_RX2_AVAIL   (1<<31)
 
#define NV_RX2_ERROR_MASK
 
#define NV_RX3_VLAN_TAG_PRESENT   (1<<16)
 
#define NV_RX3_VLAN_TAG_MASK   (0x0000FFFF)
 
#define NV_TXRX_RESET_DELAY   4
 
#define NV_TXSTOP_DELAY1   10
 
#define NV_TXSTOP_DELAY1MAX   500000
 
#define NV_TXSTOP_DELAY2   100
 
#define NV_TXIDLE_DELAY   10
 
#define NV_TXIDLE_ATTEMPTS   100000
 
#define NV_RXSTOP_DELAY1   10
 
#define NV_RXSTOP_DELAY1MAX   500000
 
#define NV_RXSTOP_DELAY2   100
 
#define NV_SETUP5_DELAY   5
 
#define NV_SETUP5_DELAYMAX   50000
 
#define NV_POWERUP_DELAY   5
 
#define NV_POWERUP_DELAYMAX   5000
 
#define NV_POWER_DELAY   50
 
#define NV_POWER_STALL   3000
 
#define NV_POWER_ATTEMPTS   20
 
#define NV_MIIBUSY_DELAY   50
 
#define NV_MIIPHY_DELAY   10
 
#define NV_MIIPHY_DELAYMAX   10000
 
#define NV_MAC_RESET_DELAY   64
 
#define NV_WAKEUPPATTERNS   5
 
#define NV_WAKEUPPATTERNS_V2   8
 
#define NV_WAKEUPMASKENTRIES   4
 
#define NV_PATTERN_V2_OFFSET   0x39C
 
#define NV_RX_HEADERS   (64)
 
#define NV_RX_ALLOC_PAD   (64)
 
#define PHY_OUI_MARVELL   0x5043
 
#define PHY_OUI_CICADA   0x03f1
 
#define PHY_OUI_VITESSE   0x01c1
 
#define PHY_OUI_REALTEK   0x0732
 
#define PHY_OUI_REALTEK2   0x0020
 
#define PHY_MODEL_REALTEK_8211   0x0110
 
#define PHY_MODEL_REALTEK_8201   0x0200
 
#define PHY_MODEL_MARVELL_E3016   0x0220
 
#define PHYID1_OUI_MASK   0x03ff
 
#define PHYID1_OUI_SHFT   6
 
#define PHYID2_MODEL_MASK   0x03f0
 
#define PHYID2_OUI_MASK   0xfc00
 
#define PHYID2_OUI_SHFT   10
 
#define PHY_GIGABIT   0x0100
 
#define PHY_CICADA_INIT_REG1   0x16
 
#define PHY_CICADA_INIT6   0x02000
 
#define PHY_CICADA_INIT_REG2   0x17
 
#define PHY_CICADA_INIT1   0x0f000
 
#define PHY_CICADA_INIT2   0x0e00
 
#define PHY_CICADA_INIT3   0x01000
 
#define PHY_CICADA_INIT4   0x0200
 
#define PHY_CICADA_INIT_REG3   0x1c
 
#define PHY_CICADA_INIT5   0x0004
 
#define PHY_MARVELL_INIT_REG1   0x1c
 
#define PHY_MARVELL_E3016_INITMASK   0x0300
 
#define PHY_VITESSE_INIT_REG2   0x10
 
#define PHY_VITESSE_INIT2   0xaf8a
 
#define PHY_VITESSE_INIT4   0x8f8a
 
#define PHY_VITESSE_INIT5   0xaf86
 
#define PHY_VITESSE_INIT6   0x8f86
 
#define PHY_VITESSE_INIT7   0xaf82
 
#define PHY_VITESSE_INIT9   0x8f82
 
#define PHY_VITESSE_INIT_REG3   0x11
 
#define PHY_VITESSE_INIT_REG4   0x12
 
#define PHY_VITESSE_INIT_MSK1   0xc
 
#define PHY_VITESSE_INIT3   0x8
 
#define PHY_VITESSE_INIT_MSK2   0x0180
 
#define PHY_VITESSE_INIT8   0x0100
 
#define PHY_VITESSE_INIT_REG1   0x1f
 
#define PHY_VITESSE_INIT1   0x52b5
 
#define PHY_VITESSE_INIT10   0x0
 
#define PHY_REALTEK_INIT_REG7   0x01
 
#define PHY_REALTEK_INIT11   0x0200
 
#define PHY_REALTEK_INIT_REG6   0x11
 
#define PHY_REALTEK_INIT7   0x1000
 
#define PHY_REALTEK_INIT9   0x0008
 
#define PHY_REALTEK_INIT_REG3   0x13
 
#define PHY_REALTEK_INIT4   0xad17
 
#define PHY_REALTEK_INIT_REG4   0x14
 
#define PHY_REALTEK_INIT5   0xfb54
 
#define PHY_REALTEK_REVISION   0x17
 
#define PHY_REV_MASK   0x0001
 
#define PHY_REV_REALTEK_8211B   0x0000
 
#define PHY_REV_REALTEK_8211C   0x0001
 
#define PHY_REALTEK_INIT_REG5   0x18
 
#define PHY_REALTEK_INIT6   0xf5c7
 
#define PHY_REALTEK_INIT_REG2   0x19
 
#define PHY_REALTEK_INIT2   0x8e00
 
#define PHY_REALTEK_INIT8   0x0003
 
#define PHY_REALTEK_INIT_MSK1   0x0003
 
#define PHY_REALTEK_INIT_REG1   0x1f
 
#define PHY_REALTEK_INIT1   0x0000
 
#define PHY_REALTEK_INIT3   0x0001
 
#define PHY_REALTEK_INIT10   0x0005
 
#define NV_PAUSEFRAME_RX_CAPABLE   0x0001
 
#define NV_PAUSEFRAME_TX_CAPABLE   0x0002
 
#define NV_PAUSEFRAME_RX_ENABLE   0x0004
 
#define NV_PAUSEFRAME_TX_ENABLE   0x0008
 
#define NV_PAUSEFRAME_RX_REQ   0x0010
 
#define NV_PAUSEFRAME_TX_REQ   0x0020
 
#define NV_PAUSEFRAME_AUTONEG   0x0040
 
#define NV_MSI_X_MAX_VECTORS   8
 
#define NV_MSI_X_VECTORS_MASK   0x000f
 
#define NV_MSI_CAPABLE   0x0010
 
#define NV_MSI_X_CAPABLE   0x0020
 
#define NV_MSI_ENABLED   0x0040
 
#define NV_MSI_X_ENABLED   0x0080
 
#define NV_MSI_X_VECTOR_ALL   0x0
 
#define NV_MSI_X_VECTOR_RX   0x0
 
#define NV_MSI_X_VECTOR_TX   0x1
 
#define NV_MSI_X_VECTOR_OTHER   0x2
 
#define NV_MSI_PRIV_OFFSET   0x68
 
#define NV_MSI_PRIV_VALUE   0xffffffff
 
#define NV_TX_LIMIT_COUNT   16
 

Typedefs

typedef enum _NVNET_REGISTER NVNET_REGISTER
 
typedef struct _NVNET_DESCRIPTOR_32 NVNET_DESCRIPTOR_32
 
typedef struct _NVNET_DESCRIPTOR_32PNVNET_DESCRIPTOR_32
 
typedef struct _NVNET_DESCRIPTOR_64 NVNET_DESCRIPTOR_64
 
typedef struct _NVNET_DESCRIPTOR_64PNVNET_DESCRIPTOR_64
 

Enumerations

enum  _NVNET_REGISTER {
  NvRegIrqStatus = 0x000, NvRegIrqMask = 0x004, NvRegUnknownSetupReg6 = 0x008, NvRegPollingInterval = 0x00c,
  NvRegMSIMap0 = 0x020, NvRegMSIMap1 = 0x024, NvRegMSIIrqMask = 0x030, NvRegMacReset = 0x34,
  NvRegMisc1 = 0x080, NvRegTransmitterControl = 0x084, NvRegTransmitterStatus = 0x088, NvRegPacketFilterFlags = 0x8c,
  NvRegOffloadConfig = 0x90, NvRegReceiverControl = 0x094, NvRegReceiverStatus = 0x98, NvRegSlotTime = 0x9c,
  NvRegTxDeferral = 0xA0, NvRegRxDeferral = 0xA4, NvRegMacAddrA = 0xA8, NvRegMacAddrB = 0xAC,
  NvRegMulticastAddrA = 0xB0, NvRegMulticastAddrB = 0xB4, NvRegMulticastMaskA = 0xB8, NvRegMulticastMaskB = 0xBC,
  NvRegPhyInterface = 0xC0, NvRegBackOffControl = 0xC4, NvRegTxRingPhysAddr = 0x100, NvRegRxRingPhysAddr = 0x104,
  NvRegRingSizes = 0x108, NvRegTransmitPoll = 0x10c, NvRegLinkSpeed = 0x110, NvRegUnknownSetupReg5 = 0x130,
  NvRegTxWatermark = 0x13c, NvRegTxRxControl = 0x144, NvRegTxRingPhysAddrHigh = 0x148, NvRegRxRingPhysAddrHigh = 0x14C,
  NvRegTxPauseFrame = 0x170, NvRegTxPauseFrameLimit = 0x174, NvRegMIIStatus = 0x180, NvRegMIIMask = 0x184,
  NvRegAdapterControl = 0x188, NvRegMIISpeed = 0x18c, NvRegMIIControl = 0x190, NvRegMIIData = 0x194,
  NvRegTxUnicast = 0x1a0, NvRegTxMulticast = 0x1a4, NvRegTxBroadcast = 0x1a8, NvRegWakeUpFlags = 0x200,
  NvRegPatternCrc = 0x204, NvRegPatternMask0 = 0x208, NvRegPatternMask1 = 0x20C, NvRegPatternMask2 = 0x210,
  NvRegPatternMask3 = 0x214, NvRegMgmtUnitGetVersion = 0x204, NvRegMgmtUnitVersion = 0x208, NvRegPowerCap = 0x268,
  NvRegPowerState = 0x26c, NvRegMgmtUnitControl = 0x278, NvRegTxCnt = 0x280, NvRegTxZeroReXmt = 0x284,
  NvRegTxOneReXmt = 0x288, NvRegTxManyReXmt = 0x28c, NvRegTxLateCol = 0x290, NvRegTxUnderflow = 0x294,
  NvRegTxLossCarrier = 0x298, NvRegTxExcessDef = 0x29c, NvRegTxRetryErr = 0x2a0, NvRegRxFrameErr = 0x2a4,
  NvRegRxExtraByte = 0x2a8, NvRegRxLateCol = 0x2ac, NvRegRxRunt = 0x2b0, NvRegRxFrameTooLong = 0x2b4,
  NvRegRxOverflow = 0x2b8, NvRegRxFCSErr = 0x2bc, NvRegRxFrameAlignErr = 0x2c0, NvRegRxLenErr = 0x2c4,
  NvRegRxUnicast = 0x2c8, NvRegRxMulticast = 0x2cc, NvRegRxBroadcast = 0x2d0, NvRegTxDef = 0x2d4,
  NvRegTxFrame = 0x2d8, NvRegRxCnt = 0x2dc, NvRegTxPause = 0x2e0, NvRegRxPause = 0x2e4,
  NvRegRxDropFrame = 0x2e8, NvRegVlanControl = 0x300, NvRegMSIXMap0 = 0x3e0, NvRegMSIXMap1 = 0x3e4,
  NvRegMSIXIrqStatus = 0x3f0, NvRegPowerState2 = 0x600, NvRegPatternCrcEx = 0x604, NvRegPatternMask0Ex = 0x608,
  NvRegPatternMask1Ex = 0x60C, NvRegPatternMask2Ex = 0x610, NvRegPatternMask3Ex = 0x614
}
 

Macro Definition Documentation

◆ DEV_HAS_CHECKSUM

#define DEV_HAS_CHECKSUM   0x00000010 /* Device supports TX and RX checksum offloads */

Definition at line 23 of file nic.h.

◆ DEV_HAS_COLLISION_FIX

#define DEV_HAS_COLLISION_FIX   0x00008000 /* Device supports TX collision fix */

Definition at line 34 of file nic.h.

◆ DEV_HAS_CORRECT_MACADDR

#define DEV_HAS_CORRECT_MACADDR   0x00004000 /* Device supports correct MAC address order */

Definition at line 33 of file nic.h.

◆ DEV_HAS_GEAR_MODE

#define DEV_HAS_GEAR_MODE   0x00200000 /* Device supports gear mode */

Definition at line 40 of file nic.h.

◆ DEV_HAS_HIGH_DMA

#define DEV_HAS_HIGH_DMA   0x00000008 /* Device supports 64-bit DMA */

Definition at line 22 of file nic.h.

◆ DEV_HAS_LARGEDESC

#define DEV_HAS_LARGEDESC
Value:
0x00000004 /* Device supports Jumbo Frames
* and needs packet format 2 */

Definition at line 20 of file nic.h.

◆ DEV_HAS_MGMT_UNIT

#define DEV_HAS_MGMT_UNIT   0x00002000 /* Device supports management unit */

Definition at line 32 of file nic.h.

◆ DEV_HAS_MSI

#define DEV_HAS_MSI   0x00000040 /* Device supports MSI */

Definition at line 25 of file nic.h.

◆ DEV_HAS_MSI_X

#define DEV_HAS_MSI_X   0x00000080 /* Device supports MSI-X */

Definition at line 26 of file nic.h.

◆ DEV_HAS_PAUSEFRAME_TX_V1

#define DEV_HAS_PAUSEFRAME_TX_V1   0x00010000 /* Device supports TX pause frames version 1 */

Definition at line 35 of file nic.h.

◆ DEV_HAS_PAUSEFRAME_TX_V2

#define DEV_HAS_PAUSEFRAME_TX_V2   0x00020000 /* Device supports TX pause frames version 2 */

Definition at line 36 of file nic.h.

◆ DEV_HAS_PAUSEFRAME_TX_V3

#define DEV_HAS_PAUSEFRAME_TX_V3   0x00040000 /* Device supports TX pause frames version 3 */

Definition at line 37 of file nic.h.

◆ DEV_HAS_POWER_CNTRL

#define DEV_HAS_POWER_CNTRL   0x00000100 /* Device supports power savings */

Definition at line 27 of file nic.h.

◆ DEV_HAS_STATISTICS_COUNTERS

#define DEV_HAS_STATISTICS_COUNTERS
Value:
DEV_HAS_STATISTICS_V3)
#define DEV_HAS_STATISTICS_V2
Definition: nic.h:29
#define DEV_HAS_STATISTICS_V1
Definition: nic.h:28

Definition at line 45 of file nic.h.

◆ DEV_HAS_STATISTICS_V1

#define DEV_HAS_STATISTICS_V1   0x00000200 /* Device supports HW statistics version 1 */

Definition at line 28 of file nic.h.

◆ DEV_HAS_STATISTICS_V2

#define DEV_HAS_STATISTICS_V2   0x00000400 /* Device supports HW statistics version 2 */

Definition at line 29 of file nic.h.

◆ DEV_HAS_STATISTICS_V3

#define DEV_HAS_STATISTICS_V3   0x00000800 /* Device supports HW statistics version 3 */

Definition at line 30 of file nic.h.

◆ DEV_HAS_TEST_EXTENDED

#define DEV_HAS_TEST_EXTENDED   0x00001000 /* Device supports extended diagnostic test */

Definition at line 31 of file nic.h.

◆ DEV_HAS_TX_PAUSEFRAME

#define DEV_HAS_TX_PAUSEFRAME
Value:
DEV_HAS_PAUSEFRAME_TX_V3)
#define DEV_HAS_PAUSEFRAME_TX_V1
Definition: nic.h:35
#define DEV_HAS_PAUSEFRAME_TX_V2
Definition: nic.h:36

Definition at line 47 of file nic.h.

◆ DEV_HAS_VLAN

#define DEV_HAS_VLAN   0x00000020 /* Device supports VLAN tagging and striping */

Definition at line 24 of file nic.h.

◆ DEV_NEED_LINKTIMER

#define DEV_NEED_LINKTIMER   0x00000002 /* Poll link settings. Relies on the timer IRQ */

Definition at line 19 of file nic.h.

◆ DEV_NEED_LOW_POWER_FIX

#define DEV_NEED_LOW_POWER_FIX   0x00800000 /* Device needs special power up workaround */

Definition at line 42 of file nic.h.

◆ DEV_NEED_MSI_FIX

#define DEV_NEED_MSI_FIX   0x01000000 /* Device needs MSI workaround */

Definition at line 43 of file nic.h.

◆ DEV_NEED_PHY_INIT_FIX

#define DEV_NEED_PHY_INIT_FIX   0x00400000 /* Device needs specific PHY workaround */

Definition at line 41 of file nic.h.

◆ DEV_NEED_TIMERIRQ

#define DEV_NEED_TIMERIRQ   0x00000001 /* Set the timer IRQ flag in the IRQ mask */

Definition at line 18 of file nic.h.

◆ DEV_NEED_TX_LIMIT

#define DEV_NEED_TX_LIMIT   0x00080000 /* Device needs to limit TX */

Definition at line 38 of file nic.h.

◆ DEV_NEED_TX_LIMIT2

#define DEV_NEED_TX_LIMIT2   0x00100000 /* Device needs to limit TX, expect for some revs */

Definition at line 39 of file nic.h.

◆ FLAG_MASK_V1

#define FLAG_MASK_V1   0xffff0000

Definition at line 370 of file nic.h.

◆ FLAG_MASK_V2

#define FLAG_MASK_V2   0xffffc000

Definition at line 371 of file nic.h.

◆ LEN_MASK_V1

#define LEN_MASK_V1   (0xffffffff ^ FLAG_MASK_V1)

Definition at line 372 of file nic.h.

◆ LEN_MASK_V2

#define LEN_MASK_V2   (0xffffffff ^ FLAG_MASK_V2)

Definition at line 373 of file nic.h.

◆ NV_MAC_RESET_DELAY

#define NV_MAC_RESET_DELAY   64

Definition at line 464 of file nic.h.

◆ NV_MAXIMUM_SG_SIZE

#define NV_MAXIMUM_SG_SIZE   (1<<NV_TX2_TSO_MAX_SHIFT)

Definition at line 404 of file nic.h.

◆ NV_MIIBUSY_DELAY

#define NV_MIIBUSY_DELAY   50

Definition at line 461 of file nic.h.

◆ NV_MIIPHY_DELAY

#define NV_MIIPHY_DELAY   10

Definition at line 462 of file nic.h.

◆ NV_MIIPHY_DELAYMAX

#define NV_MIIPHY_DELAYMAX   10000

Definition at line 463 of file nic.h.

◆ NV_MSI_CAPABLE

#define NV_MSI_CAPABLE   0x0010

Definition at line 554 of file nic.h.

◆ NV_MSI_ENABLED

#define NV_MSI_ENABLED   0x0040

Definition at line 556 of file nic.h.

◆ NV_MSI_PRIV_OFFSET

#define NV_MSI_PRIV_OFFSET   0x68

Definition at line 564 of file nic.h.

◆ NV_MSI_PRIV_VALUE

#define NV_MSI_PRIV_VALUE   0xffffffff

Definition at line 565 of file nic.h.

◆ NV_MSI_X_CAPABLE

#define NV_MSI_X_CAPABLE   0x0020

Definition at line 555 of file nic.h.

◆ NV_MSI_X_ENABLED

#define NV_MSI_X_ENABLED   0x0080

Definition at line 557 of file nic.h.

◆ NV_MSI_X_MAX_VECTORS

#define NV_MSI_X_MAX_VECTORS   8

Definition at line 552 of file nic.h.

◆ NV_MSI_X_VECTOR_ALL

#define NV_MSI_X_VECTOR_ALL   0x0

Definition at line 559 of file nic.h.

◆ NV_MSI_X_VECTOR_OTHER

#define NV_MSI_X_VECTOR_OTHER   0x2

Definition at line 562 of file nic.h.

◆ NV_MSI_X_VECTOR_RX

#define NV_MSI_X_VECTOR_RX   0x0

Definition at line 560 of file nic.h.

◆ NV_MSI_X_VECTOR_TX

#define NV_MSI_X_VECTOR_TX   0x1

Definition at line 561 of file nic.h.

◆ NV_MSI_X_VECTORS_MASK

#define NV_MSI_X_VECTORS_MASK   0x000f

Definition at line 553 of file nic.h.

◆ NV_PATTERN_V2_OFFSET

#define NV_PATTERN_V2_OFFSET   0x39C

Definition at line 469 of file nic.h.

◆ NV_PAUSEFRAME_AUTONEG

#define NV_PAUSEFRAME_AUTONEG   0x0040

Definition at line 550 of file nic.h.

◆ NV_PAUSEFRAME_RX_CAPABLE

#define NV_PAUSEFRAME_RX_CAPABLE   0x0001

Definition at line 544 of file nic.h.

◆ NV_PAUSEFRAME_RX_ENABLE

#define NV_PAUSEFRAME_RX_ENABLE   0x0004

Definition at line 546 of file nic.h.

◆ NV_PAUSEFRAME_RX_REQ

#define NV_PAUSEFRAME_RX_REQ   0x0010

Definition at line 548 of file nic.h.

◆ NV_PAUSEFRAME_TX_CAPABLE

#define NV_PAUSEFRAME_TX_CAPABLE   0x0002

Definition at line 545 of file nic.h.

◆ NV_PAUSEFRAME_TX_ENABLE

#define NV_PAUSEFRAME_TX_ENABLE   0x0008

Definition at line 547 of file nic.h.

◆ NV_PAUSEFRAME_TX_REQ

#define NV_PAUSEFRAME_TX_REQ   0x0020

Definition at line 549 of file nic.h.

◆ NV_POWER_ATTEMPTS

#define NV_POWER_ATTEMPTS   20

Definition at line 460 of file nic.h.

◆ NV_POWER_DELAY

#define NV_POWER_DELAY   50

Definition at line 458 of file nic.h.

◆ NV_POWER_STALL

#define NV_POWER_STALL   3000

Definition at line 459 of file nic.h.

◆ NV_POWERUP_DELAY

#define NV_POWERUP_DELAY   5

Definition at line 456 of file nic.h.

◆ NV_POWERUP_DELAYMAX

#define NV_POWERUP_DELAYMAX   5000

Definition at line 457 of file nic.h.

◆ NV_RX2_AVAIL

#define NV_RX2_AVAIL   (1<<31)

Definition at line 438 of file nic.h.

◆ NV_RX2_CHECKSUM_IP

#define NV_RX2_CHECKSUM_IP   (0x10000000)

Definition at line 424 of file nic.h.

◆ NV_RX2_CHECKSUM_IP_TCP

#define NV_RX2_CHECKSUM_IP_TCP   (0x14000000)

Definition at line 425 of file nic.h.

◆ NV_RX2_CHECKSUM_IP_UDP

#define NV_RX2_CHECKSUM_IP_UDP   (0x18000000)

Definition at line 426 of file nic.h.

◆ NV_RX2_CHECKSUMMASK

#define NV_RX2_CHECKSUMMASK   (0x1C000000)

Definition at line 423 of file nic.h.

◆ NV_RX2_CRCERR

#define NV_RX2_CRCERR   (1<<22)

Definition at line 433 of file nic.h.

◆ NV_RX2_DESCRIPTORVALID

#define NV_RX2_DESCRIPTORVALID   (1<<29)

Definition at line 427 of file nic.h.

◆ NV_RX2_ERROR

#define NV_RX2_ERROR   (1<<30)

Definition at line 437 of file nic.h.

◆ NV_RX2_ERROR1

#define NV_RX2_ERROR1   (1<<18)

Definition at line 429 of file nic.h.

◆ NV_RX2_ERROR2

#define NV_RX2_ERROR2   (1<<19)

Definition at line 430 of file nic.h.

◆ NV_RX2_ERROR3

#define NV_RX2_ERROR3   (1<<20)

Definition at line 431 of file nic.h.

◆ NV_RX2_ERROR4

#define NV_RX2_ERROR4   (1<<21)

Definition at line 432 of file nic.h.

◆ NV_RX2_ERROR_MASK

#define NV_RX2_ERROR_MASK
Value:
#define NV_RX2_ERROR2
Definition: nic.h:430
#define NV_RX2_ERROR3
Definition: nic.h:431
#define NV_RX2_OVERFLOW
Definition: nic.h:434
#define NV_RX2_ERROR4
Definition: nic.h:432
#define NV_RX2_ERROR1
Definition: nic.h:429
#define NV_RX2_FRAMINGERR
Definition: nic.h:435

Definition at line 439 of file nic.h.

◆ NV_RX2_FRAMINGERR

#define NV_RX2_FRAMINGERR   (1<<24)

Definition at line 435 of file nic.h.

◆ NV_RX2_OVERFLOW

#define NV_RX2_OVERFLOW   (1<<23)

Definition at line 434 of file nic.h.

◆ NV_RX2_SUBTRACT1

#define NV_RX2_SUBTRACT1   (1<<25)

Definition at line 428 of file nic.h.

◆ NV_RX3_VLAN_TAG_MASK

#define NV_RX3_VLAN_TAG_MASK   (0x0000FFFF)

Definition at line 443 of file nic.h.

◆ NV_RX3_VLAN_TAG_PRESENT

#define NV_RX3_VLAN_TAG_PRESENT   (1<<16)

Definition at line 442 of file nic.h.

◆ NV_RX_ALLOC_PAD

#define NV_RX_ALLOC_PAD   (64)

Definition at line 474 of file nic.h.

◆ NV_RX_AVAIL

#define NV_RX_AVAIL   (1<<31)

Definition at line 419 of file nic.h.

◆ NV_RX_CRCERR

#define NV_RX_CRCERR   (1<<27)

Definition at line 415 of file nic.h.

◆ NV_RX_DESCRIPTORVALID

#define NV_RX_DESCRIPTORVALID   (1<<16)

Definition at line 408 of file nic.h.

◆ NV_RX_ERROR

#define NV_RX_ERROR   (1<<30)

Definition at line 418 of file nic.h.

◆ NV_RX_ERROR1

#define NV_RX_ERROR1   (1<<23)

Definition at line 411 of file nic.h.

◆ NV_RX_ERROR2

#define NV_RX_ERROR2   (1<<24)

Definition at line 412 of file nic.h.

◆ NV_RX_ERROR3

#define NV_RX_ERROR3   (1<<25)

Definition at line 413 of file nic.h.

◆ NV_RX_ERROR4

#define NV_RX_ERROR4   (1<<26)

Definition at line 414 of file nic.h.

◆ NV_RX_ERROR_MASK

#define NV_RX_ERROR_MASK
Value:
NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
#define NV_RX_ERROR3
Definition: nic.h:413
#define NV_RX_ERROR2
Definition: nic.h:412
#define NV_RX_ERROR4
Definition: nic.h:414
#define NV_RX_CRCERR
Definition: nic.h:415
#define NV_RX_ERROR1
Definition: nic.h:411
#define NV_RX_FRAMINGERR
Definition: nic.h:417

Definition at line 420 of file nic.h.

◆ NV_RX_FRAMINGERR

#define NV_RX_FRAMINGERR   (1<<29)

Definition at line 417 of file nic.h.

◆ NV_RX_HEADERS

#define NV_RX_HEADERS   (64)

Definition at line 472 of file nic.h.

◆ NV_RX_MISSEDFRAME

#define NV_RX_MISSEDFRAME   (1<<17)

Definition at line 409 of file nic.h.

◆ NV_RX_OVERFLOW

#define NV_RX_OVERFLOW   (1<<28)

Definition at line 416 of file nic.h.

◆ NV_RX_SUBTRACT1

#define NV_RX_SUBTRACT1   (1<<18)

Definition at line 410 of file nic.h.

◆ NV_RXSTOP_DELAY1

#define NV_RXSTOP_DELAY1   10

Definition at line 451 of file nic.h.

◆ NV_RXSTOP_DELAY1MAX

#define NV_RXSTOP_DELAY1MAX   500000

Definition at line 452 of file nic.h.

◆ NV_RXSTOP_DELAY2

#define NV_RXSTOP_DELAY2   100

Definition at line 453 of file nic.h.

◆ NV_SETUP5_DELAY

#define NV_SETUP5_DELAY   5

Definition at line 454 of file nic.h.

◆ NV_SETUP5_DELAYMAX

#define NV_SETUP5_DELAYMAX   50000

Definition at line 455 of file nic.h.

◆ NV_TX2_CARRIERLOST

#define NV_TX2_CARRIERLOST   (1<<26)

Definition at line 392 of file nic.h.

◆ NV_TX2_CHECKSUM_L3

#define NV_TX2_CHECKSUM_L3   (1<<27)

Definition at line 401 of file nic.h.

◆ NV_TX2_CHECKSUM_L4

#define NV_TX2_CHECKSUM_L4   (1<<26)

Definition at line 402 of file nic.h.

◆ NV_TX2_DEFERRED

#define NV_TX2_DEFERRED   (1<<25)

Definition at line 391 of file nic.h.

◆ NV_TX2_ERROR

#define NV_TX2_ERROR   (1<<30)

Definition at line 396 of file nic.h.

◆ NV_TX2_FORCED_INTERRUPT

#define NV_TX2_FORCED_INTERRUPT   (1<<30)

Definition at line 390 of file nic.h.

◆ NV_TX2_LASTPACKET

#define NV_TX2_LASTPACKET   (1<<29)

Definition at line 387 of file nic.h.

◆ NV_TX2_LATECOLLISION

#define NV_TX2_LATECOLLISION   (1<<27)

Definition at line 393 of file nic.h.

◆ NV_TX2_RETRYCOUNT_MASK

#define NV_TX2_RETRYCOUNT_MASK   (0xF<<19)

Definition at line 389 of file nic.h.

◆ NV_TX2_RETRYERROR

#define NV_TX2_RETRYERROR   (1<<18)

Definition at line 388 of file nic.h.

◆ NV_TX2_TSO

#define NV_TX2_TSO   (1<<28)

Definition at line 398 of file nic.h.

◆ NV_TX2_TSO_MAX_SHIFT

#define NV_TX2_TSO_MAX_SHIFT   14

Definition at line 400 of file nic.h.

◆ NV_TX2_TSO_SHIFT

#define NV_TX2_TSO_SHIFT   14

Definition at line 399 of file nic.h.

◆ NV_TX2_UNDERFLOW

#define NV_TX2_UNDERFLOW   (1<<28)

Definition at line 394 of file nic.h.

◆ NV_TX2_VALID

#define NV_TX2_VALID   (1<<31)

Definition at line 397 of file nic.h.

◆ NV_TX3_VLAN_TAG_PRESENT

#define NV_TX3_VLAN_TAG_PRESENT   (1<<18)

Definition at line 406 of file nic.h.

◆ NV_TX_CARRIERLOST

#define NV_TX_CARRIERLOST   (1<<27)

Definition at line 381 of file nic.h.

◆ NV_TX_DEFERRED

#define NV_TX_DEFERRED   (1<<26)

Definition at line 380 of file nic.h.

◆ NV_TX_ERROR

#define NV_TX_ERROR   (1<<30)

Definition at line 384 of file nic.h.

◆ NV_TX_FORCED_INTERRUPT

#define NV_TX_FORCED_INTERRUPT   (1<<24)

Definition at line 379 of file nic.h.

◆ NV_TX_LASTPACKET

#define NV_TX_LASTPACKET   (1<<16)

Definition at line 375 of file nic.h.

◆ NV_TX_LATECOLLISION

#define NV_TX_LATECOLLISION   (1<<28)

Definition at line 382 of file nic.h.

◆ NV_TX_LIMIT_COUNT

#define NV_TX_LIMIT_COUNT   16

Definition at line 567 of file nic.h.

◆ NV_TX_ONE_RETRY

#define NV_TX_ONE_RETRY   (1<<20)

Definition at line 378 of file nic.h.

◆ NV_TX_RETRYCOUNT_MASK

#define NV_TX_RETRYCOUNT_MASK   (0xF<<20)

Definition at line 377 of file nic.h.

◆ NV_TX_RETRYERROR

#define NV_TX_RETRYERROR   (1<<19)

Definition at line 376 of file nic.h.

◆ NV_TX_UNDERFLOW

#define NV_TX_UNDERFLOW   (1<<29)

Definition at line 383 of file nic.h.

◆ NV_TX_VALID

#define NV_TX_VALID   (1<<31)

Definition at line 385 of file nic.h.

◆ NV_TXIDLE_ATTEMPTS

#define NV_TXIDLE_ATTEMPTS   100000

Definition at line 450 of file nic.h.

◆ NV_TXIDLE_DELAY

#define NV_TXIDLE_DELAY   10

Definition at line 449 of file nic.h.

◆ NV_TXRX_RESET_DELAY

#define NV_TXRX_RESET_DELAY   4

Definition at line 445 of file nic.h.

◆ NV_TXSTOP_DELAY1

#define NV_TXSTOP_DELAY1   10

Definition at line 446 of file nic.h.

◆ NV_TXSTOP_DELAY1MAX

#define NV_TXSTOP_DELAY1MAX   500000

Definition at line 447 of file nic.h.

◆ NV_TXSTOP_DELAY2

#define NV_TXSTOP_DELAY2   100

Definition at line 448 of file nic.h.

◆ NV_WAKEUPMASKENTRIES

#define NV_WAKEUPMASKENTRIES   4

Definition at line 468 of file nic.h.

◆ NV_WAKEUPPATTERNS

#define NV_WAKEUPPATTERNS   5

Definition at line 466 of file nic.h.

◆ NV_WAKEUPPATTERNS_V2

#define NV_WAKEUPPATTERNS_V2   8

Definition at line 467 of file nic.h.

◆ NVREG_ADAPTCTL_LINKUP

#define NVREG_ADAPTCTL_LINKUP   0x04

Definition at line 237 of file nic.h.

◆ NVREG_ADAPTCTL_PHYSHIFT

#define NVREG_ADAPTCTL_PHYSHIFT   24

Definition at line 240 of file nic.h.

◆ NVREG_ADAPTCTL_PHYVALID

#define NVREG_ADAPTCTL_PHYVALID   0x40000

Definition at line 238 of file nic.h.

◆ NVREG_ADAPTCTL_RUNNING

#define NVREG_ADAPTCTL_RUNNING   0x100000

Definition at line 239 of file nic.h.

◆ NVREG_ADAPTCTL_START

#define NVREG_ADAPTCTL_START   0x02

Definition at line 236 of file nic.h.

◆ NVREG_BKOFFCTRL_DEFAULT

#define NVREG_BKOFFCTRL_DEFAULT   0x70000000

Definition at line 171 of file nic.h.

◆ NVREG_BKOFFCTRL_GEAR

#define NVREG_BKOFFCTRL_GEAR   12

Definition at line 174 of file nic.h.

◆ NVREG_BKOFFCTRL_SEED_MASK

#define NVREG_BKOFFCTRL_SEED_MASK   0x000003ff

Definition at line 172 of file nic.h.

◆ NVREG_BKOFFCTRL_SELECT

#define NVREG_BKOFFCTRL_SELECT   24

Definition at line 173 of file nic.h.

◆ NVREG_IRQ_LINK

#define NVREG_IRQ_LINK   0x0040

Definition at line 63 of file nic.h.

◆ NVREG_IRQ_OTHER

Definition at line 72 of file nic.h.

◆ NVREG_IRQ_RECOVER_ERROR

#define NVREG_IRQ_RECOVER_ERROR   0x8200

Definition at line 66 of file nic.h.

◆ NVREG_IRQ_RX

#define NVREG_IRQ_RX   0x0002

Definition at line 58 of file nic.h.

◆ NVREG_IRQ_RX_ALL

#define NVREG_IRQ_RX_ALL
Value:
NVREG_IRQ_RX_FORCED)
#define NVREG_IRQ_RX
Definition: nic.h:58
#define NVREG_IRQ_RX_NOBUF
Definition: nic.h:59
#define NVREG_IRQ_RX_ERROR
Definition: nic.h:57

Definition at line 70 of file nic.h.

◆ NVREG_IRQ_RX_ERROR

#define NVREG_IRQ_RX_ERROR   0x0001

Definition at line 57 of file nic.h.

◆ NVREG_IRQ_RX_FORCED

#define NVREG_IRQ_RX_FORCED   0x0080

Definition at line 64 of file nic.h.

◆ NVREG_IRQ_RX_NOBUF

#define NVREG_IRQ_RX_NOBUF   0x0004

Definition at line 59 of file nic.h.

◆ NVREG_IRQ_TIMER

#define NVREG_IRQ_TIMER   0x0020

Definition at line 62 of file nic.h.

◆ NVREG_IRQ_TX_ALL

Definition at line 69 of file nic.h.

◆ NVREG_IRQ_TX_ERR

#define NVREG_IRQ_TX_ERR   0x0008

Definition at line 60 of file nic.h.

◆ NVREG_IRQ_TX_FORCED

#define NVREG_IRQ_TX_FORCED   0x0100

Definition at line 65 of file nic.h.

◆ NVREG_IRQ_TX_OK

#define NVREG_IRQ_TX_OK   0x0010

Definition at line 61 of file nic.h.

◆ NVREG_IRQMASK_CPU

#define NVREG_IRQMASK_CPU   0x0060

Definition at line 68 of file nic.h.

◆ NVREG_IRQMASK_THROUGHPUT

#define NVREG_IRQMASK_THROUGHPUT   0x00df

Definition at line 67 of file nic.h.

◆ NVREG_IRQSTAT_MASK

#define NVREG_IRQSTAT_MASK   0x83ff

Definition at line 54 of file nic.h.

◆ NVREG_IRQSTAT_MIIEVENT

#define NVREG_IRQSTAT_MIIEVENT   0x040

Definition at line 53 of file nic.h.

◆ NVREG_LINKSPEED_10

#define NVREG_LINKSPEED_10   1000

Definition at line 188 of file nic.h.

◆ NVREG_LINKSPEED_100

#define NVREG_LINKSPEED_100   100

Definition at line 189 of file nic.h.

◆ NVREG_LINKSPEED_1000

#define NVREG_LINKSPEED_1000   50

Definition at line 190 of file nic.h.

◆ NVREG_LINKSPEED_FORCE

#define NVREG_LINKSPEED_FORCE   0x10000

Definition at line 187 of file nic.h.

◆ NVREG_LINKSPEED_MASK

#define NVREG_LINKSPEED_MASK   (0xFFF)

Definition at line 191 of file nic.h.

◆ NVREG_MAC_RESET_ASSERT

#define NVREG_MAC_RESET_ASSERT   0x0F3

Definition at line 88 of file nic.h.

◆ NVREG_MCASTADDRA_FORCE

#define NVREG_MCASTADDRA_FORCE   0x01

Definition at line 156 of file nic.h.

◆ NVREG_MCASTMASKA_NONE

#define NVREG_MCASTMASKA_NONE   0xffffffff

Definition at line 159 of file nic.h.

◆ NVREG_MCASTMASKB_NONE

#define NVREG_MCASTMASKB_NONE   0xffff

Definition at line 162 of file nic.h.

◆ NVREG_MGMTUNITCONTROL_INUSE

#define NVREG_MGMTUNITCONTROL_INUSE   0x20000

Definition at line 298 of file nic.h.

◆ NVREG_MGMTUNITGETVERSION

#define NVREG_MGMTUNITGETVERSION   0x01

Definition at line 278 of file nic.h.

◆ NVREG_MGMTUNITVERSION

#define NVREG_MGMTUNITVERSION   0x08

Definition at line 281 of file nic.h.

◆ NVREG_MII_LINKCHANGE

#define NVREG_MII_LINKCHANGE   0x0008

Definition at line 233 of file nic.h.

◆ NVREG_MIICTL_ADDRSHIFT

#define NVREG_MIICTL_ADDRSHIFT   5

Definition at line 249 of file nic.h.

◆ NVREG_MIICTL_INUSE

#define NVREG_MIICTL_INUSE   0x08000

Definition at line 247 of file nic.h.

◆ NVREG_MIICTL_WRITE

#define NVREG_MIICTL_WRITE   0x00400

Definition at line 248 of file nic.h.

◆ NVREG_MIIDELAY

#define NVREG_MIIDELAY   5

Definition at line 244 of file nic.h.

◆ NVREG_MIISPEED_BIT8

#define NVREG_MIISPEED_BIT8   (1<<8)

Definition at line 243 of file nic.h.

◆ NVREG_MIISTAT_ERROR

#define NVREG_MIISTAT_ERROR   0x0001

Definition at line 227 of file nic.h.

◆ NVREG_MIISTAT_LINKCHANGE

#define NVREG_MIISTAT_LINKCHANGE   0x0008

Definition at line 228 of file nic.h.

◆ NVREG_MIISTAT_MASK_ALL

#define NVREG_MIISTAT_MASK_ALL   0x000f

Definition at line 230 of file nic.h.

◆ NVREG_MIISTAT_MASK_RW

#define NVREG_MIISTAT_MASK_RW   0x0007

Definition at line 229 of file nic.h.

◆ NVREG_MISC1_FORCE

#define NVREG_MISC1_FORCE   0x3b0f3c

Definition at line 93 of file nic.h.

◆ NVREG_MISC1_HD

#define NVREG_MISC1_HD   0x02

Definition at line 92 of file nic.h.

◆ NVREG_MISC1_PAUSE_TX

#define NVREG_MISC1_PAUSE_TX   0x01

Definition at line 91 of file nic.h.

◆ NVREG_MSI_VECTOR_0_ENABLED

#define NVREG_MSI_VECTOR_0_ENABLED   0x01

Definition at line 85 of file nic.h.

◆ NVREG_OFFLOAD_HOMEPHY

#define NVREG_OFFLOAD_HOMEPHY   0x601

Definition at line 122 of file nic.h.

◆ NVREG_OFFLOAD_NORMAL

#define NVREG_OFFLOAD_NORMAL   RX_NIC_BUFSIZE

Definition at line 123 of file nic.h.

◆ NVREG_PFF_ALWAYS

#define NVREG_PFF_ALWAYS   0x7F0000

Definition at line 116 of file nic.h.

◆ NVREG_PFF_LOOPBACK

#define NVREG_PFF_LOOPBACK   0x10

Definition at line 119 of file nic.h.

◆ NVREG_PFF_MYADDR

#define NVREG_PFF_MYADDR   0x20

Definition at line 118 of file nic.h.

◆ NVREG_PFF_PAUSE_RX

#define NVREG_PFF_PAUSE_RX   0x08

Definition at line 115 of file nic.h.

◆ NVREG_PFF_PROMISC

#define NVREG_PFF_PROMISC   0x80

Definition at line 117 of file nic.h.

◆ NVREG_POLL_DEFAULT_CPU

#define NVREG_POLL_DEFAULT_CPU   13

Definition at line 79 of file nic.h.

◆ NVREG_POLL_DEFAULT_THROUGHPUT

#define NVREG_POLL_DEFAULT_THROUGHPUT   65535

Definition at line 78 of file nic.h.

◆ NVREG_POWERCAP_D1SUPP

#define NVREG_POWERCAP_D1SUPP   (1<<25)

Definition at line 286 of file nic.h.

◆ NVREG_POWERCAP_D2SUPP

#define NVREG_POWERCAP_D2SUPP   (1<<26)

Definition at line 285 of file nic.h.

◆ NVREG_POWERCAP_D3SUPP

#define NVREG_POWERCAP_D3SUPP   (1<<30)

Definition at line 284 of file nic.h.

◆ NVREG_POWERSTATE2_GATE_CLOCK_1

#define NVREG_POWERSTATE2_GATE_CLOCK_1   0x0100

Definition at line 339 of file nic.h.

◆ NVREG_POWERSTATE2_GATE_CLOCK_2

#define NVREG_POWERSTATE2_GATE_CLOCK_2   0x0200

Definition at line 340 of file nic.h.

◆ NVREG_POWERSTATE2_GATE_CLOCK_3

#define NVREG_POWERSTATE2_GATE_CLOCK_3   0x0400

Definition at line 341 of file nic.h.

◆ NVREG_POWERSTATE2_GATE_CLOCKS

#define NVREG_POWERSTATE2_GATE_CLOCKS   0x0F00

Definition at line 342 of file nic.h.

◆ NVREG_POWERSTATE2_PHY_RESET

#define NVREG_POWERSTATE2_PHY_RESET   0x0004

Definition at line 338 of file nic.h.

◆ NVREG_POWERSTATE2_POWERUP_MASK

#define NVREG_POWERSTATE2_POWERUP_MASK   0x0F15

Definition at line 336 of file nic.h.

◆ NVREG_POWERSTATE2_POWERUP_REV_A3

#define NVREG_POWERSTATE2_POWERUP_REV_A3   0x0001

Definition at line 337 of file nic.h.

◆ NVREG_POWERSTATE2_WAKEUPPAT_5

#define NVREG_POWERSTATE2_WAKEUPPAT_5   (1<<16)

Definition at line 343 of file nic.h.

◆ NVREG_POWERSTATE2_WAKEUPPAT_6

#define NVREG_POWERSTATE2_WAKEUPPAT_6   (1<<17)

Definition at line 344 of file nic.h.

◆ NVREG_POWERSTATE2_WAKEUPPAT_7

#define NVREG_POWERSTATE2_WAKEUPPAT_7   (1<<18)

Definition at line 345 of file nic.h.

◆ NVREG_POWERSTATE_D0

#define NVREG_POWERSTATE_D0   0x0000

Definition at line 292 of file nic.h.

◆ NVREG_POWERSTATE_D1

#define NVREG_POWERSTATE_D1   0x0001

Definition at line 293 of file nic.h.

◆ NVREG_POWERSTATE_D2

#define NVREG_POWERSTATE_D2   0x0002

Definition at line 294 of file nic.h.

◆ NVREG_POWERSTATE_D3

#define NVREG_POWERSTATE_D3   0x0003

Definition at line 295 of file nic.h.

◆ NVREG_POWERSTATE_MASK

#define NVREG_POWERSTATE_MASK   0x0003

Definition at line 291 of file nic.h.

◆ NVREG_POWERSTATE_POWEREDUP

#define NVREG_POWERSTATE_POWEREDUP   0x8000

Definition at line 289 of file nic.h.

◆ NVREG_POWERSTATE_VALID

#define NVREG_POWERSTATE_VALID   0x0100

Definition at line 290 of file nic.h.

◆ NVREG_RCVCTL_RX_PATH_EN

#define NVREG_RCVCTL_RX_PATH_EN   0x01000000

Definition at line 127 of file nic.h.

◆ NVREG_RCVCTL_START

#define NVREG_RCVCTL_START   0x01

Definition at line 126 of file nic.h.

◆ NVREG_RCVSTAT_BUSY

#define NVREG_RCVSTAT_BUSY   0x01

Definition at line 130 of file nic.h.

◆ NVREG_RINGSZ_RXSHIFT

#define NVREG_RINGSZ_RXSHIFT   16

Definition at line 181 of file nic.h.

◆ NVREG_RINGSZ_TXSHIFT

#define NVREG_RINGSZ_TXSHIFT   0

Definition at line 180 of file nic.h.

◆ NVREG_RX_DEFERRAL_DEFAULT

#define NVREG_RX_DEFERRAL_DEFAULT   0x16

Definition at line 149 of file nic.h.

◆ NVREG_SLOTTIME_1000_FULL

#define NVREG_SLOTTIME_1000_FULL   0x0003ff00

Definition at line 135 of file nic.h.

◆ NVREG_SLOTTIME_10_100_FULL

#define NVREG_SLOTTIME_10_100_FULL   0x00007f00

Definition at line 134 of file nic.h.

◆ NVREG_SLOTTIME_DEFAULT

#define NVREG_SLOTTIME_DEFAULT   0x00007f00

Definition at line 137 of file nic.h.

◆ NVREG_SLOTTIME_HALF

#define NVREG_SLOTTIME_HALF   0x0000ff00

Definition at line 136 of file nic.h.

◆ NVREG_SLOTTIME_LEGBF_ENABLED

#define NVREG_SLOTTIME_LEGBF_ENABLED   0x80000000

Definition at line 133 of file nic.h.

◆ NVREG_SLOTTIME_MASK

#define NVREG_SLOTTIME_MASK   0x000000ff

Definition at line 138 of file nic.h.

◆ NVREG_TRANSMITPOLL_MAC_ADDR_REV

#define NVREG_TRANSMITPOLL_MAC_ADDR_REV   0x00008000

Definition at line 184 of file nic.h.

◆ NVREG_TX_DEFERRAL_DEFAULT

#define NVREG_TX_DEFERRAL_DEFAULT   0x15050f

Definition at line 141 of file nic.h.

◆ NVREG_TX_DEFERRAL_MII_STRETCH

#define NVREG_TX_DEFERRAL_MII_STRETCH   0x152000

Definition at line 146 of file nic.h.

◆ NVREG_TX_DEFERRAL_RGMII_1000

#define NVREG_TX_DEFERRAL_RGMII_1000   0x14050f

Definition at line 143 of file nic.h.

◆ NVREG_TX_DEFERRAL_RGMII_10_100

#define NVREG_TX_DEFERRAL_RGMII_10_100   0x16070f

Definition at line 142 of file nic.h.

◆ NVREG_TX_DEFERRAL_RGMII_STRETCH_10

#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10   0x16190f

Definition at line 144 of file nic.h.

◆ NVREG_TX_DEFERRAL_RGMII_STRETCH_100

#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100   0x16300f

Definition at line 145 of file nic.h.

◆ NVREG_TX_PAUSEFRAME_DISABLE

#define NVREG_TX_PAUSEFRAME_DISABLE   0x0fff0080

Definition at line 218 of file nic.h.

◆ NVREG_TX_PAUSEFRAME_ENABLE_V1

#define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010

Definition at line 219 of file nic.h.

◆ NVREG_TX_PAUSEFRAME_ENABLE_V2

#define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0

Definition at line 220 of file nic.h.

◆ NVREG_TX_PAUSEFRAME_ENABLE_V3

#define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880

Definition at line 221 of file nic.h.

◆ NVREG_TX_PAUSEFRAMELIMIT_ENABLE

#define NVREG_TX_PAUSEFRAMELIMIT_ENABLE   0x00010000

Definition at line 224 of file nic.h.

◆ NVREG_TX_WM_DESC1_DEFAULT

#define NVREG_TX_WM_DESC1_DEFAULT   0x0200010

Definition at line 197 of file nic.h.

◆ NVREG_TX_WM_DESC2_3_1000

#define NVREG_TX_WM_DESC2_3_1000   0xfe08000

Definition at line 199 of file nic.h.

◆ NVREG_TX_WM_DESC2_3_DEFAULT

#define NVREG_TX_WM_DESC2_3_DEFAULT   0x1e08000

Definition at line 198 of file nic.h.

◆ NVREG_TXRXCTL_BIT1

#define NVREG_TXRXCTL_BIT1   0x0002

Definition at line 203 of file nic.h.

◆ NVREG_TXRXCTL_BIT2

#define NVREG_TXRXCTL_BIT2   0x0004

Definition at line 204 of file nic.h.

◆ NVREG_TXRXCTL_DESC_1

#define NVREG_TXRXCTL_DESC_1   0

Definition at line 208 of file nic.h.

◆ NVREG_TXRXCTL_DESC_2

#define NVREG_TXRXCTL_DESC_2   0x002100

Definition at line 209 of file nic.h.

◆ NVREG_TXRXCTL_DESC_3

#define NVREG_TXRXCTL_DESC_3   0xc02200

Definition at line 210 of file nic.h.

◆ NVREG_TXRXCTL_IDLE

#define NVREG_TXRXCTL_IDLE   0x0008

Definition at line 205 of file nic.h.

◆ NVREG_TXRXCTL_KICK

#define NVREG_TXRXCTL_KICK   0x0001

Definition at line 202 of file nic.h.

◆ NVREG_TXRXCTL_RESET

#define NVREG_TXRXCTL_RESET   0x0010

Definition at line 206 of file nic.h.

◆ NVREG_TXRXCTL_RXCHECK

#define NVREG_TXRXCTL_RXCHECK   0x0400

Definition at line 207 of file nic.h.

◆ NVREG_TXRXCTL_VLANINS

#define NVREG_TXRXCTL_VLANINS   0x00080

Definition at line 212 of file nic.h.

◆ NVREG_TXRXCTL_VLANSTRIP

#define NVREG_TXRXCTL_VLANSTRIP   0x00040

Definition at line 211 of file nic.h.

◆ NVREG_UNKSETUP5_BIT31

#define NVREG_UNKSETUP5_BIT31   (1<<31)

Definition at line 194 of file nic.h.

◆ NVREG_UNKSETUP6_VAL

#define NVREG_UNKSETUP6_VAL   3

Definition at line 75 of file nic.h.

◆ NVREG_VLANCONTROL_ENABLE

#define NVREG_VLANCONTROL_ENABLE   0x2000

Definition at line 329 of file nic.h.

◆ NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE

#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE   0x04

Definition at line 266 of file nic.h.

◆ NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT

#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT   0x01

Definition at line 264 of file nic.h.

◆ NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT

#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT   0x02

Definition at line 265 of file nic.h.

◆ NVREG_WAKEUPFLAGS_BUSYSHIFT

#define NVREG_WAKEUPFLAGS_BUSYSHIFT   24

Definition at line 258 of file nic.h.

◆ NVREG_WAKEUPFLAGS_D0SHIFT

#define NVREG_WAKEUPFLAGS_D0SHIFT   0

Definition at line 263 of file nic.h.

◆ NVREG_WAKEUPFLAGS_D1SHIFT

#define NVREG_WAKEUPFLAGS_D1SHIFT   4

Definition at line 262 of file nic.h.

◆ NVREG_WAKEUPFLAGS_D2SHIFT

#define NVREG_WAKEUPFLAGS_D2SHIFT   8

Definition at line 261 of file nic.h.

◆ NVREG_WAKEUPFLAGS_D3SHIFT

#define NVREG_WAKEUPFLAGS_D3SHIFT   12

Definition at line 260 of file nic.h.

◆ NVREG_WAKEUPFLAGS_ENABLE_LINKCHANGE

#define NVREG_WAKEUPFLAGS_ENABLE_LINKCHANGE   0x4444

Definition at line 269 of file nic.h.

◆ NVREG_WAKEUPFLAGS_ENABLE_MAGPAT

#define NVREG_WAKEUPFLAGS_ENABLE_MAGPAT   0x1111

Definition at line 267 of file nic.h.

◆ NVREG_WAKEUPFLAGS_ENABLE_WAKEUPPAT

#define NVREG_WAKEUPFLAGS_ENABLE_WAKEUPPAT   0x2222

Definition at line 268 of file nic.h.

◆ NVREG_WAKEUPFLAGS_ENABLESHIFT

#define NVREG_WAKEUPFLAGS_ENABLESHIFT   16

Definition at line 259 of file nic.h.

◆ NVREG_WAKEUPFLAGS_VAL

#define NVREG_WAKEUPFLAGS_VAL   0x7770

Definition at line 257 of file nic.h.

◆ NVREG_XMITCTL_DATA_ERROR

#define NVREG_XMITCTL_DATA_ERROR   0x00020000

Definition at line 109 of file nic.h.

◆ NVREG_XMITCTL_DATA_READY

#define NVREG_XMITCTL_DATA_READY   0x00010000

Definition at line 108 of file nic.h.

◆ NVREG_XMITCTL_DATA_START

#define NVREG_XMITCTL_DATA_START   0x00100000

Definition at line 107 of file nic.h.

◆ NVREG_XMITCTL_HOST_LOADED

#define NVREG_XMITCTL_HOST_LOADED   0x00004000

Definition at line 105 of file nic.h.

◆ NVREG_XMITCTL_HOST_SEMA_ACQ

#define NVREG_XMITCTL_HOST_SEMA_ACQ   0x0000f000

Definition at line 104 of file nic.h.

◆ NVREG_XMITCTL_HOST_SEMA_MASK

#define NVREG_XMITCTL_HOST_SEMA_MASK   0x0000f000

Definition at line 103 of file nic.h.

◆ NVREG_XMITCTL_MGMT_SEMA_FREE

#define NVREG_XMITCTL_MGMT_SEMA_FREE   0x0

Definition at line 102 of file nic.h.

◆ NVREG_XMITCTL_MGMT_SEMA_MASK

#define NVREG_XMITCTL_MGMT_SEMA_MASK   0x00000f00

Definition at line 101 of file nic.h.

◆ NVREG_XMITCTL_MGMT_ST

#define NVREG_XMITCTL_MGMT_ST   0x40000000

Definition at line 97 of file nic.h.

◆ NVREG_XMITCTL_START

#define NVREG_XMITCTL_START   0x01

Definition at line 96 of file nic.h.

◆ NVREG_XMITCTL_SYNC_MASK

#define NVREG_XMITCTL_SYNC_MASK   0x000f0000

Definition at line 98 of file nic.h.

◆ NVREG_XMITCTL_SYNC_NOT_READY

#define NVREG_XMITCTL_SYNC_NOT_READY   0x0

Definition at line 99 of file nic.h.

◆ NVREG_XMITCTL_SYNC_PHY_INIT

#define NVREG_XMITCTL_SYNC_PHY_INIT   0x00040000

Definition at line 100 of file nic.h.

◆ NVREG_XMITCTL_TX_PATH_EN

#define NVREG_XMITCTL_TX_PATH_EN   0x01000000

Definition at line 106 of file nic.h.

◆ NVREG_XMITSTAT_BUSY

#define NVREG_XMITSTAT_BUSY   0x01

Definition at line 112 of file nic.h.

◆ PHY_100

#define PHY_100   0x1

Definition at line 165 of file nic.h.

◆ PHY_1000

#define PHY_1000   0x2

Definition at line 166 of file nic.h.

◆ PHY_CICADA_INIT1

#define PHY_CICADA_INIT1   0x0f000

Definition at line 496 of file nic.h.

◆ PHY_CICADA_INIT2

#define PHY_CICADA_INIT2   0x0e00

Definition at line 497 of file nic.h.

◆ PHY_CICADA_INIT3

#define PHY_CICADA_INIT3   0x01000

Definition at line 498 of file nic.h.

◆ PHY_CICADA_INIT4

#define PHY_CICADA_INIT4   0x0200

Definition at line 499 of file nic.h.

◆ PHY_CICADA_INIT5

#define PHY_CICADA_INIT5   0x0004

Definition at line 501 of file nic.h.

◆ PHY_CICADA_INIT6

#define PHY_CICADA_INIT6   0x02000

Definition at line 494 of file nic.h.

◆ PHY_CICADA_INIT_REG1

#define PHY_CICADA_INIT_REG1   0x16

Definition at line 493 of file nic.h.

◆ PHY_CICADA_INIT_REG2

#define PHY_CICADA_INIT_REG2   0x17

Definition at line 495 of file nic.h.

◆ PHY_CICADA_INIT_REG3

#define PHY_CICADA_INIT_REG3   0x1c

Definition at line 500 of file nic.h.

◆ PHY_GIGABIT

#define PHY_GIGABIT   0x0100

Definition at line 491 of file nic.h.

◆ PHY_HALF

#define PHY_HALF   0x100

Definition at line 167 of file nic.h.

◆ PHY_MARVELL_E3016_INITMASK

#define PHY_MARVELL_E3016_INITMASK   0x0300

Definition at line 503 of file nic.h.

◆ PHY_MARVELL_INIT_REG1

#define PHY_MARVELL_INIT_REG1   0x1c

Definition at line 502 of file nic.h.

◆ PHY_MODEL_MARVELL_E3016

#define PHY_MODEL_MARVELL_E3016   0x0220

Definition at line 483 of file nic.h.

◆ PHY_MODEL_REALTEK_8201

#define PHY_MODEL_REALTEK_8201   0x0200

Definition at line 482 of file nic.h.

◆ PHY_MODEL_REALTEK_8211

#define PHY_MODEL_REALTEK_8211   0x0110

Definition at line 481 of file nic.h.

◆ PHY_OUI_CICADA

#define PHY_OUI_CICADA   0x03f1

Definition at line 477 of file nic.h.

◆ PHY_OUI_MARVELL

#define PHY_OUI_MARVELL   0x5043

Definition at line 476 of file nic.h.

◆ PHY_OUI_REALTEK

#define PHY_OUI_REALTEK   0x0732

Definition at line 479 of file nic.h.

◆ PHY_OUI_REALTEK2

#define PHY_OUI_REALTEK2   0x0020

Definition at line 480 of file nic.h.

◆ PHY_OUI_VITESSE

#define PHY_OUI_VITESSE   0x01c1

Definition at line 478 of file nic.h.

◆ PHY_REALTEK_INIT1

#define PHY_REALTEK_INIT1   0x0000

Definition at line 540 of file nic.h.

◆ PHY_REALTEK_INIT10

#define PHY_REALTEK_INIT10   0x0005

Definition at line 542 of file nic.h.

◆ PHY_REALTEK_INIT11

#define PHY_REALTEK_INIT11   0x0200

Definition at line 521 of file nic.h.

◆ PHY_REALTEK_INIT2

#define PHY_REALTEK_INIT2   0x8e00

Definition at line 536 of file nic.h.

◆ PHY_REALTEK_INIT3

#define PHY_REALTEK_INIT3   0x0001

Definition at line 541 of file nic.h.

◆ PHY_REALTEK_INIT4

#define PHY_REALTEK_INIT4   0xad17

Definition at line 526 of file nic.h.

◆ PHY_REALTEK_INIT5

#define PHY_REALTEK_INIT5   0xfb54

Definition at line 528 of file nic.h.

◆ PHY_REALTEK_INIT6

#define PHY_REALTEK_INIT6   0xf5c7

Definition at line 534 of file nic.h.

◆ PHY_REALTEK_INIT7

#define PHY_REALTEK_INIT7   0x1000

Definition at line 523 of file nic.h.

◆ PHY_REALTEK_INIT8

#define PHY_REALTEK_INIT8   0x0003

Definition at line 537 of file nic.h.

◆ PHY_REALTEK_INIT9

#define PHY_REALTEK_INIT9   0x0008

Definition at line 524 of file nic.h.

◆ PHY_REALTEK_INIT_MSK1

#define PHY_REALTEK_INIT_MSK1   0x0003

Definition at line 538 of file nic.h.

◆ PHY_REALTEK_INIT_REG1

#define PHY_REALTEK_INIT_REG1   0x1f

Definition at line 539 of file nic.h.

◆ PHY_REALTEK_INIT_REG2

#define PHY_REALTEK_INIT_REG2   0x19

Definition at line 535 of file nic.h.

◆ PHY_REALTEK_INIT_REG3

#define PHY_REALTEK_INIT_REG3   0x13

Definition at line 525 of file nic.h.

◆ PHY_REALTEK_INIT_REG4

#define PHY_REALTEK_INIT_REG4   0x14

Definition at line 527 of file nic.h.

◆ PHY_REALTEK_INIT_REG5

#define PHY_REALTEK_INIT_REG5   0x18

Definition at line 533 of file nic.h.

◆ PHY_REALTEK_INIT_REG6

#define PHY_REALTEK_INIT_REG6   0x11

Definition at line 522 of file nic.h.

◆ PHY_REALTEK_INIT_REG7

#define PHY_REALTEK_INIT_REG7   0x01

Definition at line 520 of file nic.h.

◆ PHY_REALTEK_REVISION

#define PHY_REALTEK_REVISION   0x17

Definition at line 529 of file nic.h.

◆ PHY_REV_MASK

#define PHY_REV_MASK   0x0001

Definition at line 530 of file nic.h.

◆ PHY_REV_REALTEK_8211B

#define PHY_REV_REALTEK_8211B   0x0000

Definition at line 531 of file nic.h.

◆ PHY_REV_REALTEK_8211C

#define PHY_REV_REALTEK_8211C   0x0001

Definition at line 532 of file nic.h.

◆ PHY_RGMII

#define PHY_RGMII   0x10000000

Definition at line 168 of file nic.h.

◆ PHY_VITESSE_INIT1

#define PHY_VITESSE_INIT1   0x52b5

Definition at line 518 of file nic.h.

◆ PHY_VITESSE_INIT10

#define PHY_VITESSE_INIT10   0x0

Definition at line 519 of file nic.h.

◆ PHY_VITESSE_INIT2

#define PHY_VITESSE_INIT2   0xaf8a

Definition at line 505 of file nic.h.

◆ PHY_VITESSE_INIT3

#define PHY_VITESSE_INIT3   0x8

Definition at line 514 of file nic.h.

◆ PHY_VITESSE_INIT4

#define PHY_VITESSE_INIT4   0x8f8a

Definition at line 506 of file nic.h.

◆ PHY_VITESSE_INIT5

#define PHY_VITESSE_INIT5   0xaf86

Definition at line 507 of file nic.h.

◆ PHY_VITESSE_INIT6

#define PHY_VITESSE_INIT6   0x8f86

Definition at line 508 of file nic.h.

◆ PHY_VITESSE_INIT7

#define PHY_VITESSE_INIT7   0xaf82

Definition at line 509 of file nic.h.

◆ PHY_VITESSE_INIT8

#define PHY_VITESSE_INIT8   0x0100

Definition at line 516 of file nic.h.

◆ PHY_VITESSE_INIT9

#define PHY_VITESSE_INIT9   0x8f82

Definition at line 510 of file nic.h.

◆ PHY_VITESSE_INIT_MSK1

#define PHY_VITESSE_INIT_MSK1   0xc

Definition at line 513 of file nic.h.

◆ PHY_VITESSE_INIT_MSK2

#define PHY_VITESSE_INIT_MSK2   0x0180

Definition at line 515 of file nic.h.

◆ PHY_VITESSE_INIT_REG1

#define PHY_VITESSE_INIT_REG1   0x1f

Definition at line 517 of file nic.h.

◆ PHY_VITESSE_INIT_REG2

#define PHY_VITESSE_INIT_REG2   0x10

Definition at line 504 of file nic.h.

◆ PHY_VITESSE_INIT_REG3

#define PHY_VITESSE_INIT_REG3   0x11

Definition at line 511 of file nic.h.

◆ PHY_VITESSE_INIT_REG4

#define PHY_VITESSE_INIT_REG4   0x12

Definition at line 512 of file nic.h.

◆ PHYID1_OUI_MASK

#define PHYID1_OUI_MASK   0x03ff

Definition at line 485 of file nic.h.

◆ PHYID1_OUI_SHFT

#define PHYID1_OUI_SHFT   6

Definition at line 486 of file nic.h.

◆ PHYID2_MODEL_MASK

#define PHYID2_MODEL_MASK   0x03f0

Definition at line 487 of file nic.h.

◆ PHYID2_OUI_MASK

#define PHYID2_OUI_MASK   0xfc00

Definition at line 488 of file nic.h.

◆ PHYID2_OUI_SHFT

#define PHYID2_OUI_SHFT   10

Definition at line 489 of file nic.h.

Typedef Documentation

◆ NVNET_DESCRIPTOR_32

◆ NVNET_DESCRIPTOR_64

◆ NVNET_REGISTER

◆ PNVNET_DESCRIPTOR_32

◆ PNVNET_DESCRIPTOR_64

Enumeration Type Documentation

◆ _NVNET_REGISTER

Enumerator
NvRegIrqStatus 
NvRegIrqMask 
NvRegUnknownSetupReg6 
NvRegPollingInterval 
NvRegMSIMap0 
NvRegMSIMap1 
NvRegMSIIrqMask 
NvRegMacReset 
NvRegMisc1 
NvRegTransmitterControl 
NvRegTransmitterStatus 
NvRegPacketFilterFlags 
NvRegOffloadConfig 
NvRegReceiverControl 
NvRegReceiverStatus 
NvRegSlotTime 
NvRegTxDeferral 
NvRegRxDeferral 
NvRegMacAddrA 
NvRegMacAddrB 
NvRegMulticastAddrA 
NvRegMulticastAddrB 
NvRegMulticastMaskA 
NvRegMulticastMaskB 
NvRegPhyInterface 
NvRegBackOffControl 
NvRegTxRingPhysAddr 
NvRegRxRingPhysAddr 
NvRegRingSizes 
NvRegTransmitPoll 
NvRegLinkSpeed 
NvRegUnknownSetupReg5 
NvRegTxWatermark 
NvRegTxRxControl 
NvRegTxRingPhysAddrHigh 
NvRegRxRingPhysAddrHigh 
NvRegTxPauseFrame 
NvRegTxPauseFrameLimit 
NvRegMIIStatus 
NvRegMIIMask 
NvRegAdapterControl 
NvRegMIISpeed 
NvRegMIIControl 
NvRegMIIData 
NvRegTxUnicast 
NvRegTxMulticast 
NvRegTxBroadcast 
NvRegWakeUpFlags 
NvRegPatternCrc 
NvRegPatternMask0 
NvRegPatternMask1 
NvRegPatternMask2 
NvRegPatternMask3 
NvRegMgmtUnitGetVersion 
NvRegMgmtUnitVersion 
NvRegPowerCap 
NvRegPowerState 
NvRegMgmtUnitControl 
NvRegTxCnt 
NvRegTxZeroReXmt 
NvRegTxOneReXmt 
NvRegTxManyReXmt 
NvRegTxLateCol 
NvRegTxUnderflow 
NvRegTxLossCarrier 
NvRegTxExcessDef 
NvRegTxRetryErr 
NvRegRxFrameErr 
NvRegRxExtraByte 
NvRegRxLateCol 
NvRegRxRunt 
NvRegRxFrameTooLong 
NvRegRxOverflow 
NvRegRxFCSErr 
NvRegRxFrameAlignErr 
NvRegRxLenErr 
NvRegRxUnicast 
NvRegRxMulticast 
NvRegRxBroadcast 
NvRegTxDef 
NvRegTxFrame 
NvRegRxCnt 
NvRegTxPause 
NvRegRxPause 
NvRegRxDropFrame 
NvRegVlanControl 
NvRegMSIXMap0 
NvRegMSIXMap1 
NvRegMSIXIrqStatus 
NvRegPowerState2 
NvRegPatternCrcEx 
NvRegPatternMask0Ex 
NvRegPatternMask1Ex 
NvRegPatternMask2Ex 
NvRegPatternMask3Ex 

Definition at line 50 of file nic.h.

51 {
52  NvRegIrqStatus = 0x000,
53 #define NVREG_IRQSTAT_MIIEVENT 0x040
54 #define NVREG_IRQSTAT_MASK 0x83ff
55 
56  NvRegIrqMask = 0x004,
57 #define NVREG_IRQ_RX_ERROR 0x0001
58 #define NVREG_IRQ_RX 0x0002
59 #define NVREG_IRQ_RX_NOBUF 0x0004
60 #define NVREG_IRQ_TX_ERR 0x0008
61 #define NVREG_IRQ_TX_OK 0x0010
62 #define NVREG_IRQ_TIMER 0x0020
63 #define NVREG_IRQ_LINK 0x0040
64 #define NVREG_IRQ_RX_FORCED 0x0080
65 #define NVREG_IRQ_TX_FORCED 0x0100
66 #define NVREG_IRQ_RECOVER_ERROR 0x8200
67 #define NVREG_IRQMASK_THROUGHPUT 0x00df
68 #define NVREG_IRQMASK_CPU 0x0060
69 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
70 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF| \
71  NVREG_IRQ_RX_FORCED)
72 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
73 
74  NvRegUnknownSetupReg6 = 0x008,
75 #define NVREG_UNKSETUP6_VAL 3
76 
77  NvRegPollingInterval = 0x00c,
78 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535
79 #define NVREG_POLL_DEFAULT_CPU 13
80 
81  NvRegMSIMap0 = 0x020,
82  NvRegMSIMap1 = 0x024,
83 
84  NvRegMSIIrqMask = 0x030,
85 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
86 
87  NvRegMacReset = 0x34,
88 #define NVREG_MAC_RESET_ASSERT 0x0F3
89 
90  NvRegMisc1 = 0x080,
91 #define NVREG_MISC1_PAUSE_TX 0x01
92 #define NVREG_MISC1_HD 0x02
93 #define NVREG_MISC1_FORCE 0x3b0f3c
94 
96 #define NVREG_XMITCTL_START 0x01
97 #define NVREG_XMITCTL_MGMT_ST 0x40000000
98 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
99 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
100 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
101 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
102 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
103 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
104 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
105 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
106 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
107 #define NVREG_XMITCTL_DATA_START 0x00100000
108 #define NVREG_XMITCTL_DATA_READY 0x00010000
109 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
110 
111  NvRegTransmitterStatus = 0x088,
112 #define NVREG_XMITSTAT_BUSY 0x01
113 
114  NvRegPacketFilterFlags = 0x8c,
115 #define NVREG_PFF_PAUSE_RX 0x08
116 #define NVREG_PFF_ALWAYS 0x7F0000
117 #define NVREG_PFF_PROMISC 0x80
118 #define NVREG_PFF_MYADDR 0x20
119 #define NVREG_PFF_LOOPBACK 0x10
120 
121  NvRegOffloadConfig = 0x90,
122 #define NVREG_OFFLOAD_HOMEPHY 0x601
123 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
124 
125  NvRegReceiverControl = 0x094,
126 #define NVREG_RCVCTL_START 0x01
127 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
128 
129  NvRegReceiverStatus = 0x98,
130 #define NVREG_RCVSTAT_BUSY 0x01
131 
132  NvRegSlotTime = 0x9c,
133 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
134 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
135 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
136 #define NVREG_SLOTTIME_HALF 0x0000ff00
137 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
138 #define NVREG_SLOTTIME_MASK 0x000000ff
139 
140  NvRegTxDeferral = 0xA0,
141 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
142 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
143 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
144 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
145 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
146 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
147 
148  NvRegRxDeferral = 0xA4,
149 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
150 
151  NvRegMacAddrA = 0xA8,
152  NvRegMacAddrB = 0xAC,
153 
154  NvRegMulticastAddrA = 0xB0,
155  NvRegMulticastAddrB = 0xB4,
156 #define NVREG_MCASTADDRA_FORCE 0x01
157 
158  NvRegMulticastMaskA = 0xB8,
159 #define NVREG_MCASTMASKA_NONE 0xffffffff
160 
161  NvRegMulticastMaskB = 0xBC,
162 #define NVREG_MCASTMASKB_NONE 0xffff
163 
164  NvRegPhyInterface = 0xC0,
165 #define PHY_100 0x1
166 #define PHY_1000 0x2
167 #define PHY_HALF 0x100
168 #define PHY_RGMII 0x10000000
169 
170  NvRegBackOffControl = 0xC4,
171 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
172 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
173 #define NVREG_BKOFFCTRL_SELECT 24
174 #define NVREG_BKOFFCTRL_GEAR 12
175 
176  NvRegTxRingPhysAddr = 0x100,
177  NvRegRxRingPhysAddr = 0x104,
178 
179  NvRegRingSizes = 0x108,
180 #define NVREG_RINGSZ_TXSHIFT 0
181 #define NVREG_RINGSZ_RXSHIFT 16
182 
183  NvRegTransmitPoll = 0x10c,
184 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
185 
186  NvRegLinkSpeed = 0x110,
187 #define NVREG_LINKSPEED_FORCE 0x10000
188 #define NVREG_LINKSPEED_10 1000
189 #define NVREG_LINKSPEED_100 100
190 #define NVREG_LINKSPEED_1000 50
191 #define NVREG_LINKSPEED_MASK (0xFFF)
192 
193  NvRegUnknownSetupReg5 = 0x130,
194 #define NVREG_UNKSETUP5_BIT31 (1<<31)
195 
196  NvRegTxWatermark = 0x13c,
197 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
198 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
199 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
200 
201  NvRegTxRxControl = 0x144,
202 #define NVREG_TXRXCTL_KICK 0x0001
203 #define NVREG_TXRXCTL_BIT1 0x0002
204 #define NVREG_TXRXCTL_BIT2 0x0004
205 #define NVREG_TXRXCTL_IDLE 0x0008
206 #define NVREG_TXRXCTL_RESET 0x0010
207 #define NVREG_TXRXCTL_RXCHECK 0x0400
208 #define NVREG_TXRXCTL_DESC_1 0
209 #define NVREG_TXRXCTL_DESC_2 0x002100
210 #define NVREG_TXRXCTL_DESC_3 0xc02200
211 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
212 #define NVREG_TXRXCTL_VLANINS 0x00080
213 
214  NvRegTxRingPhysAddrHigh = 0x148,
215  NvRegRxRingPhysAddrHigh = 0x14C,
216 
217  NvRegTxPauseFrame = 0x170,
218 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
219 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
220 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
221 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
222 
223  NvRegTxPauseFrameLimit = 0x174,
224 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
225 
226  NvRegMIIStatus = 0x180,
227 #define NVREG_MIISTAT_ERROR 0x0001
228 #define NVREG_MIISTAT_LINKCHANGE 0x0008
229 #define NVREG_MIISTAT_MASK_RW 0x0007
230 #define NVREG_MIISTAT_MASK_ALL 0x000f
231 
232  NvRegMIIMask = 0x184,
233 #define NVREG_MII_LINKCHANGE 0x0008
234 
235  NvRegAdapterControl = 0x188,
236 #define NVREG_ADAPTCTL_START 0x02
237 #define NVREG_ADAPTCTL_LINKUP 0x04
238 #define NVREG_ADAPTCTL_PHYVALID 0x40000
239 #define NVREG_ADAPTCTL_RUNNING 0x100000
240 #define NVREG_ADAPTCTL_PHYSHIFT 24
241 
242  NvRegMIISpeed = 0x18c,
243 #define NVREG_MIISPEED_BIT8 (1<<8)
244 #define NVREG_MIIDELAY 5
245 
246  NvRegMIIControl = 0x190,
247 #define NVREG_MIICTL_INUSE 0x08000
248 #define NVREG_MIICTL_WRITE 0x00400
249 #define NVREG_MIICTL_ADDRSHIFT 5
250 
251  NvRegMIIData = 0x194,
252  NvRegTxUnicast = 0x1a0,
253  NvRegTxMulticast = 0x1a4,
254  NvRegTxBroadcast = 0x1a8,
255 
256  NvRegWakeUpFlags = 0x200,
257 #define NVREG_WAKEUPFLAGS_VAL 0x7770
258 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
259 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
260 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
261 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
262 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
263 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
264 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
265 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
266 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
267 #define NVREG_WAKEUPFLAGS_ENABLE_MAGPAT 0x1111
268 #define NVREG_WAKEUPFLAGS_ENABLE_WAKEUPPAT 0x2222
269 #define NVREG_WAKEUPFLAGS_ENABLE_LINKCHANGE 0x4444
270 
271  NvRegPatternCrc = 0x204,
272  NvRegPatternMask0 = 0x208,
273  NvRegPatternMask1 = 0x20C,
274  NvRegPatternMask2 = 0x210,
275  NvRegPatternMask3 = 0x214,
276 
277  NvRegMgmtUnitGetVersion = 0x204,
278 #define NVREG_MGMTUNITGETVERSION 0x01
279 
280  NvRegMgmtUnitVersion = 0x208,
281 #define NVREG_MGMTUNITVERSION 0x08
282 
283  NvRegPowerCap = 0x268,
284 #define NVREG_POWERCAP_D3SUPP (1<<30)
285 #define NVREG_POWERCAP_D2SUPP (1<<26)
286 #define NVREG_POWERCAP_D1SUPP (1<<25)
287 
288  NvRegPowerState = 0x26c,
289 #define NVREG_POWERSTATE_POWEREDUP 0x8000
290 #define NVREG_POWERSTATE_VALID 0x0100
291 #define NVREG_POWERSTATE_MASK 0x0003
292 #define NVREG_POWERSTATE_D0 0x0000
293 #define NVREG_POWERSTATE_D1 0x0001
294 #define NVREG_POWERSTATE_D2 0x0002
295 #define NVREG_POWERSTATE_D3 0x0003
296 
297  NvRegMgmtUnitControl = 0x278,
298 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
299 
300  NvRegTxCnt = 0x280,
301  NvRegTxZeroReXmt = 0x284,
302  NvRegTxOneReXmt = 0x288,
303  NvRegTxManyReXmt = 0x28c,
304  NvRegTxLateCol = 0x290,
305  NvRegTxUnderflow = 0x294,
306  NvRegTxLossCarrier = 0x298,
307  NvRegTxExcessDef = 0x29c,
308  NvRegTxRetryErr = 0x2a0,
309  NvRegRxFrameErr = 0x2a4,
310  NvRegRxExtraByte = 0x2a8,
311  NvRegRxLateCol = 0x2ac,
312  NvRegRxRunt = 0x2b0,
313  NvRegRxFrameTooLong = 0x2b4,
314  NvRegRxOverflow = 0x2b8,
315  NvRegRxFCSErr = 0x2bc,
316  NvRegRxFrameAlignErr = 0x2c0,
317  NvRegRxLenErr = 0x2c4,
318  NvRegRxUnicast = 0x2c8,
319  NvRegRxMulticast = 0x2cc,
320  NvRegRxBroadcast = 0x2d0,
321  NvRegTxDef = 0x2d4,
322  NvRegTxFrame = 0x2d8,
323  NvRegRxCnt = 0x2dc,
324  NvRegTxPause = 0x2e0,
325  NvRegRxPause = 0x2e4,
326  NvRegRxDropFrame = 0x2e8,
327 
328  NvRegVlanControl = 0x300,
329 #define NVREG_VLANCONTROL_ENABLE 0x2000
330 
331  NvRegMSIXMap0 = 0x3e0,
332  NvRegMSIXMap1 = 0x3e4,
333  NvRegMSIXIrqStatus = 0x3f0,
334 
335  NvRegPowerState2 = 0x600,
336 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
337 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
338 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
339 #define NVREG_POWERSTATE2_GATE_CLOCK_1 0x0100
340 #define NVREG_POWERSTATE2_GATE_CLOCK_2 0x0200
341 #define NVREG_POWERSTATE2_GATE_CLOCK_3 0x0400
342 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
343 #define NVREG_POWERSTATE2_WAKEUPPAT_5 (1<<16)
344 #define NVREG_POWERSTATE2_WAKEUPPAT_6 (1<<17)
345 #define NVREG_POWERSTATE2_WAKEUPPAT_7 (1<<18)
346 
347  NvRegPatternCrcEx = 0x604,
348  NvRegPatternMask0Ex = 0x608,
349  NvRegPatternMask1Ex = 0x60C,
350  NvRegPatternMask2Ex = 0x610,
351  NvRegPatternMask3Ex = 0x614
enum _NVNET_REGISTER NVNET_REGISTER
Definition: nic.h:90