ReactOS  0.4.12-dev-409-g9f418243
usbohci.c
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1 /*
2  * PROJECT: ReactOS USB OHCI Miniport Driver
3  * LICENSE: GPL-2.0+ (https://spdx.org/licenses/GPL-2.0+)
4  * PURPOSE: USBOHCI main driver functions
5  * COPYRIGHT: Copyright 2017-2018 Vadim Galyant <vgal@rambler.ru>
6  */
7 
8 #include "usbohci.h"
9 
10 #define NDEBUG
11 #include <debug.h>
12 
13 #define NDEBUG_OHCI_TRACE
14 #include "dbg_ohci.h"
15 
16 USBPORT_REGISTRATION_PACKET RegPacket;
17 
18 static const UCHAR Index[8] =
19 {
20  ENDPOINT_INTERRUPT_1ms - 1,
21  ENDPOINT_INTERRUPT_2ms - 1,
22  ENDPOINT_INTERRUPT_4ms - 1,
23  ENDPOINT_INTERRUPT_8ms - 1,
24  ENDPOINT_INTERRUPT_16ms - 1,
25  ENDPOINT_INTERRUPT_32ms - 1,
26  ENDPOINT_INTERRUPT_32ms - 1,
27  ENDPOINT_INTERRUPT_32ms - 1
28 };
29 
30 static const UCHAR Balance[OHCI_NUMBER_OF_INTERRUPTS] =
31 {
32  0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30,
33  1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23, 15, 31
34 };
35 
36 VOID
37 NTAPI
38 OHCI_DumpHcdED(POHCI_HCD_ED ED)
39 {
40  DPRINT("ED - %p\n", ED);
41  DPRINT("EndpointControl - %X\n", ED->HwED.EndpointControl.AsULONG);
42  DPRINT("TailPointer - %08X\n", ED->HwED.TailPointer);
43  DPRINT("HeadPointer - %08X\n", ED->HwED.HeadPointer);
44  DPRINT("NextED - %08X\n", ED->HwED.NextED);
45 }
46 
47 VOID
48 NTAPI
49 OHCI_DumpHcdTD(POHCI_HCD_TD TD)
50 {
51  DPRINT("TD - %p\n", TD);
52  DPRINT("gTD.Control - %08X\n", TD->HwTD.gTD.Control.AsULONG);
53 if (TD->HwTD.gTD.CurrentBuffer)
54  DPRINT("gTD.CurrentBuffer - %08X\n", TD->HwTD.gTD.CurrentBuffer);
55 if (TD->HwTD.gTD.NextTD)
56  DPRINT("gTD.NextTD - %08X\n", TD->HwTD.gTD.NextTD);
57 if (TD->HwTD.gTD.BufferEnd)
58  DPRINT("gTD.BufferEnd - %08X\n", TD->HwTD.gTD.BufferEnd);
59 
60 if (TD->HwTD.SetupPacket.bmRequestType.B)
61  DPRINT("bmRequestType - %02X\n", TD->HwTD.SetupPacket.bmRequestType.B);
62 if (TD->HwTD.SetupPacket.bRequest)
63  DPRINT("bRequest - %02X\n", TD->HwTD.SetupPacket.bRequest);
64 if (TD->HwTD.SetupPacket.wValue.W)
65  DPRINT("wValue - %04X\n", TD->HwTD.SetupPacket.wValue.W);
66 if (TD->HwTD.SetupPacket.wIndex.W)
67  DPRINT("wIndex - %04X\n", TD->HwTD.SetupPacket.wIndex.W);
68 if (TD->HwTD.SetupPacket.wLength)
69  DPRINT("wLength - %04X\n", TD->HwTD.SetupPacket.wLength);
70 
71  DPRINT("PhysicalAddress - %p\n", TD->PhysicalAddress);
72  DPRINT("Flags - %X\n", TD->Flags);
73  DPRINT("OhciTransfer - %08X\n", TD->OhciTransfer);
74  DPRINT("NextHcdTD - %08X\n", TD->NextHcdTD);
75 if (TD->TransferLen)
76  DPRINT("TransferLen - %X\n", TD->TransferLen);
77 }
78 
79 VOID
80 NTAPI
81 OHCI_EnableList(IN POHCI_EXTENSION OhciExtension,
82  IN POHCI_ENDPOINT OhciEndpoint)
83 {
84  POHCI_OPERATIONAL_REGISTERS OperationalRegs;
85  PULONG CommandStatusReg;
86  ULONG TransferType;
87  OHCI_REG_COMMAND_STATUS CommandStatus;
88 
89  DPRINT_OHCI("OHCI_EnableList: ... \n");
90 
91  OperationalRegs = OhciExtension->OperationalRegs;
92  CommandStatusReg = (PULONG)&OperationalRegs->HcCommandStatus;
93 
94  CommandStatus.AsULONG = 0;
95 
96  if (READ_REGISTER_ULONG((PULONG)&OperationalRegs->HcControlHeadED))
97  CommandStatus.ControlListFilled = 1;
98 
99  if (READ_REGISTER_ULONG((PULONG)&OperationalRegs->HcBulkHeadED))
100  CommandStatus.BulkListFilled = 1;
101 
102  TransferType = OhciEndpoint->EndpointProperties.TransferType;
103 
104  if (TransferType == USBPORT_TRANSFER_TYPE_BULK)
105  CommandStatus.BulkListFilled = 1;
106  else if (TransferType == USBPORT_TRANSFER_TYPE_CONTROL)
107  CommandStatus.ControlListFilled = 1;
108 
109  WRITE_REGISTER_ULONG(CommandStatusReg, CommandStatus.AsULONG);
110 }
111 
112 VOID
113 NTAPI
114 OHCI_InsertEndpointInSchedule(IN POHCI_ENDPOINT OhciEndpoint)
115 {
116  POHCI_STATIC_ED HeadED;
117  POHCI_HCD_ED ED;
118  POHCI_HCD_ED PrevED;
119  PLIST_ENTRY HeadLink;
120 
121  DPRINT_OHCI("OHCI_InsertEndpointInSchedule: OhciEndpoint - %p\n",
122  OhciEndpoint);
123 
124  ED = OhciEndpoint->HcdED;
125 
126  HeadED = OhciEndpoint->HeadED;
127  HeadLink = &HeadED->Link;
128 
129  if (IsListEmpty(HeadLink))
130  {
131  InsertHeadList(HeadLink, &ED->HcdEDLink);
132 
133  if (HeadED->Type == OHCI_STATIC_ED_TYPE_CONTROL ||
134  HeadED->Type == OHCI_STATIC_ED_TYPE_BULK)
135  {
136  ED->HwED.NextED = READ_REGISTER_ULONG(HeadED->pNextED);
137  WRITE_REGISTER_ULONG(HeadED->pNextED, ED->PhysicalAddress);
138  }
139  else if (HeadED->Type == OHCI_STATIC_ED_TYPE_INTERRUPT)
140  {
141  ED->HwED.NextED = *HeadED->pNextED;
142  *HeadED->pNextED = ED->PhysicalAddress;
143  }
144  else
145  {
146  DPRINT1("OHCI_InsertEndpointInSchedule: Unknown HeadED->Type - %x\n",
147  HeadED->Type);
148  DbgBreakPoint();
149  }
150  }
151  else
152  {
153  PrevED = CONTAINING_RECORD(HeadLink->Blink,
154  OHCI_HCD_ED,
155  HcdEDLink);
156 
157  InsertTailList(HeadLink, &ED->HcdEDLink);
158 
159  ED->HwED.NextED = 0;
160  PrevED->HwED.NextED = ED->PhysicalAddress;
161  }
162 }
163 
164 POHCI_HCD_ED
165 NTAPI
166 OHCI_InitializeED(IN POHCI_ENDPOINT OhciEndpoint,
167  IN POHCI_HCD_ED ED,
168  IN POHCI_HCD_TD FirstTD,
169  IN ULONG_PTR EdPA)
170 {
171  OHCI_ENDPOINT_CONTROL EndpointControl;
172  PUSBPORT_ENDPOINT_PROPERTIES EndpointProperties;
173 
174  DPRINT_OHCI("OHCI_InitializeED: OhciEndpoint - %p, ED - %p, FirstTD - %p, EdPA - %p\n",
175  OhciEndpoint,
176  ED,
177  FirstTD,
178  EdPA);
179 
180  RtlZeroMemory(ED, sizeof(OHCI_HCD_ED));
181 
182  ED->PhysicalAddress = EdPA;
183 
184  EndpointProperties = &OhciEndpoint->EndpointProperties;
185 
186  EndpointControl = ED->HwED.EndpointControl;
187 
188  EndpointControl.FunctionAddress = EndpointProperties->DeviceAddress;
189  EndpointControl.EndpointNumber = EndpointProperties->EndpointAddress;
190  EndpointControl.MaximumPacketSize = EndpointProperties->TotalMaxPacketSize;
191 
192  if (EndpointProperties->TransferType == USBPORT_TRANSFER_TYPE_CONTROL)
193  {
194  EndpointControl.Direction = OHCI_ED_DATA_FLOW_DIRECTION_FROM_TD;
195  }
196  else if (EndpointProperties->Direction)
197  {
198  EndpointControl.Direction = OHCI_ED_DATA_FLOW_DIRECTION_OUT;
199  }
200  else
201  {
202  EndpointControl.Direction = OHCI_ED_DATA_FLOW_DIRECTION_IN;
203  }
204 
205  if (EndpointProperties->DeviceSpeed == UsbLowSpeed)
206  EndpointControl.Speed = OHCI_ENDPOINT_LOW_SPEED;
207 
208  if (EndpointProperties->TransferType == USBPORT_TRANSFER_TYPE_ISOCHRONOUS)
209  EndpointControl.Format = OHCI_ENDPOINT_ISOCHRONOUS_FORMAT;
210  else
211  EndpointControl.sKip = 1;
212 
213  ED->HwED.EndpointControl = EndpointControl;
214 
215  ED->HwED.TailPointer = FirstTD->PhysicalAddress;
216  ED->HwED.HeadPointer = FirstTD->PhysicalAddress;
217 
218  FirstTD->Flags |= OHCI_HCD_TD_FLAG_ALLOCATED;
219 
220  OhciEndpoint->HcdTailP = FirstTD;
221  OhciEndpoint->HcdHeadP = FirstTD;
222 
223  return ED;
224 }
225 
226 VOID
227 NTAPI
228 OHCI_InitializeTDs(IN POHCI_ENDPOINT OhciEndpoint,
229  IN PUSBPORT_ENDPOINT_PROPERTIES EndpointProperties)
230 {
231  POHCI_HCD_TD TdVA;
232  ULONG TdPA;
233  ULONG TdCount;
234  ULONG ix;
235 
236  ASSERT(EndpointProperties->BufferLength > sizeof(OHCI_HCD_ED));
237 
238  TdCount = (EndpointProperties->BufferLength - sizeof(OHCI_HCD_ED)) /
239  sizeof(OHCI_HCD_TD);
240 
241  OhciEndpoint->MaxTransferDescriptors = TdCount;
242 
243  DPRINT_OHCI("OHCI_InitializeTDs: TdCount - %x\n", TdCount);
244 
245  ASSERT(TdCount > 0);
246 
247  TdVA = OhciEndpoint->FirstTD;
248 
249  TdPA = EndpointProperties->BufferPA + sizeof(OHCI_HCD_ED);
250 
251  for (ix = 0; ix < TdCount; ix++)
252  {
253  DPRINT_OHCI("OHCI_InitializeTDs: TdVA - %p, TdPA - %08X\n", TdVA, TdPA);
254 
255  RtlZeroMemory(TdVA, sizeof(OHCI_HCD_TD));
256 
257  TdVA->PhysicalAddress = TdPA;
258  TdVA->Flags = 0;
259  TdVA->OhciTransfer = 0;
260 
261  TdVA++;
262  TdPA += sizeof(OHCI_HCD_TD);
263  }
264 }
265 
266 MPSTATUS
267 NTAPI
268 OHCI_OpenControlEndpoint(IN POHCI_EXTENSION OhciExtension,
269  IN PUSBPORT_ENDPOINT_PROPERTIES EndpointProperties,
270  IN POHCI_ENDPOINT OhciEndpoint)
271 {
272  POHCI_HCD_ED ED;
273 
274  DPRINT_OHCI("OHCI_OpenControlEndpoint: ... \n");
275 
276  ED = (POHCI_HCD_ED)EndpointProperties->BufferVA;
277 
278  OhciEndpoint->FirstTD = (POHCI_HCD_TD)((ULONG_PTR)ED + sizeof(OHCI_HCD_ED));
279  OhciEndpoint->HeadED = &OhciExtension->ControlStaticED;
280 
281  OHCI_InitializeTDs(OhciEndpoint, EndpointProperties);
282 
283  OhciEndpoint->HcdED = OHCI_InitializeED(OhciEndpoint,
284  ED,
285  OhciEndpoint->FirstTD,
286  EndpointProperties->BufferPA);
287 
288  OhciEndpoint->HcdED->Flags = OHCI_HCD_ED_FLAG_CONTROL |
289  OHCI_HCD_ED_FLAG_RESET_ON_HALT;
290 
291  OHCI_InsertEndpointInSchedule(OhciEndpoint);
292 
293  return MP_STATUS_SUCCESS;
294 }
295 
296 MPSTATUS
297 NTAPI
298 OHCI_OpenBulkEndpoint(IN POHCI_EXTENSION OhciExtension,
299  IN PUSBPORT_ENDPOINT_PROPERTIES EndpointProperties,
300  IN POHCI_ENDPOINT OhciEndpoint)
301 {
302  POHCI_HCD_ED ED;
303 
304  DPRINT_OHCI("OHCI_OpenBulkEndpoint: ... \n");
305 
306  ED = (POHCI_HCD_ED)EndpointProperties->BufferVA;
307 
308  OhciEndpoint->FirstTD = (POHCI_HCD_TD)((ULONG_PTR)ED + sizeof(OHCI_HCD_ED));
309  OhciEndpoint->HeadED = &OhciExtension->BulkStaticED;
310 
311  OHCI_InitializeTDs(OhciEndpoint, EndpointProperties);
312 
313  OhciEndpoint->HcdED = OHCI_InitializeED(OhciEndpoint,
314  ED,
315  OhciEndpoint->FirstTD,
316  EndpointProperties->BufferPA);
317 
318  OHCI_InsertEndpointInSchedule(OhciEndpoint);
319 
320  return MP_STATUS_SUCCESS;
321 }
322 
323 MPSTATUS
324 NTAPI
325 OHCI_OpenInterruptEndpoint(IN POHCI_EXTENSION OhciExtension,
326  IN PUSBPORT_ENDPOINT_PROPERTIES EndpointProperties,
327  IN POHCI_ENDPOINT OhciEndpoint)
328 {
329  UCHAR Period;
330  ULONG PeriodIdx = 0;
331  POHCI_HCD_ED ED;
332  ULONG ScheduleOffset;
333 
334  DPRINT_OHCI("OHCI_OpenInterruptEndpoint: ... \n");
335 
336  ED = (POHCI_HCD_ED)EndpointProperties->BufferVA;
337 
338  OhciEndpoint->FirstTD = (POHCI_HCD_TD)((ULONG_PTR)ED + sizeof(OHCI_HCD_ED));
339 
340  Period = EndpointProperties->Period;
341 
342  ASSERT(Period != 0);
343 
344  while (!(Period & 1))
345  {
346  PeriodIdx++;
347  Period >>= 1;
348  }
349 
350  ASSERT(PeriodIdx < ARRAYSIZE(Index));
351 
352  ScheduleOffset = EndpointProperties->ScheduleOffset;
353  DPRINT_OHCI("OHCI_OpenInterruptEndpoint: InitTD. Index[PeriodIdx] - %x, ScheduleOffset - %x\n",
354  Index[PeriodIdx],
355  ScheduleOffset);
356 
357  OhciEndpoint->HeadED = &OhciExtension->IntStaticED[Index[PeriodIdx] +
358  ScheduleOffset];
359 
360  //OhciEndpoint->HeadED->UsbBandwidth += EndpointProperties->UsbBandwidth;
361 
362  OHCI_InitializeTDs(OhciEndpoint, EndpointProperties);
363 
364  OhciEndpoint->HcdED = OHCI_InitializeED(OhciEndpoint,
365  ED,
366  OhciEndpoint->FirstTD,
367  EndpointProperties->BufferPA);
368 
369  OHCI_InsertEndpointInSchedule(OhciEndpoint);
370 
371  return MP_STATUS_SUCCESS;
372 }
373 
374 MPSTATUS
375 NTAPI
376 OHCI_OpenIsoEndpoint(IN POHCI_EXTENSION OhciExtension,
377  IN PUSBPORT_ENDPOINT_PROPERTIES EndpointProperties,
378  IN POHCI_ENDPOINT OhciEndpoint)
379 {
380  DPRINT1("OHCI_OpenIsoEndpoint: UNIMPLEMENTED. FIXME\n");
381  return MP_STATUS_NOT_SUPPORTED;
382 }
383 
384 MPSTATUS
385 NTAPI
386 OHCI_OpenEndpoint(IN PVOID ohciExtension,
387  IN PUSBPORT_ENDPOINT_PROPERTIES EndpointProperties,
388  IN PVOID ohciEndpoint)
389 {
390  POHCI_EXTENSION OhciExtension = ohciExtension;
391  POHCI_ENDPOINT OhciEndpoint = ohciEndpoint;
392  ULONG TransferType;
393  MPSTATUS MPStatus;
394 
395  DPRINT_OHCI("OHCI_OpenEndpoint: ... \n");
396 
397  RtlCopyMemory(&OhciEndpoint->EndpointProperties,
398  EndpointProperties,
399  sizeof(OhciEndpoint->EndpointProperties));
400 
401  InitializeListHead(&OhciEndpoint->TDList);
402 
403  TransferType = EndpointProperties->TransferType;
404 
405  switch (TransferType)
406  {
407  case USBPORT_TRANSFER_TYPE_ISOCHRONOUS:
408  MPStatus = OHCI_OpenIsoEndpoint(OhciExtension,
409  EndpointProperties,
410  OhciEndpoint);
411  break;
412 
413  case USBPORT_TRANSFER_TYPE_CONTROL:
414  MPStatus = OHCI_OpenControlEndpoint(OhciExtension,
415  EndpointProperties,
416  OhciEndpoint);
417  break;
418 
419  case USBPORT_TRANSFER_TYPE_BULK:
420  MPStatus = OHCI_OpenBulkEndpoint(OhciExtension,
421  EndpointProperties,
422  OhciEndpoint);
423  break;
424 
425  case USBPORT_TRANSFER_TYPE_INTERRUPT:
426  MPStatus = OHCI_OpenInterruptEndpoint(OhciExtension,
427  EndpointProperties,
428  OhciEndpoint);
429  break;
430 
431  default:
432  MPStatus = MP_STATUS_NOT_SUPPORTED;
433  break;
434  }
435 
436  return MPStatus;
437 }
438 
439 MPSTATUS
440 NTAPI
441 OHCI_ReopenEndpoint(IN PVOID ohciExtension,
442  IN PUSBPORT_ENDPOINT_PROPERTIES EndpointProperties,
443  IN PVOID ohciEndpoint)
444 {
445  POHCI_ENDPOINT OhciEndpoint = ohciEndpoint;
446  POHCI_HCD_ED ED;
447 
448  DPRINT_OHCI("OHCI_ReopenEndpoint: ... \n");
449 
450  ED = OhciEndpoint->HcdED;
451 
452  RtlCopyMemory(&OhciEndpoint->EndpointProperties,
453  EndpointProperties,
454  sizeof(OhciEndpoint->EndpointProperties));
455 
456  ED->HwED.EndpointControl.FunctionAddress =
457  OhciEndpoint->EndpointProperties.DeviceAddress;
458 
459  ED->HwED.EndpointControl.MaximumPacketSize =
460  OhciEndpoint->EndpointProperties.TotalMaxPacketSize;
461 
462  return MP_STATUS_SUCCESS;
463 }
464 
465 VOID
466 NTAPI
467 OHCI_QueryEndpointRequirements(IN PVOID ohciExtension,
468  IN PUSBPORT_ENDPOINT_PROPERTIES EndpointProperties,
469  IN PUSBPORT_ENDPOINT_REQUIREMENTS EndpointRequirements)
470 {
471  ULONG TransferType;
472 
473  DPRINT_OHCI("OHCI_QueryEndpointRequirements: ... \n");
474 
475  TransferType = EndpointProperties->TransferType;
476 
477  switch (TransferType)
478  {
479  case USBPORT_TRANSFER_TYPE_ISOCHRONOUS:
480  DPRINT_OHCI("OHCI_QueryEndpointRequirements: IsoTransfer\n");
481  EndpointRequirements->MaxTransferSize = OHCI_MAX_ISO_TRANSFER_SIZE;
482  EndpointRequirements->HeaderBufferSize =
483  sizeof(OHCI_HCD_ED) + OHCI_MAX_ISO_TD_COUNT * sizeof(OHCI_HCD_TD);
484  break;
485 
486  case USBPORT_TRANSFER_TYPE_CONTROL:
487  DPRINT_OHCI("OHCI_QueryEndpointRequirements: ControlTransfer\n");
488  EndpointRequirements->MaxTransferSize = OHCI_MAX_CONTROL_TRANSFER_SIZE;
489  EndpointRequirements->HeaderBufferSize =
490  sizeof(OHCI_HCD_ED) + OHCI_MAX_CONTROL_TD_COUNT * sizeof(OHCI_HCD_TD);
491  break;
492 
493  case USBPORT_TRANSFER_TYPE_BULK:
494  DPRINT_OHCI("OHCI_QueryEndpointRequirements: BulkTransfer\n");
495  EndpointRequirements->MaxTransferSize = OHCI_MAX_BULK_TRANSFER_SIZE;
496  EndpointRequirements->HeaderBufferSize =
497  sizeof(OHCI_HCD_ED) + OHCI_MAX_BULK_TD_COUNT * sizeof(OHCI_HCD_TD);
498  break;
499 
500  case USBPORT_TRANSFER_TYPE_INTERRUPT:
501  DPRINT_OHCI("OHCI_QueryEndpointRequirements: InterruptTransfer\n");
502  EndpointRequirements->MaxTransferSize = OHCI_MAX_INTERRUPT_TRANSFER_SIZE;
503  EndpointRequirements->HeaderBufferSize =
504  sizeof(OHCI_HCD_ED) + OHCI_MAX_INTERRUPT_TD_COUNT * sizeof(OHCI_HCD_TD);
505  break;
506 
507  default:
508  DPRINT1("OHCI_QueryEndpointRequirements: Unknown TransferType - %x\n",
509  TransferType);
510  DbgBreakPoint();
511  break;
512  }
513 }
514 
515 VOID
516 NTAPI
517 OHCI_CloseEndpoint(IN PVOID ohciExtension,
518  IN PVOID ohciEndpoint,
519  IN BOOLEAN IsDoDisablePeriodic)
520 {
521 #if DBG
522  DPRINT1("OHCI_CloseEndpoint: Not supported\n");
523 #endif
524  return;
525 }
526 
527 MPSTATUS
528 NTAPI
529 OHCI_TakeControlHC(IN POHCI_EXTENSION OhciExtension,
530  IN PUSBPORT_RESOURCES Resources)
531 {
532  POHCI_OPERATIONAL_REGISTERS OperationalRegs;
533  PULONG ControlReg;
534  PULONG InterruptEnableReg;
535  PULONG InterruptDisableReg;
536  PULONG CommandStatusReg;
537  PULONG InterruptStatusReg;
538  OHCI_REG_CONTROL Control;
539  OHCI_REG_INTERRUPT_ENABLE_DISABLE IntEnable;
540  OHCI_REG_INTERRUPT_ENABLE_DISABLE IntDisable;
541  OHCI_REG_COMMAND_STATUS CommandStatus;
542  OHCI_REG_INTERRUPT_STATUS IntStatus;
543  LARGE_INTEGER EndTime;
544  LARGE_INTEGER SystemTime;
545 
546  DPRINT("OHCI_TakeControlHC: ...\n");
547 
548  OperationalRegs = OhciExtension->OperationalRegs;
549 
550  ControlReg = (PULONG)&OperationalRegs->HcControl;
551  InterruptEnableReg = (PULONG)&OperationalRegs->HcInterruptEnable;
552  InterruptDisableReg = (PULONG)&OperationalRegs->HcInterruptDisable;
553  CommandStatusReg = (PULONG)&OperationalRegs->HcCommandStatus;
554  InterruptStatusReg = (PULONG)&OperationalRegs->HcInterruptStatus;
555 
556  /* 5.1.1.3 Take Control of Host Controller */
557  Control.AsULONG = READ_REGISTER_ULONG(ControlReg);
558 
559  if (Control.InterruptRouting == 0)
560  return MP_STATUS_SUCCESS;
561 
562  DPRINT1("OHCI_TakeControlHC: detected Legacy BIOS\n");
563 
564  IntEnable.AsULONG = READ_REGISTER_ULONG(InterruptEnableReg);
565 
566  DPRINT("OHCI_TakeControlHC: Control - %lX, IntEnable - %lX\n",
567  Control.AsULONG,
568  IntEnable.AsULONG);
569 
570  if (Control.HostControllerFunctionalState == OHCI_HC_STATE_RESET &&
571  IntEnable.AsULONG == 0)
572  {
573  Control.AsULONG = 0;
574  WRITE_REGISTER_ULONG(ControlReg, Control.AsULONG);
575  return MP_STATUS_SUCCESS;
576  }
577 
578  /* Enable interrupt generations */
579  IntEnable.AsULONG = 0;
580  IntEnable.MasterInterruptEnable = 1;
581 
582  WRITE_REGISTER_ULONG(InterruptEnableReg, IntEnable.AsULONG);
583 
584  /* Request a change of control of the HC */
585  CommandStatus.AsULONG = 0;
586  CommandStatus.OwnershipChangeRequest = 1;
587 
588  WRITE_REGISTER_ULONG(CommandStatusReg, CommandStatus.AsULONG);
589 
590  /* Disable interrupt generation due to Root Hub Status Change */
591  IntDisable.AsULONG = 0;
592  IntDisable.RootHubStatusChange = 1;
593 
594  WRITE_REGISTER_ULONG(InterruptDisableReg, IntDisable.AsULONG);
595 
596  /* Monitoring the InterruptRouting bit
597  to determine when the ownership change has taken effect. */
598 
599  KeQuerySystemTime(&EndTime);
600  EndTime.QuadPart += 500 * 10000; // 0.5 sec;
601 
602  do
603  {
604  Control.AsULONG = READ_REGISTER_ULONG(ControlReg);
605 
606  if (Control.InterruptRouting == 0)
607  {
608  /* Clear all bits in register */
609  IntStatus.AsULONG = 0xFFFFFFFF;
610  WRITE_REGISTER_ULONG(InterruptStatusReg, IntStatus.AsULONG);
611 
612  /* Disable interrupt generations */
613  IntDisable.AsULONG = 0;
614  IntDisable.MasterInterruptEnable = 1;
615 
616  WRITE_REGISTER_ULONG(InterruptDisableReg, IntDisable.AsULONG);
617 
618  return MP_STATUS_SUCCESS;
619  }
620 
621  KeQuerySystemTime(&SystemTime);
622  }
623  while (SystemTime.QuadPart < EndTime.QuadPart);
624 
625  return MP_STATUS_HW_ERROR;
626 }
627 
628 MPSTATUS
629 NTAPI
630 OHCI_StartController(IN PVOID ohciExtension,
631  IN PUSBPORT_RESOURCES Resources)
632 {
633  POHCI_EXTENSION OhciExtension = ohciExtension;
634  POHCI_OPERATIONAL_REGISTERS OperationalRegs;
635  PULONG CommandStatusReg;
636  PULONG FmIntervalReg;
637  PULONG ControlReg;
638  PULONG InterruptEnableReg;
639  PULONG RhStatusReg;
640  OHCI_REG_COMMAND_STATUS CommandStatus;
641  OHCI_REG_INTERRUPT_ENABLE_DISABLE Interrupts;
642  OHCI_REG_RH_STATUS RhStatus;
643  OHCI_REG_FRAME_INTERVAL FrameInterval;
644  ULONG MaxFrameIntervalAdjusting;
645  OHCI_REG_CONTROL Control;
646  UCHAR HeadIndex;
647  POHCI_ENDPOINT_DESCRIPTOR IntED;
648  ULONG_PTR IntEdPA;
649  POHCI_HCCA OhciHCCA;
650  LARGE_INTEGER SystemTime;
651  LARGE_INTEGER EndTime;
652  ULONG ix;
653  ULONG jx;
654  MPSTATUS MPStatus = MP_STATUS_SUCCESS;
655 
656  DPRINT_OHCI("OHCI_StartController: ohciExtension - %p, Resources - %p\n",
657  ohciExtension,
658  Resources);
659 
660  /* HC on-chip operational registers */
661  OperationalRegs = (POHCI_OPERATIONAL_REGISTERS)Resources->ResourceBase;
662  OhciExtension->OperationalRegs = OperationalRegs;
663 
664  CommandStatusReg = (PULONG)&OperationalRegs->HcCommandStatus;
665  FmIntervalReg = (PULONG)&OperationalRegs->HcFmInterval;
666  ControlReg = (PULONG)&OperationalRegs->HcControl;
667  InterruptEnableReg = (PULONG)&OperationalRegs->HcInterruptEnable;
668  RhStatusReg = (PULONG)&OperationalRegs->HcRhStatus;
669 
670  /* 5.1.1 Initialization */
671 
672  MPStatus = OHCI_TakeControlHC(OhciExtension, Resources);
673 
674  if (MPStatus != MP_STATUS_SUCCESS)
675  {
676  DPRINT1("OHCI_StartController: OHCI_TakeControlHC return MPStatus - %x\n",
677  MPStatus);
678 
679  return MPStatus;
680  }
681 
682  OhciExtension->HcResourcesVA = (POHCI_HC_RESOURCES)Resources->StartVA;
683  OhciExtension->HcResourcesPA = Resources->StartPA;
684 
685  DPRINT_OHCI("OHCI_StartController: HcResourcesVA - %p, HcResourcesPA - %lx\n",
686  OhciExtension->HcResourcesVA,
687  OhciExtension->HcResourcesPA);
688 
689  /* 5.2.7.2 Interrupt */
690 
691  /* Build structure of interrupt static EDs */
692  for (ix = 0; ix < INTERRUPT_ENDPOINTs; ix++)
693  {
694  IntED = &OhciExtension->HcResourcesVA->InterrruptHeadED[ix];
695  IntEdPA = OhciExtension->HcResourcesPA + FIELD_OFFSET(OHCI_HC_RESOURCES, InterrruptHeadED[ix]);
696 
697  if (ix == (ENDPOINT_INTERRUPT_1ms - 1))
698  {
699  HeadIndex = ED_EOF;
700  IntED->NextED = 0;
701  }
702  else
703  {
704  HeadIndex = ((ix - 1) / 2);
705 
706  ASSERT(HeadIndex >= (ENDPOINT_INTERRUPT_1ms - 1) &&
707  HeadIndex < (INTERRUPT_ENDPOINTs - ENDPOINT_INTERRUPT_32ms));
708 
709  IntED->NextED = OhciExtension->IntStaticED[HeadIndex].PhysicalAddress;
710  }
711 
712  IntED->EndpointControl.sKip = 1;
713 
714  IntED->TailPointer = 0;
715  IntED->HeadPointer = 0;
716 
717  OhciExtension->IntStaticED[ix].HwED = IntED;
718  OhciExtension->IntStaticED[ix].PhysicalAddress = IntEdPA;
719  OhciExtension->IntStaticED[ix].HeadIndex = HeadIndex;
720  OhciExtension->IntStaticED[ix].pNextED = &IntED->NextED;
721  OhciExtension->IntStaticED[ix].Type = OHCI_STATIC_ED_TYPE_INTERRUPT;
722 
723  InitializeListHead(&OhciExtension->IntStaticED[ix].Link);
724  }
725 
726  OhciHCCA = &OhciExtension->HcResourcesVA->HcHCCA;
727  DPRINT_OHCI("OHCI_InitializeSchedule: OhciHCCA - %p\n", OhciHCCA);
728 
729  /* Set head pointers which start from HCCA */
730  for (ix = 0, jx = (INTERRUPT_ENDPOINTs - ENDPOINT_INTERRUPT_32ms);
731  ix < OHCI_NUMBER_OF_INTERRUPTS;
732  ix++, jx++)
733  {
734  OhciHCCA->InterrruptTable[Balance[ix]] =
735  OhciExtension->IntStaticED[jx].PhysicalAddress;
736 
737  OhciExtension->IntStaticED[jx].pNextED =
738  (PULONG)&OhciHCCA->InterrruptTable[Balance[ix]];
739 
740  OhciExtension->IntStaticED[jx].HccaIndex = Balance[ix];
741  }
742 
743  DPRINT_OHCI("OHCI_InitializeSchedule: ix - %x\n", ix);
744 
745  /* Init static Control and Bulk EDs head pointers which start from HCCA */
746  InitializeListHead(&OhciExtension->ControlStaticED.Link);
747 
748  OhciExtension->ControlStaticED.HeadIndex = ED_EOF;
749  OhciExtension->ControlStaticED.Type = OHCI_STATIC_ED_TYPE_CONTROL;
750  OhciExtension->ControlStaticED.pNextED = &OperationalRegs->HcControlHeadED;
751 
752  InitializeListHead(&OhciExtension->BulkStaticED.Link);
753 
754  OhciExtension->BulkStaticED.HeadIndex = ED_EOF;
755  OhciExtension->BulkStaticED.Type = OHCI_STATIC_ED_TYPE_BULK;
756  OhciExtension->BulkStaticED.pNextED = &OperationalRegs->HcBulkHeadED;
757 
758  /* 6.3.1 Frame Timing */
759  FrameInterval.AsULONG = READ_REGISTER_ULONG(FmIntervalReg);
760 
761  MaxFrameIntervalAdjusting = OHCI_DEFAULT_FRAME_INTERVAL / 10; // 10%
762 
763  if ((FrameInterval.FrameInterval) < (OHCI_DEFAULT_FRAME_INTERVAL - MaxFrameIntervalAdjusting) ||
764  (FrameInterval.FrameInterval) > (OHCI_DEFAULT_FRAME_INTERVAL + MaxFrameIntervalAdjusting))
765  {
766  FrameInterval.FrameInterval = OHCI_DEFAULT_FRAME_INTERVAL;
767  }
768 
769  /* 5.4 FrameInterval Counter */
770  FrameInterval.FrameIntervalToggle = 1;
771 
772  /* OHCI_MAXIMUM_OVERHEAD is the maximum overhead per frame */
773  FrameInterval.FSLargestDataPacket =
774  ((FrameInterval.FrameInterval - OHCI_MAXIMUM_OVERHEAD) * 6) / 7;
775 
776  OhciExtension->FrameInterval = FrameInterval;
777 
778  DPRINT_OHCI("OHCI_StartController: FrameInterval - %lX\n",
779  FrameInterval.AsULONG);
780 
781  /* Reset HostController */
782  CommandStatus.AsULONG = 0;
783  CommandStatus.HostControllerReset = 1;
784 
785  WRITE_REGISTER_ULONG(CommandStatusReg, CommandStatus.AsULONG);
786 
787  KeStallExecutionProcessor(25);
788 
789  Control.AsULONG = READ_REGISTER_ULONG(ControlReg);
790  Control.HostControllerFunctionalState = OHCI_HC_STATE_RESET;
791 
792  WRITE_REGISTER_ULONG(ControlReg, Control.AsULONG);
793 
794  KeQuerySystemTime(&EndTime);
795  EndTime.QuadPart += 500 * 10000; // 0.5 sec
796 
797  while (TRUE)
798  {
799  WRITE_REGISTER_ULONG(FmIntervalReg, OhciExtension->FrameInterval.AsULONG);
800  FrameInterval.AsULONG = READ_REGISTER_ULONG(FmIntervalReg);
801 
802  KeQuerySystemTime(&SystemTime);
803 
804  if (SystemTime.QuadPart >= EndTime.QuadPart)
805  {
806  MPStatus = MP_STATUS_HW_ERROR;
807  break;
808  }
809 
810  if (FrameInterval.AsULONG == OhciExtension->FrameInterval.AsULONG)
811  {
812  MPStatus = MP_STATUS_SUCCESS;
813  break;
814  }
815  }
816 
817  if (MPStatus != MP_STATUS_SUCCESS)
818  {
819  DPRINT_OHCI("OHCI_StartController: frame interval not set\n");
820  return MPStatus;
821  }
822 
823  /* Setup HcPeriodicStart register */
824  WRITE_REGISTER_ULONG(&OperationalRegs->HcPeriodicStart,
825  (OhciExtension->FrameInterval.FrameInterval * 9) / 10); //90%
826 
827  /* Setup HcHCCA register */
828  WRITE_REGISTER_ULONG(&OperationalRegs->HcHCCA,
829  OhciExtension->HcResourcesPA + FIELD_OFFSET(OHCI_HC_RESOURCES, HcHCCA));
830 
831  /* Setup HcInterruptEnable register */
832  Interrupts.AsULONG = 0;
833 
834  Interrupts.SchedulingOverrun = 1;
835  Interrupts.WritebackDoneHead = 1;
836  Interrupts.UnrecoverableError = 1;
837  Interrupts.FrameNumberOverflow = 1;
838  Interrupts.OwnershipChange = 1;
839 
840  WRITE_REGISTER_ULONG(InterruptEnableReg, Interrupts.AsULONG);
841 
842  /* Setup HcControl register */
843  Control.AsULONG = READ_REGISTER_ULONG(ControlReg);
844 
845  Control.ControlBulkServiceRatio = 0; // FIXME (1 : 1)
846  Control.PeriodicListEnable = 1;
847  Control.IsochronousEnable = 1;
848  Control.ControlListEnable = 1;
849  Control.BulkListEnable = 1;
850  Control.HostControllerFunctionalState = OHCI_HC_STATE_OPERATIONAL;
851 
852  WRITE_REGISTER_ULONG(ControlReg, Control.AsULONG);
853 
854  /* Setup HcRhStatus register */
855  RhStatus.AsULONG = 0;
856  RhStatus.SetGlobalPower = 1;
857 
858  WRITE_REGISTER_ULONG(RhStatusReg, RhStatus.AsULONG);
859 
860  return MP_STATUS_SUCCESS;
861 }
862 
863 VOID
864 NTAPI
865 OHCI_StopController(IN PVOID ohciExtension,
866  IN BOOLEAN IsDoDisableInterrupts)
867 {
868  POHCI_EXTENSION OhciExtension = ohciExtension;
869  POHCI_OPERATIONAL_REGISTERS OperationalRegs;
870  PULONG ControlReg;
871  PULONG InterruptDisableReg;
872  PULONG InterruptStatusReg;
873  OHCI_REG_CONTROL Control;
874  OHCI_REG_INTERRUPT_ENABLE_DISABLE IntDisable;
875  OHCI_REG_INTERRUPT_STATUS IntStatus;
876 
877  DPRINT("OHCI_StopController: ... \n");
878 
879  OperationalRegs = OhciExtension->OperationalRegs;
880 
881  ControlReg = (PULONG)&OperationalRegs->HcControl;
882  InterruptDisableReg = (PULONG)&OperationalRegs->HcInterruptDisable;
883  InterruptStatusReg = (PULONG)&OperationalRegs->HcInterruptStatus;
884 
885  /* Setup HcControl register */
886  Control.AsULONG = READ_REGISTER_ULONG(ControlReg);
887 
888  Control.PeriodicListEnable = 0;
889  Control.IsochronousEnable = 0;
890  Control.ControlListEnable = 0;
891  Control.BulkListEnable = 0;
892  Control.HostControllerFunctionalState = OHCI_HC_STATE_SUSPEND;
893  Control.RemoteWakeupEnable = 0;
894 
895  WRITE_REGISTER_ULONG(ControlReg, Control.AsULONG);
896 
897  /* Disable interrupt generations */
898  IntDisable.AsULONG = 0xFFFFFFFF;
899  WRITE_REGISTER_ULONG(InterruptDisableReg, IntDisable.AsULONG);
900 
901  /* Clear all bits in HcInterruptStatus register */
902  IntStatus.AsULONG = 0xFFFFFFFF;
903  WRITE_REGISTER_ULONG(InterruptStatusReg, IntStatus.AsULONG);
904 }
905 
906 VOID
907 NTAPI
908 OHCI_SuspendController(IN PVOID ohciExtension)
909 {
910  POHCI_EXTENSION OhciExtension = ohciExtension;
911  POHCI_OPERATIONAL_REGISTERS OperationalRegs;
912  PULONG ControlReg;
913  PULONG InterruptEnableReg;
914  OHCI_REG_CONTROL Control;
915  OHCI_REG_INTERRUPT_ENABLE_DISABLE InterruptReg;
916 
917  DPRINT("OHCI_SuspendController: ... \n");
918 
919  OperationalRegs = OhciExtension->OperationalRegs;
920  ControlReg = (PULONG)&OperationalRegs->HcControl;
921  InterruptEnableReg = (PULONG)&OperationalRegs->HcInterruptEnable;
922 
923  /* Disable all interrupt generations */
924  WRITE_REGISTER_ULONG(&OperationalRegs->HcInterruptDisable.AsULONG,
925  0xFFFFFFFF);
926 
927  /* Clear all bits in HcInterruptStatus register */
928  WRITE_REGISTER_ULONG(&OperationalRegs->HcInterruptStatus.AsULONG,
929  0xFFFFFFFF);
930 
931  /* Setup HcControl register */
932  Control.AsULONG = READ_REGISTER_ULONG(ControlReg);
933  Control.HostControllerFunctionalState = OHCI_HC_STATE_SUSPEND;
934  Control.RemoteWakeupEnable = 1;
935 
936  WRITE_REGISTER_ULONG(ControlReg, Control.AsULONG);
937 
938  /* Setup HcInterruptEnable register */
939  InterruptReg.AsULONG = 0;
940  InterruptReg.ResumeDetected = 1;
941  InterruptReg.UnrecoverableError = 1;
942  InterruptReg.RootHubStatusChange = 1;
943  InterruptReg.MasterInterruptEnable = 1;
944 
945  WRITE_REGISTER_ULONG(InterruptEnableReg, InterruptReg.AsULONG);
946 }
947 
948 MPSTATUS
949 NTAPI
950 OHCI_ResumeController(IN PVOID ohciExtension)
951 {
952  POHCI_EXTENSION OhciExtension = ohciExtension;
953  POHCI_OPERATIONAL_REGISTERS OperationalRegs;
954  PULONG ControlReg;
955  PULONG InterruptEnableReg;
956  POHCI_HCCA HcHCCA;
957  OHCI_REG_CONTROL control;
958  OHCI_REG_INTERRUPT_ENABLE_DISABLE InterruptReg;
959 
960  DPRINT("OHCI_ResumeController \n");
961 
962  OperationalRegs = OhciExtension->OperationalRegs;
963  ControlReg = (PULONG)&OperationalRegs->HcControl;
964  InterruptEnableReg = (PULONG)&OperationalRegs->HcInterruptEnable;
965 
966  control.AsULONG = READ_REGISTER_ULONG(ControlReg);
967 
968  if (control.HostControllerFunctionalState != OHCI_HC_STATE_SUSPEND)
969  return MP_STATUS_HW_ERROR;
970 
971  HcHCCA = &OhciExtension->HcResourcesVA->HcHCCA;
972  HcHCCA->Pad1 = 0;
973 
974  /* Setup HcControl register */
975  control.HostControllerFunctionalState = OHCI_HC_STATE_OPERATIONAL;
976  WRITE_REGISTER_ULONG(ControlReg, control.AsULONG);
977 
978  /* Setup HcInterruptEnable register */
979  InterruptReg.AsULONG = 0;
980  InterruptReg.SchedulingOverrun = 1;
981  InterruptReg.WritebackDoneHead = 1;
982  InterruptReg.UnrecoverableError = 1;
983  InterruptReg.FrameNumberOverflow = 1;
984  InterruptReg.OwnershipChange = 1;
985 
986  WRITE_REGISTER_ULONG(InterruptEnableReg, InterruptReg.AsULONG);
987  WRITE_REGISTER_ULONG(ControlReg, control.AsULONG);
988 
989  return MP_STATUS_SUCCESS;
990 }
991 
992 BOOLEAN
993 NTAPI
994 OHCI_HardwarePresent(IN POHCI_EXTENSION OhciExtension,
995  IN BOOLEAN IsInvalidateController)
996 {
997  POHCI_OPERATIONAL_REGISTERS OperationalRegs;
998  PULONG CommandStatusReg;
999 
1000  OperationalRegs = OhciExtension->OperationalRegs;
1001  CommandStatusReg = (PULONG)&OperationalRegs->HcCommandStatus;
1002 
1003  if (READ_REGISTER_ULONG(CommandStatusReg) != 0xFFFFFFFF)
1004  return TRUE;
1005 
1006  DPRINT1("OHCI_HardwarePresent: IsInvalidateController - %x\n",
1007  IsInvalidateController);
1008 
1009  if (IsInvalidateController)
1010  {
1011  RegPacket.UsbPortInvalidateController(OhciExtension,
1012  USBPORT_INVALIDATE_CONTROLLER_SURPRISE_REMOVE);
1013  }
1014 
1015  return FALSE;
1016 }
1017 
1018 BOOLEAN
1019 NTAPI
1020 OHCI_InterruptService(IN PVOID ohciExtension)
1021 {
1022  POHCI_EXTENSION OhciExtension = ohciExtension;
1023  POHCI_OPERATIONAL_REGISTERS OperationalRegs;
1024  OHCI_REG_INTERRUPT_STATUS IntStatus;
1025  OHCI_REG_INTERRUPT_ENABLE_DISABLE IntEnable;
1026  OHCI_REG_INTERRUPT_ENABLE_DISABLE IntDisable;
1027  BOOLEAN HardwarePresent = FALSE;
1028 
1029  DPRINT_OHCI("OHCI_Interrupt: Ext %p\n", OhciExtension);
1030 
1031  OperationalRegs = OhciExtension->OperationalRegs;
1032 
1033  HardwarePresent = OHCI_HardwarePresent(OhciExtension, FALSE);
1034 
1035  if (!HardwarePresent)
1036  return FALSE;
1037 
1038  IntEnable.AsULONG = READ_REGISTER_ULONG((PULONG)&OperationalRegs->HcInterruptEnable);
1039  IntStatus.AsULONG = READ_REGISTER_ULONG((PULONG)&OperationalRegs->HcInterruptStatus) & IntEnable.AsULONG;
1040 
1041  if ((IntStatus.AsULONG == 0) || (IntEnable.MasterInterruptEnable == 0))
1042  return FALSE;
1043 
1044  if (IntStatus.UnrecoverableError)
1045  DPRINT1("OHCI_InterruptService: IntStatus.UnrecoverableError\n");
1046 
1047  if (IntStatus.FrameNumberOverflow)
1048  {
1049  POHCI_HCCA HcHCCA;
1050  ULONG fm;
1051  ULONG hp;
1052 
1053  HcHCCA = &OhciExtension->HcResourcesVA->HcHCCA;
1054 
1055  DPRINT("FrameNumberOverflow %lX\n", HcHCCA->FrameNumber);
1056 
1057  hp = OhciExtension->FrameHighPart;
1058  fm = HcHCCA->FrameNumber;
1059 
1060  /* Increment value of FrameHighPart */
1061  OhciExtension->FrameHighPart += 1 * (1 << 16) - ((hp ^ fm) & 0x8000);
1062  }
1063 
1064  /* Disable interrupt generation */
1065  IntDisable.AsULONG = 0;
1066  IntDisable.MasterInterruptEnable = 1;
1067  WRITE_REGISTER_ULONG((PULONG)&OperationalRegs->HcInterruptDisable,
1068  IntDisable.AsULONG);
1069 
1070  return TRUE;
1071 }
1072 
1073 VOID
1074 NTAPI
1075 OHCI_InterruptDpc(IN PVOID ohciExtension,
1076  IN BOOLEAN IsDoEnableInterrupts)
1077 {
1078  POHCI_EXTENSION OhciExtension = ohciExtension;
1079  POHCI_OPERATIONAL_REGISTERS OperationalRegs;
1080  PULONG InterruptDisableReg;
1081  PULONG InterruptEnableReg;
1082  PULONG InterruptStatusReg;
1083  OHCI_REG_INTERRUPT_STATUS IntStatus;
1084  OHCI_REG_INTERRUPT_ENABLE_DISABLE InterruptBits;
1085  POHCI_HCCA HcHCCA;
1086 
1087  OperationalRegs = OhciExtension->OperationalRegs;
1088 
1089  InterruptEnableReg = (PULONG)&OperationalRegs->HcInterruptEnable;
1090  InterruptDisableReg = (PULONG)&OperationalRegs->HcInterruptDisable;
1091  InterruptStatusReg = (PULONG)&OperationalRegs->HcInterruptStatus;
1092 
1093  DPRINT_OHCI("OHCI_InterruptDpc: OhciExtension - %p, IsDoEnableInterrupts - %x\n",
1094  OhciExtension,
1095  IsDoEnableInterrupts);
1096 
1097  IntStatus.AsULONG = READ_REGISTER_ULONG(InterruptStatusReg);
1098 
1099  if (IntStatus.RootHubStatusChange)
1100  {
1101  DPRINT_OHCI("OHCI_InterruptDpc: RootHubStatusChange\n");
1102  RegPacket.UsbPortInvalidateRootHub(OhciExtension);
1103  }
1104 
1105  if (IntStatus.WritebackDoneHead)
1106  {
1107  DPRINT_OHCI("OHCI_InterruptDpc: WritebackDoneHead\n");
1108 
1109  HcHCCA = &OhciExtension->HcResourcesVA->HcHCCA;
1110  HcHCCA->DoneHead = 0;
1111 
1112  RegPacket.UsbPortInvalidateEndpoint(OhciExtension, NULL);
1113  }
1114 
1115  if (IntStatus.StartofFrame)
1116  {
1117  /* Disable interrupt generation due to Start of Frame */
1118  InterruptBits.AsULONG = 0;
1119  InterruptBits.StartofFrame = 1;
1120 
1121  WRITE_REGISTER_ULONG(InterruptDisableReg, InterruptBits.AsULONG);
1122  }
1123 
1124  if (IntStatus.ResumeDetected)
1125  DPRINT1("OHCI_IntDpc: ResumeDetected\n");
1126 
1127  if (IntStatus.UnrecoverableError)
1128  {
1129  DPRINT1("OHCI_IntDpc: UnrecoverableError\n");
1130  }
1131 
1132  WRITE_REGISTER_ULONG(InterruptStatusReg, IntStatus.AsULONG);
1133 
1134  if (IsDoEnableInterrupts)
1135  {
1136  /* Enable interrupt generation */
1137  InterruptBits.AsULONG = 0;
1138  InterruptBits.MasterInterruptEnable = 1;
1139 
1140  WRITE_REGISTER_ULONG(InterruptEnableReg, InterruptBits.AsULONG);
1141  }
1142 }
1143 
1144 ULONG
1145 NTAPI
1146 OHCI_MapTransferToTD(IN POHCI_EXTENSION OhciExtension,
1147  IN ULONG MaxPacketSize,
1148  IN OUT ULONG TransferedLen,
1149  IN POHCI_TRANSFER OhciTransfer,
1150  IN POHCI_HCD_TD TD,
1151  IN PUSBPORT_SCATTER_GATHER_LIST SGList)
1152 {
1153  PUSBPORT_SCATTER_GATHER_ELEMENT SgElement;
1154  ULONG SgIdx;
1155  ULONG SgRemain;
1156  ULONG LengthThisTd;
1157  ULONG BufferEnd;
1158  ULONG Offset;
1159  ULONG TransferLength;
1160  ULONG Buffer;
1161 
1162  DPRINT_OHCI("OHCI_MapTransferToTD: TransferedLen - %x\n", TransferedLen);
1163 
1164  for (SgIdx = 0; SgIdx < SGList->SgElementCount; SgIdx++)
1165  {
1166  SgElement = &SGList->SgElement[SgIdx];
1167 
1168  if (TransferedLen >= SgElement->SgOffset &&
1169  TransferedLen < SgElement->SgOffset + SgElement->SgTransferLength)
1170  {
1171  break;
1172  }
1173  }
1174 
1175  DPRINT_OHCI("OHCI_MapTransferToTD: SgIdx - %x, SgCount - %x\n",
1176  SgIdx,
1177  SGList->SgElementCount);
1178 
1179  ASSERT(SgIdx < SGList->SgElementCount);
1180 
1181  Offset = TransferedLen - SGList->SgElement[SgIdx].SgOffset;
1182  Buffer = SGList->SgElement[SgIdx].SgPhysicalAddress.LowPart + Offset;
1183 
1184  SgRemain = SGList->SgElementCount - SgIdx;
1185 
1186  if (SgRemain == 1)
1187  {
1188  LengthThisTd = OhciTransfer->TransferParameters->TransferBufferLength -
1189  TransferedLen -
1190  Offset;
1191 
1192  BufferEnd = SGList->SgElement[SgIdx].SgPhysicalAddress.LowPart +
1193  LengthThisTd;
1194  }
1195  else if (SgRemain == 2)
1196  {
1197  LengthThisTd = OhciTransfer->TransferParameters->TransferBufferLength -
1198  TransferedLen;
1199 
1200  BufferEnd = SGList->SgElement[SgIdx + 1].SgPhysicalAddress.LowPart +
1201  SGList->SgElement[SgIdx + 1].SgTransferLength;
1202  }
1203  else
1204  {
1205  TransferLength = SGList->SgElement[SgIdx].SgTransferLength +
1206  SGList->SgElement[SgIdx+1].SgTransferLength -
1207  Offset;
1208 
1209  BufferEnd = SGList->SgElement[SgIdx + 1].SgPhysicalAddress.LowPart +
1210  SGList->SgElement[SgIdx + 1].SgTransferLength;
1211 
1212  LengthThisTd = MaxPacketSize * (TransferLength / MaxPacketSize);
1213 
1214  if (TransferLength > LengthThisTd)
1215  BufferEnd -= (TransferLength - LengthThisTd);
1216  }
1217 
1218  TD->HwTD.gTD.CurrentBuffer = Buffer;
1219  TD->HwTD.gTD.BufferEnd = BufferEnd - 1;
1220  TD->TransferLen = LengthThisTd;
1221 
1222  return TransferedLen + LengthThisTd;
1223 }
1224 
1225 POHCI_HCD_TD
1226 NTAPI
1227 OHCI_AllocateTD(IN POHCI_EXTENSION OhciExtension,
1228  IN POHCI_ENDPOINT OhciEndpoint)
1229 {
1230  POHCI_HCD_TD TD;
1231 
1232  DPRINT_OHCI("OHCI_AllocateTD: ... \n");
1233 
1234  TD = OhciEndpoint->FirstTD;
1235 
1236  while (TD->Flags & OHCI_HCD_TD_FLAG_ALLOCATED)
1237  {
1238  TD += 1;
1239  }
1240 
1241  TD->Flags |= OHCI_HCD_TD_FLAG_ALLOCATED;
1242 
1243  return TD;
1244 }
1245 
1246 ULONG
1247 NTAPI
1248 OHCI_RemainTDs(IN POHCI_EXTENSION OhciExtension,
1249  IN POHCI_ENDPOINT OhciEndpoint)
1250 {
1251  POHCI_HCD_TD TD;
1252  ULONG MaxTDs;
1253  ULONG RemainTDs;
1254  ULONG ix;
1255 
1256  DPRINT_OHCI("OHCI_RemainTDs: ... \n");
1257 
1258  MaxTDs = OhciEndpoint->MaxTransferDescriptors;
1259  TD = OhciEndpoint->FirstTD;
1260 
1261  RemainTDs = 0;
1262 
1263  for (ix = 0; ix < MaxTDs; ix++)
1264  {
1265  if (!(TD->Flags & OHCI_HCD_TD_FLAG_ALLOCATED))
1266  RemainTDs++;
1267 
1268  TD += 1;
1269  }
1270 
1271  return RemainTDs;
1272 }
1273 
1274 MPSTATUS
1275 NTAPI
1276 OHCI_ControlTransfer(IN POHCI_EXTENSION OhciExtension,
1277  IN POHCI_ENDPOINT OhciEndpoint,
1278  IN PUSBPORT_TRANSFER_PARAMETERS TransferParameters,
1279  IN POHCI_TRANSFER OhciTransfer,
1280  IN PUSBPORT_SCATTER_GATHER_LIST SGList)
1281 {
1282  POHCI_HCD_TD FirstTD;
1283  ULONG FirstTdPA;
1284  POHCI_HCD_TD TD;
1285  POHCI_HCD_TD TD2;
1286  POHCI_HCD_TD PrevTD;
1287  POHCI_HCD_TD NextTD;
1288  ULONG MaxTDs;
1289  ULONG TransferedLen;
1290  ULONG MaxPacketSize;
1291  ULONG BufferEnd;
1292  UCHAR DataToggle;
1293 
1294  DPRINT_OHCI("OHCI_ControlTransfer: Ext %p, Endpoint %p\n",
1295  OhciExtension,
1296  OhciEndpoint);
1297 
1298  MaxTDs = OHCI_RemainTDs(OhciExtension, OhciEndpoint);
1299 
1300  if ((SGList->SgElementCount + OHCI_NON_DATA_CONTROL_TDS) > MaxTDs)
1301  return MP_STATUS_FAILURE;
1302 
1303  FirstTD = OhciEndpoint->HcdTailP;
1304  FirstTD->HwTD.gTD.Control.DelayInterrupt = OHCI_TD_INTERRUPT_NONE;
1305 
1306  FirstTD->HwTD.gTD.NextTD = 0;
1307  FirstTD->HwTD.gTD.CurrentBuffer = 0;
1308  FirstTD->HwTD.gTD.BufferEnd = 0;
1309 
1310  FirstTD->Flags |= OHCI_HCD_TD_FLAG_PROCESSED;
1311  FirstTD->NextHcdTD = 0;
1312  FirstTD->OhciTransfer = OhciTransfer;
1313 
1314  FirstTD->HwTD.Padded[0] = 0;
1315  FirstTD->HwTD.Padded[1] = 0;
1316 
1317  OhciTransfer->PendingTDs++;
1318 
1319  RtlCopyMemory(&FirstTD->HwTD.SetupPacket,
1320  &TransferParameters->SetupPacket,
1321  sizeof(FirstTD->HwTD.SetupPacket));
1322 
1323  FirstTdPA = FirstTD->PhysicalAddress;
1324 
1325  FirstTD->HwTD.gTD.CurrentBuffer = FirstTdPA + FIELD_OFFSET(OHCI_HCD_TD, HwTD.SetupPacket);
1326 
1327  BufferEnd = FirstTdPA + FIELD_OFFSET(OHCI_HCD_TD, HwTD.SetupPacket) +
1328  sizeof(USB_DEFAULT_PIPE_SETUP_PACKET) - 1;
1329 
1330  FirstTD->HwTD.gTD.BufferEnd = BufferEnd;
1331 
1332  FirstTD->HwTD.gTD.Control.AsULONG = 0;
1333  FirstTD->HwTD.gTD.Control.DelayInterrupt = OHCI_TD_INTERRUPT_NONE;
1334  FirstTD->HwTD.gTD.Control.ConditionCode = OHCI_TD_CONDITION_NOT_ACCESSED;
1335  FirstTD->HwTD.gTD.Control.DataToggle = OHCI_TD_DATA_TOGGLE_DATA0;
1336 
1337  TD2 = OHCI_AllocateTD(OhciExtension, OhciEndpoint);
1338 
1339  TD2->HwTD.gTD.Control.DelayInterrupt = OHCI_TD_INTERRUPT_NONE;
1340  TD2->HwTD.gTD.CurrentBuffer = 0;
1341  TD2->HwTD.gTD.BufferEnd = 0;
1342  TD2->HwTD.gTD.NextTD = 0;
1343 
1344  TD2->Flags |= OHCI_HCD_TD_FLAG_PROCESSED;
1345  TD2->NextHcdTD = 0;
1346  TD2->OhciTransfer = OhciTransfer;
1347 
1348  RtlZeroMemory(&TD2->HwTD.SetupPacket,
1349  sizeof(TD2->HwTD.SetupPacket));
1350 
1351  TD2->HwTD.Padded[0] = 0;
1352  TD2->HwTD.Padded[1] = 0;
1353 
1354  PrevTD = FirstTD;
1355  TD = TD2;
1356 
1357  PrevTD->HwTD.gTD.NextTD = TD2->PhysicalAddress;
1358  PrevTD->NextHcdTD = TD2;
1359 
1360  MaxPacketSize = OhciEndpoint->EndpointProperties.TotalMaxPacketSize;
1361 
1362  TransferedLen = 0;
1363  DataToggle = OHCI_TD_DATA_TOGGLE_DATA1;
1364 
1365  while (TransferedLen < TransferParameters->TransferBufferLength)
1366  {
1367  OhciTransfer->PendingTDs++;
1368 
1369  if (TransferParameters->TransferFlags & USBD_TRANSFER_DIRECTION_IN)
1370  TD->HwTD.gTD.Control.DirectionPID = OHCI_TD_DIRECTION_PID_IN;
1371  else
1372  TD->HwTD.gTD.Control.DirectionPID = OHCI_TD_DIRECTION_PID_OUT;
1373 
1374  TD->HwTD.gTD.Control.DelayInterrupt = OHCI_TD_INTERRUPT_NONE;
1375  TD->HwTD.gTD.Control.DataToggle = DataToggle;
1376  TD->HwTD.gTD.Control.ConditionCode = OHCI_TD_CONDITION_NOT_ACCESSED;
1377 
1378  DataToggle = OHCI_TD_DATA_TOGGLE_FROM_ED;
1379 
1380  TransferedLen = OHCI_MapTransferToTD(OhciExtension,
1381  MaxPacketSize,
1382  TransferedLen,
1383  OhciTransfer,
1384  TD,
1385  SGList);
1386 
1387  PrevTD = TD;
1388 
1389  TD = OHCI_AllocateTD(OhciExtension, OhciEndpoint);
1390 
1391  TD->Flags |= OHCI_HCD_TD_FLAG_PROCESSED;
1392 
1393  TD->HwTD.gTD.NextTD = 0;
1394  TD->HwTD.gTD.Control.DelayInterrupt = OHCI_TD_INTERRUPT_NONE;
1395 
1396  TD->NextHcdTD = 0;
1397  TD->OhciTransfer = OhciTransfer;
1398 
1399  TD->HwTD.gTD.CurrentBuffer = 0;
1400  TD->HwTD.gTD.BufferEnd = 0;
1401 
1402  RtlZeroMemory(&TD->HwTD.SetupPacket,
1403  sizeof(TD->HwTD.SetupPacket));
1404 
1405  TD->HwTD.Padded[0] = 0;
1406  TD->HwTD.Padded[1] = 0;
1407 
1408  PrevTD->HwTD.gTD.NextTD = TD->PhysicalAddress;
1409  PrevTD->NextHcdTD = TD;
1410  }
1411 
1412  if (TransferParameters->TransferFlags & USBD_SHORT_TRANSFER_OK)
1413  {
1414  PrevTD->HwTD.gTD.Control.BufferRounding = TRUE;
1415  OhciTransfer->Flags |= OHCI_TRANSFER_FLAGS_SHORT_TRANSFER_OK;
1416  }
1417 
1418  TD->HwTD.gTD.CurrentBuffer = 0;
1419  TD->HwTD.gTD.BufferEnd = 0;
1420 
1421  TD->Flags |= OHCI_HCD_TD_FLAG_CONTROL_STATUS;
1422  TD->TransferLen = 0;
1423 
1424  TD->HwTD.gTD.Control.AsULONG = 0;
1425 
1426  if ((TransferParameters->TransferFlags & USBD_TRANSFER_DIRECTION_IN) != 0)
1427  {
1428  TD->HwTD.gTD.Control.DirectionPID = OHCI_TD_DIRECTION_PID_OUT;
1429  }
1430  else
1431  {
1432  TD->HwTD.gTD.Control.BufferRounding = TRUE;
1433  TD->HwTD.gTD.Control.DirectionPID = OHCI_TD_DIRECTION_PID_IN;
1434  }
1435 
1436  TD->HwTD.gTD.Control.DataToggle = OHCI_TD_DATA_TOGGLE_DATA1;
1437  TD->HwTD.gTD.Control.ConditionCode = OHCI_TD_CONDITION_NOT_ACCESSED;
1438 
1439  OhciTransfer->PendingTDs++;
1440  OhciTransfer->ControlStatusTD = TD;
1441 
1442  NextTD = OHCI_AllocateTD(OhciExtension, OhciEndpoint);
1443 
1444  TD->HwTD.gTD.NextTD = NextTD->PhysicalAddress;
1445  TD->NextHcdTD = NextTD;
1446 
1447  NextTD->NextHcdTD = 0;
1448  NextTD->HwTD.gTD.NextTD = 0;
1449 
1450  OhciTransfer->NextTD = NextTD;
1451  OhciEndpoint->HcdTailP = NextTD;
1452 
1453  OhciEndpoint->HcdED->HwED.TailPointer = NextTD->PhysicalAddress;
1454 
1455  OHCI_EnableList(OhciExtension, OhciEndpoint);
1456 
1457  return MP_STATUS_SUCCESS;
1458 }
1459 
1460 MPSTATUS
1461 NTAPI
1462 OHCI_BulkOrInterruptTransfer(IN POHCI_EXTENSION OhciExtension,
1463  IN POHCI_ENDPOINT OhciEndpoint,
1464  IN PUSBPORT_TRANSFER_PARAMETERS TransferParameters,
1465  IN POHCI_TRANSFER OhciTransfer,
1466  IN PUSBPORT_SCATTER_GATHER_LIST SGList)
1467 {
1468  POHCI_HCD_TD TD;
1469  POHCI_HCD_TD PrevTD;
1470  ULONG TransferedLen;
1471  ULONG MaxTDs;
1472  ULONG MaxPacketSize;
1473 
1474  DPRINT_OHCI("OHCI_BulkOrInterruptTransfer: ... \n");
1475 
1476  MaxTDs = OHCI_RemainTDs(OhciExtension, OhciEndpoint);
1477 
1478  if (SGList->SgElementCount > MaxTDs)
1479  return MP_STATUS_FAILURE;
1480 
1481  TD = OhciEndpoint->HcdTailP;
1482 
1483  TransferedLen = 0;
1484 
1485  do
1486  {
1487  TD->HwTD.gTD.Control.AsULONG = 0;
1488  TD->HwTD.gTD.Control.DelayInterrupt = OHCI_TD_INTERRUPT_NONE;
1489  TD->HwTD.gTD.Control.ConditionCode = OHCI_TD_CONDITION_NOT_ACCESSED;
1490 
1491  if (TransferParameters->TransferFlags & USBD_TRANSFER_DIRECTION_IN)
1492  {
1493  TD->HwTD.gTD.Control.BufferRounding = 0;
1494  TD->HwTD.gTD.Control.DirectionPID = OHCI_TD_DIRECTION_PID_IN;
1495  }
1496  else
1497  {
1498  TD->HwTD.gTD.Control.BufferRounding = TRUE;
1499  TD->HwTD.gTD.Control.DirectionPID = OHCI_TD_DIRECTION_PID_OUT;
1500  }
1501 
1502  TD->HwTD.gTD.CurrentBuffer = 0;
1503  TD->HwTD.gTD.NextTD = 0;
1504  TD->HwTD.gTD.BufferEnd = 0;
1505 
1506  RtlZeroMemory(&TD->HwTD.SetupPacket,
1507  sizeof(TD->HwTD.SetupPacket));
1508 
1509  TD->HwTD.Padded[0] = 0;
1510  TD->HwTD.Padded[1] = 0;
1511 
1512  TD->Flags |= OHCI_HCD_TD_FLAG_PROCESSED;
1513  TD->OhciTransfer = OhciTransfer;
1514  TD->NextHcdTD = 0;
1515 
1516  if (TransferParameters->TransferBufferLength)
1517  {
1518  MaxPacketSize = OhciEndpoint->EndpointProperties.TotalMaxPacketSize;
1519 
1520  TransferedLen = OHCI_MapTransferToTD(OhciExtension,
1521  MaxPacketSize,
1522  TransferedLen,
1523  OhciTransfer,
1524  TD,
1525  SGList);
1526  }
1527  else
1528  {
1529  ASSERT(SGList->SgElementCount == 0);
1530 
1531  TD->HwTD.gTD.CurrentBuffer = 0;
1532  TD->HwTD.gTD.BufferEnd = 0;
1533 
1534  TD->TransferLen = 0;
1535  }
1536 
1537  PrevTD = TD;
1538 
1539  TD = OHCI_AllocateTD(OhciExtension, OhciEndpoint);
1540  OhciTransfer->PendingTDs++;
1541 
1542  PrevTD->HwTD.gTD.NextTD = TD->PhysicalAddress;
1543  PrevTD->NextHcdTD = TD;
1544  }
1545  while (TransferedLen < TransferParameters->TransferBufferLength);
1546 
1547  if (TransferParameters->TransferFlags & USBD_SHORT_TRANSFER_OK)
1548  {
1549  PrevTD->HwTD.gTD.Control.BufferRounding = TRUE;
1550  OhciTransfer->Flags |= OHCI_TRANSFER_FLAGS_SHORT_TRANSFER_OK;
1551  }
1552 
1553  PrevTD->HwTD.gTD.Control.DelayInterrupt = OHCI_TD_INTERRUPT_IMMEDIATE;
1554  PrevTD->HwTD.gTD.NextTD = TD->PhysicalAddress;
1555  PrevTD->NextHcdTD = TD;
1556 
1557  TD->HwTD.gTD.NextTD = 0;
1558  TD->NextHcdTD = 0;
1559 
1560  OhciTransfer->NextTD = TD;
1561  OhciEndpoint->HcdTailP = TD;
1562 
1563  OhciEndpoint->HcdED->HwED.TailPointer = TD->PhysicalAddress;
1564 
1565  OHCI_EnableList(OhciExtension, OhciEndpoint);
1566 
1567  return MP_STATUS_SUCCESS;
1568 }
1569 
1570 MPSTATUS
1571 NTAPI
1572 OHCI_SubmitTransfer(IN PVOID ohciExtension,
1573  IN PVOID ohciEndpoint,
1574  IN PUSBPORT_TRANSFER_PARAMETERS TransferParameters,
1575  IN PVOID ohciTransfer,
1576  IN PUSBPORT_SCATTER_GATHER_LIST SGList)
1577 {
1578  POHCI_EXTENSION OhciExtension = ohciExtension;
1579  POHCI_ENDPOINT OhciEndpoint = ohciEndpoint;
1580  POHCI_TRANSFER OhciTransfer = ohciTransfer;
1581  ULONG TransferType;
1582 
1583  DPRINT_OHCI("OHCI_SubmitTransfer: ... \n");
1584 
1585  RtlZeroMemory(OhciTransfer, sizeof(OHCI_TRANSFER));
1586 
1587  OhciTransfer->TransferParameters = TransferParameters;
1588  OhciTransfer->OhciEndpoint = OhciEndpoint;
1589 
1590  TransferType = OhciEndpoint->EndpointProperties.TransferType;
1591 
1592  if (TransferType == USBPORT_TRANSFER_TYPE_CONTROL)
1593  {
1594  return OHCI_ControlTransfer(OhciExtension,
1595  OhciEndpoint,
1596  TransferParameters,
1597  OhciTransfer,
1598  SGList);
1599  }
1600 
1601  if (TransferType == USBPORT_TRANSFER_TYPE_BULK ||
1602  TransferType == USBPORT_TRANSFER_TYPE_INTERRUPT)
1603  {
1604  return OHCI_BulkOrInterruptTransfer(OhciExtension,
1605  OhciEndpoint,
1606  TransferParameters,
1607  OhciTransfer,
1608  SGList);
1609  }
1610 
1611  return MP_STATUS_FAILURE;
1612 }
1613 
1614 MPSTATUS
1615 NTAPI
1616 OHCI_SubmitIsoTransfer(IN PVOID ohciExtension,
1617  IN PVOID ohciEndpoint,
1618  IN PUSBPORT_TRANSFER_PARAMETERS TransferParameters,
1619  IN PVOID ohciTransfer,
1620  IN PVOID isoParameters)
1621 {
1622  DPRINT1("OHCI_SubmitIsoTransfer: UNIMPLEMENTED. FIXME\n");
1623  return MP_STATUS_SUCCESS;
1624 }
1625 
1626 VOID
1627 NTAPI
1628 OHCI_ProcessDoneTD(IN POHCI_EXTENSION OhciExtension,
1629  IN POHCI_HCD_TD TD,
1630  IN BOOLEAN IsPortComplete)
1631 {
1632  POHCI_TRANSFER OhciTransfer;
1633  POHCI_ENDPOINT OhciEndpoint;
1634  ULONG Buffer;
1635  ULONG BufferEnd;
1636  ULONG Length;
1637 
1638  DPRINT_OHCI("OHCI_ProcessDoneTD: ... \n");
1639 
1640  OhciTransfer = TD->OhciTransfer;
1641  OhciEndpoint = OhciTransfer->OhciEndpoint;
1642 
1643  OhciTransfer->PendingTDs--;
1644 
1645  Buffer = TD->HwTD.gTD.CurrentBuffer;
1646  BufferEnd = TD->HwTD.gTD.BufferEnd;
1647 
1648  if (TD->Flags & OHCI_HCD_TD_FLAG_NOT_ACCESSED)
1649  {
1650  TD->HwTD.gTD.Control.ConditionCode = OHCI_TD_CONDITION_NO_ERROR;
1651  }
1652  else
1653  {
1654  if (TD->HwTD.gTD.CurrentBuffer)
1655  {
1656  if (TD->TransferLen)
1657  {
1658  Length = (BufferEnd & (PAGE_SIZE - 1)) -
1659  (Buffer & (PAGE_SIZE - 1));
1660 
1661  Length++;
1662 
1663  if (Buffer >> PAGE_SHIFT != BufferEnd >> PAGE_SHIFT)
1664  Length += PAGE_SIZE;
1665 
1666  TD->TransferLen -= Length;
1667  }
1668  }
1669 
1670  if (TD->HwTD.gTD.Control.DirectionPID != OHCI_TD_DIRECTION_PID_SETUP)
1671  OhciTransfer->TransferLen += TD->TransferLen;
1672 
1673  if (TD->HwTD.gTD.Control.ConditionCode)
1674  {
1675  OhciTransfer->USBDStatus = USBD_STATUS_HALTED |
1676  TD->HwTD.gTD.Control.ConditionCode;
1677  }
1678  }
1679 
1680  TD->Flags = 0;
1681  TD->HwTD.gTD.NextTD = 0;
1682  TD->OhciTransfer = 0;
1683 
1684  TD->DoneLink.Flink = NULL;
1685  TD->DoneLink.Blink = NULL;
1686 
1687  if (IsPortComplete && (OhciTransfer->PendingTDs == 0))
1688  {
1689  RegPacket.UsbPortCompleteTransfer(OhciExtension,
1690  OhciEndpoint,
1691  OhciTransfer->TransferParameters,
1692  OhciTransfer->USBDStatus,
1693  OhciTransfer->TransferLen);
1694  }
1695 }
1696 
1697 VOID
1698 NTAPI
1699 OHCI_ProcessDoneIsoTD(IN POHCI_EXTENSION OhciExtension,
1700  IN POHCI_HCD_TD TD,
1701  IN BOOLEAN IsPortComplete)
1702 {
1703  DPRINT1("OHCI_ProcessDoneIsoTD: UNIMPLEMENTED. FIXME\n");
1704 }
1705 
1706 VOID
1707 NTAPI
1708 OHCI_AbortTransfer(IN PVOID ohciExtension,
1709  IN PVOID ohciEndpoint,
1710  IN PVOID ohciTransfer,
1711  IN OUT PULONG CompletedLength)
1712 {
1713  POHCI_EXTENSION OhciExtension = ohciExtension;
1714  POHCI_ENDPOINT OhciEndpoint = ohciEndpoint;
1715  POHCI_TRANSFER OhciTransfer = ohciTransfer;
1716  POHCI_TRANSFER TmpTransfer;
1717  POHCI_HCD_ED ED;
1718  ULONG_PTR NextTdPA;
1719  POHCI_HCD_TD NextTD;
1720  POHCI_HCD_TD TD;
1721  POHCI_HCD_TD PrevTD;
1722  POHCI_HCD_TD LastTD;
1723  POHCI_HCD_TD td = NULL;
1724  ULONG ix;
1725  BOOLEAN IsIsoEndpoint = FALSE;
1726  BOOLEAN IsProcessed = FALSE;
1727 
1728  DPRINT("OHCI_AbortTransfer: ohciEndpoint - %p, ohciTransfer - %p\n",
1729  OhciEndpoint,
1730  OhciTransfer);
1731 
1732  if (OhciEndpoint->EndpointProperties.TransferType ==
1733  USBPORT_TRANSFER_TYPE_ISOCHRONOUS)
1734  {
1735  IsIsoEndpoint = TRUE;
1736  }
1737 
1738  ED = OhciEndpoint->HcdED;
1739  NextTdPA = ED->HwED.HeadPointer & OHCI_ED_HEAD_POINTER_MASK;
1740 
1741  NextTD = RegPacket.UsbPortGetMappedVirtualAddress(NextTdPA,
1742  OhciExtension,
1743  OhciEndpoint);
1744 
1745  if (NextTD->OhciTransfer == OhciTransfer)
1746  {
1747  LastTD = OhciTransfer->NextTD;
1748 
1749  ED->HwED.HeadPointer = LastTD->PhysicalAddress |
1750  (ED->HwED.HeadPointer & OHCI_ED_HEAD_POINTER_CARRY);
1751 
1752  OhciEndpoint->HcdHeadP = LastTD;
1753 
1754  for (ix = 0; ix < OhciEndpoint->MaxTransferDescriptors; ix++)
1755  {
1756  TD = &OhciEndpoint->FirstTD[ix];
1757 
1758  if (TD->OhciTransfer == OhciTransfer)
1759  {
1760  if (IsIsoEndpoint)
1761  OHCI_ProcessDoneIsoTD(OhciExtension, TD, FALSE);
1762  else
1763  OHCI_ProcessDoneTD(OhciExtension, TD, FALSE);
1764  }
1765  }
1766 
1767  *CompletedLength = OhciTransfer->TransferLen;
1768  return;
1769  }
1770 
1771  TD = OhciEndpoint->HcdHeadP;
1772 
1773  if (TD == NextTD)
1774  goto Exit;
1775 
1776  do
1777  {
1778  if (TD->OhciTransfer == ohciTransfer)
1779  {
1780  PrevTD = TD;
1781  TD = TD->NextHcdTD;
1782 
1783  if (PrevTD == OhciEndpoint->HcdHeadP)
1784  OhciEndpoint->HcdHeadP = TD;
1785 
1786  if (IsIsoEndpoint)
1787  OHCI_ProcessDoneIsoTD(OhciExtension, PrevTD, FALSE);
1788  else
1789  OHCI_ProcessDoneTD(OhciExtension, PrevTD, FALSE);
1790 
1791  IsProcessed = TRUE;
1792  }
1793  else
1794  {
1795  TD = TD->NextHcdTD;
1796  }
1797  }
1798  while (TD != NextTD);
1799 
1800  if (!IsProcessed)
1801  {
1802  TD = OhciEndpoint->HcdHeadP;
1803 
1804  LastTD = TD;
1805  td = NULL;
1806 
1807  while (TD != OhciEndpoint->HcdTailP)
1808  {
1809  if (TD->OhciTransfer == OhciTransfer)
1810  {
1811  td = TD;
1812  break;
1813  }
1814 
1815  LastTD = TD;
1816 
1817  TD = TD->NextHcdTD;
1818  }
1819 
1820  TD = td;
1821 
1822  do
1823  {
1824  if (TD == OhciEndpoint->HcdTailP)
1825  break;
1826 
1827  PrevTD = TD;
1828  TD = TD->NextHcdTD;
1829 
1830  if (IsIsoEndpoint)
1831  OHCI_ProcessDoneIsoTD(OhciExtension, PrevTD, FALSE);
1832  else
1833  OHCI_ProcessDoneTD(OhciExtension, PrevTD, FALSE);
1834  }
1835  while (TD->OhciTransfer == OhciTransfer);
1836 
1837  TmpTransfer = LastTD->OhciTransfer;
1838  TmpTransfer->NextTD = TD;
1839 
1840  LastTD->NextHcdTD = TD;
1841  LastTD->HwTD.gTD.NextTD = TD->PhysicalAddress;
1842  }
1843 
1844 Exit:
1845 
1846  *CompletedLength = OhciTransfer->TransferLen;
1847 
1848  if (OhciTransfer->TransferLen)
1849  {
1850  DPRINT("OHCI_AbortTransfer: *CompletedLength - %x\n", *CompletedLength);
1851  }
1852 }
1853 
1854 ULONG
1855 NTAPI
1856 OHCI_GetEndpointState(IN PVOID ohciExtension,
1857  IN PVOID ohciEndpoint)
1858 {
1859  POHCI_ENDPOINT OhciEndpoint = ohciEndpoint;
1860  POHCI_HCD_ED ED;
1861 
1862  DPRINT_OHCI("OHCI_GetEndpointState: ... \n");
1863 
1864  ED = OhciEndpoint->HcdED;
1865 
1866  if (ED->Flags & OHCI_HCD_TD_FLAG_NOT_ACCESSED)
1867  return USBPORT_ENDPOINT_REMOVE;
1868 
1869  if (ED->HwED.EndpointControl.sKip)
1870  return USBPORT_ENDPOINT_PAUSED;
1871 
1872  return USBPORT_ENDPOINT_ACTIVE;
1873 }
1874 
1875 VOID
1876 NTAPI
1877 OHCI_RemoveEndpointFromSchedule(IN POHCI_ENDPOINT OhciEndpoint)
1878 {
1879  POHCI_HCD_ED ED;
1880  POHCI_HCD_ED PreviousED;
1881  POHCI_STATIC_ED HeadED;
1882 
1883  DPRINT_OHCI("OHCI_RemoveEndpointFromSchedule \n");
1884 
1885  ED = OhciEndpoint->HcdED;
1886  HeadED = OhciEndpoint->HeadED;
1887 
1888  if (&HeadED->Link == ED->HcdEDLink.Blink)
1889  {
1890  if (HeadED->Type == OHCI_STATIC_ED_TYPE_CONTROL ||
1891  HeadED->Type == OHCI_STATIC_ED_TYPE_BULK)
1892  {
1893  WRITE_REGISTER_ULONG(HeadED->pNextED, ED->HwED.NextED);
1894  }
1895  else if (HeadED->Type == OHCI_STATIC_ED_TYPE_INTERRUPT)
1896  {
1897  *HeadED->pNextED = ED->HwED.NextED;
1898  }
1899  else
1900  {
1901  DPRINT1("OHCI_RemoveEndpointFromSchedule: Unknown HeadED->Type - %x\n",
1902  HeadED->Type);
1903  DbgBreakPoint();
1904  }
1905  }
1906  else
1907  {
1908  PreviousED = CONTAINING_RECORD(ED->HcdEDLink.Blink,
1909  OHCI_HCD_ED,
1910  HcdEDLink);
1911 
1912  PreviousED->HwED.NextED = ED->HwED.NextED;
1913  }
1914 
1915  RemoveEntryList(&ED->HcdEDLink);
1916 
1917  OhciEndpoint->HeadED = NULL;
1918 }
1919 
1920 VOID
1921 NTAPI
1922 OHCI_SetEndpointState(IN PVOID ohciExtension,
1923  IN PVOID ohciEndpoint,
1924  IN ULONG EndpointState)
1925 {
1926  POHCI_EXTENSION OhciExtension = ohciExtension;
1927  POHCI_ENDPOINT OhciEndpoint = ohciEndpoint;
1928  POHCI_HCD_ED ED;
1929 
1930  DPRINT_OHCI("OHCI_SetEndpointState: EndpointState - %x\n",
1931  EndpointState);
1932 
1933  ED = OhciEndpoint->HcdED;
1934 
1935  switch (EndpointState)
1936  {
1937  case USBPORT_ENDPOINT_PAUSED:
1938  ED->HwED.EndpointControl.sKip = 1;
1939  break;
1940 
1941  case USBPORT_ENDPOINT_ACTIVE:
1942  ED->HwED.EndpointControl.sKip = 0;
1943  OHCI_EnableList(OhciExtension, OhciEndpoint);
1944  break;
1945 
1946  case USBPORT_ENDPOINT_REMOVE:
1947  ED->HwED.EndpointControl.sKip = 1;
1948  ED->Flags |= OHCI_HCD_ED_FLAG_NOT_ACCESSED;
1949  OHCI_RemoveEndpointFromSchedule(OhciEndpoint);
1950  break;
1951 
1952  default:
1953  ASSERT(FALSE);
1954  break;
1955  }
1956 }
1957 
1958 VOID
1959 NTAPI
1960 OHCI_PollAsyncEndpoint(IN POHCI_EXTENSION OhciExtension,
1961  IN POHCI_ENDPOINT OhciEndpoint)
1962 {
1963  PUSBPORT_TRANSFER_PARAMETERS TransferParameters;
1964  POHCI_HCD_ED ED;
1965  ULONG_PTR NextTdPA;
1966  POHCI_HCD_TD NextTD;
1967  POHCI_HCD_TD TD;
1968  PLIST_ENTRY DoneList;
1969  POHCI_TRANSFER OhciTransfer;
1970  POHCI_HCD_TD ControlStatusTD;
1971  ULONG_PTR PhysicalAddress;
1972  ULONG TransferNumber;
1973  POHCI_TRANSFER transfer;
1974  UCHAR ConditionCode;
1975  BOOLEAN IsResetOnHalt = FALSE;
1976 
1977  //DPRINT_OHCI("OHCI_PollAsyncEndpoint: Endpoint - %p\n", OhciEndpoint);
1978 
1979  ED = OhciEndpoint->HcdED;
1980  NextTdPA = ED->HwED.HeadPointer & OHCI_ED_HEAD_POINTER_MASK;
1981 
1982  if (!NextTdPA)
1983  {
1984  OHCI_DumpHcdED(ED);
1985  DbgBreakPoint();
1986  }
1987 
1988  NextTD = RegPacket.UsbPortGetMappedVirtualAddress(NextTdPA,
1989  OhciExtension,
1990  OhciEndpoint);
1991  DPRINT_OHCI("NextTD - %p\n", NextTD);
1992 
1993  if ((ED->HwED.HeadPointer & OHCI_ED_HEAD_POINTER_HALT) == 0)
1994  goto ProcessListTDs;
1995 
1996  OHCI_DumpHcdED(ED);
1997 
1998  IsResetOnHalt = (ED->Flags & OHCI_HCD_ED_FLAG_RESET_ON_HALT) != 0;
1999  DPRINT1("PollAsyncEndpoint: IsResetOnHalt %x\n", IsResetOnHalt);
2000 
2001  for (TD = OhciEndpoint->HcdHeadP; ; TD = TD->NextHcdTD)
2002  {
2003  if (!TD)
2004  {
2005  OHCI_DumpHcdED(ED);
2006  DbgBreakPoint();
2007  }
2008 
2009  if (TD == NextTD)
2010  {
2011  DPRINT("TD == NextTD - %p\n", TD);
2012  goto HandleDoneList;
2013  }
2014 
2015  OhciTransfer = TD->OhciTransfer;
2016  ConditionCode = TD->HwTD.gTD.Control.ConditionCode;
2017 
2018  DPRINT("TD - %p, ConditionCode - %X\n", TD, ConditionCode);
2019  OHCI_DumpHcdTD(TD);
2020 
2021  switch (ConditionCode)
2022  {
2023  case OHCI_TD_CONDITION_NO_ERROR:
2024  TD->Flags |= OHCI_HCD_TD_FLAG_DONE;
2025  InsertTailList(&OhciEndpoint->TDList, &TD->DoneLink);
2026  continue;
2027 
2028  case OHCI_TD_CONDITION_NOT_ACCESSED:
2029  TD->Flags |= (OHCI_HCD_TD_FLAG_DONE | OHCI_HCD_TD_FLAG_NOT_ACCESSED);
2030  InsertTailList(&OhciEndpoint->TDList, &TD->DoneLink);
2031  continue;
2032 
2033  case OHCI_TD_CONDITION_DATA_UNDERRUN:
2034  DPRINT1("DATA_UNDERRUN. Transfer->Flags - %X\n", OhciTransfer->Flags);
2035 
2036  if (OhciTransfer->Flags & OHCI_TRANSFER_FLAGS_SHORT_TRANSFER_OK)
2037  {
2038  IsResetOnHalt = TRUE;
2039  TD->HwTD.gTD.Control.ConditionCode = OHCI_TD_CONDITION_NO_ERROR;
2040 
2041  ControlStatusTD = OhciTransfer->ControlStatusTD;
2042 
2043  if ((TD->Flags & OHCI_HCD_TD_FLAG_CONTROL_STATUS) == 0 &&
2044  ControlStatusTD)
2045  {
2046  PhysicalAddress = ControlStatusTD->PhysicalAddress;
2047  PhysicalAddress |= (ED->HwED.HeadPointer &
2048  OHCI_ED_HEAD_POINTER_FLAGS_MASK);
2049 
2050  ED->HwED.HeadPointer = PhysicalAddress;
2051 
2052  NextTD = OhciTransfer->ControlStatusTD;
2053  DPRINT("PhysicalAddress - %p, NextTD - %p\n", PhysicalAddress, NextTD);
2054  }
2055  else
2056  {
2057  TransferParameters = OhciTransfer->TransferParameters;
2058 
2059  if (TransferParameters->IsTransferSplited)
2060  {
2061  TransferNumber = TransferParameters->TransferCounter;
2062  transfer = OhciTransfer;
2063 
2064  do
2065  {
2066  transfer = transfer->NextTD->OhciTransfer;
2067  NextTD = transfer->NextTD;
2068  }
2069  while (transfer && TransferNumber ==
2070  transfer->TransferParameters->TransferCounter);
2071 
2072  PhysicalAddress = NextTD->PhysicalAddress;
2073  PhysicalAddress |= (ED->HwED.HeadPointer &
2074  OHCI_ED_HEAD_POINTER_FLAGS_MASK);
2075 
2076  ED->HwED.HeadPointer = PhysicalAddress;
2077  DPRINT("PhysicalAddress - %p, NextTD - %p\n", PhysicalAddress, NextTD);
2078  }
2079  else
2080  {
2081  PhysicalAddress = OhciTransfer->NextTD->PhysicalAddress;
2082  PhysicalAddress |= (ED->HwED.HeadPointer &
2083  OHCI_ED_HEAD_POINTER_FLAGS_MASK);
2084 
2085  ED->HwED.HeadPointer = PhysicalAddress;
2086 
2087  NextTD = OhciTransfer->NextTD;
2088  DPRINT("PhysicalAddress - %p, NextTD - %p\n", PhysicalAddress, NextTD);
2089  }
2090  }
2091 
2092  TD->Flags |= OHCI_HCD_TD_FLAG_DONE;
2093  InsertTailList(&OhciEndpoint->TDList, &TD->DoneLink);
2094  continue;
2095  }
2096 
2097  /* fall through */
2098 
2099  default:
2100  TD->Flags |= OHCI_HCD_TD_FLAG_DONE;
2101  InsertTailList(&OhciEndpoint->TDList, &TD->DoneLink);
2102 
2103  ED->HwED.HeadPointer = OhciTransfer->NextTD->PhysicalAddress |
2104  (ED->HwED.HeadPointer &
2105  OHCI_ED_HEAD_POINTER_FLAGS_MASK);
2106 
2107  NextTD = OhciTransfer->NextTD;
2108  break;
2109  }
2110  }
2111 
2112 ProcessListTDs:
2113 
2114  TD = OhciEndpoint->HcdHeadP;
2115 
2116  while (TD != NextTD)
2117  {
2118  OHCI_DumpHcdTD(TD);
2119  TD->Flags |= OHCI_HCD_TD_FLAG_DONE;
2120  InsertTailList(&OhciEndpoint->TDList, &TD->DoneLink);
2121  TD = TD->NextHcdTD;
2122  }
2123 
2124 HandleDoneList:
2125 
2126  TD = NextTD;
2127  OhciEndpoint->HcdHeadP = NextTD;
2128 
2129  DoneList = &OhciEndpoint->TDList;
2130 
2131  while (!IsListEmpty(DoneList))
2132  {
2133  TD = CONTAINING_RECORD(DoneList->Flink,
2134  OHCI_HCD_TD,
2135  DoneLink);
2136 
2137  RemoveHeadList(DoneList);
2138 
2139  if (TD->Flags & OHCI_HCD_TD_FLAG_DONE &&
2140  TD->Flags & OHCI_HCD_TD_FLAG_PROCESSED)
2141  {
2142  OHCI_ProcessDoneTD(OhciExtension, TD, TRUE);
2143  }
2144  }
2145 
2146  if (IsResetOnHalt)
2147  {
2148  ED->HwED.HeadPointer &= ~OHCI_ED_HEAD_POINTER_HALT;
2149  DPRINT("ED->HwED.HeadPointer - %p\n", ED->HwED.HeadPointer);
2150  }
2151 }
2152 
2153 VOID
2154 NTAPI
2155 OHCI_PollIsoEndpoint(IN POHCI_EXTENSION OhciExtension,
2156  IN POHCI_ENDPOINT OhciEndpoint)
2157 {
2158  DPRINT1("OHCI_PollAsyncEndpoint: UNIMPLEMENTED. FIXME \n");
2159  ASSERT(FALSE);
2160 }
2161 
2162 VOID
2163 NTAPI
2164 OHCI_PollEndpoint(IN PVOID ohciExtension,
2165  IN PVOID ohciEndpoint)
2166 {
2167  POHCI_EXTENSION OhciExtension = ohciExtension;
2168  POHCI_ENDPOINT OhciEndpoint = ohciEndpoint;
2169  ULONG TransferType;
2170 
2171  DPRINT_OHCI("OHCI_PollEndpoint: OhciExtension - %p, Endpoint - %p\n",
2172  OhciExtension,
2173  OhciEndpoint);
2174 
2175  TransferType = OhciEndpoint->EndpointProperties.TransferType;
2176 
2177  if (TransferType == USBPORT_TRANSFER_TYPE_ISOCHRONOUS)
2178  {
2179  OHCI_PollIsoEndpoint(OhciExtension, OhciEndpoint);
2180  return;
2181  }
2182 
2183  if (TransferType == USBPORT_TRANSFER_TYPE_CONTROL ||
2184  TransferType == USBPORT_TRANSFER_TYPE_BULK ||
2185  TransferType == USBPORT_TRANSFER_TYPE_INTERRUPT)
2186  {
2187  OHCI_PollAsyncEndpoint(OhciExtension, OhciEndpoint);
2188  }
2189 }
2190 
2191 VOID
2192 NTAPI
2193 OHCI_CheckController(IN PVOID ohciExtension)
2194 {
2195  POHCI_EXTENSION OhciExtension = ohciExtension;
2196  POHCI_OPERATIONAL_REGISTERS OperationalRegs;
2197  PULONG HcControlReg;
2198  OHCI_REG_CONTROL HcControl;
2199  ULONG FmNumber;
2200  USHORT FmDiff;
2201  POHCI_HCCA HcHCCA;
2202 
2203  //DPRINT_OHCI("OHCI_CheckController: ...\n");
2204 
2205  OperationalRegs = OhciExtension->OperationalRegs;
2206 
2207  if (!OHCI_HardwarePresent(OhciExtension, TRUE))
2208  return;
2209 
2210  HcControlReg = (PULONG)&OperationalRegs->HcControl;
2211  HcControl.AsULONG = READ_REGISTER_ULONG(HcControlReg);
2212 
2213  if (HcControl.HostControllerFunctionalState != OHCI_HC_STATE_OPERATIONAL)
2214  return;
2215 
2216  FmNumber = READ_REGISTER_ULONG(&OperationalRegs->HcFmNumber);
2217  FmDiff = (USHORT)(FmNumber - OhciExtension->HcdFmNumber);
2218 
2219  if (FmNumber == 0 || FmDiff < 5)
2220  return;
2221 
2222  HcHCCA = &OhciExtension->HcResourcesVA->HcHCCA;
2223  OhciExtension->HcdFmNumber = FmNumber;
2224 
2225  if (HcHCCA->Pad1 == 0)
2226  {
2227  HcHCCA->Pad1 = 0xBAD1;
2228  return;
2229  }
2230 
2231  DPRINT1("OHCI_CheckController: HcHCCA->Pad1 - %x\n", HcHCCA->Pad1);
2232 
2233  if (HcHCCA->Pad1 == 0xBAD1)
2234  {
2235  HcHCCA->Pad1 = 0xBAD2;
2236  }
2237  else if (HcHCCA->Pad1 == 0xBAD2)
2238  {
2239  HcHCCA->Pad1 = 0xBAD3;
2240 
2241  RegPacket.UsbPortInvalidateController(OhciExtension,
2242  USBPORT_INVALIDATE_CONTROLLER_RESET);
2243  }
2244 }
2245 
2246 ULONG
2247 NTAPI
2248 OHCI_Get32BitFrameNumber(IN PVOID ohciExtension)
2249 {
2250  POHCI_EXTENSION OhciExtension = ohciExtension;
2251  POHCI_HCCA HcHCCA;
2252  ULONG fm;
2253  ULONG hp;
2254 
2255  HcHCCA = &OhciExtension->HcResourcesVA->HcHCCA;
2256 
2257  /* 5.4 FrameInterval Counter: Get32BitFrameNumber() */
2258 
2259  hp = OhciExtension->FrameHighPart;
2260  fm = HcHCCA->FrameNumber;
2261 
2262  DPRINT_OHCI("OHCI_Get32BitFrameNumber: hp - %lX, fm - %lX\n", hp, fm);
2263 
2264  return ((fm & 0x7FFF) | hp) + ((fm ^ hp) & 0x8000);
2265 }
2266 
2267 VOID
2268 NTAPI
2269 OHCI_InterruptNextSOF(IN PVOID ohciExtension)
2270 {
2271  POHCI_EXTENSION OhciExtension = ohciExtension;
2272  POHCI_OPERATIONAL_REGISTERS OperationalRegs;
2273  PULONG InterruptEnableReg;
2274  OHCI_REG_INTERRUPT_ENABLE_DISABLE IntEnable;
2275 
2276  DPRINT_OHCI("OHCI_InterruptNextSOF: OhciExtension - %p\n",
2277  OhciExtension);
2278 
2279  OperationalRegs = OhciExtension->OperationalRegs;
2280  InterruptEnableReg = (PULONG)&OperationalRegs->HcInterruptEnable;
2281 
2282  /* Enable interrupt generation due to Start of Frame */
2283  IntEnable.AsULONG = 0;
2284  IntEnable.StartofFrame = 1;
2285 
2286  WRITE_REGISTER_ULONG(InterruptEnableReg, IntEnable.AsULONG);
2287 }
2288 
2289 VOID
2290 NTAPI
2291 OHCI_EnableInterrupts(IN PVOID ohciExtension)
2292 {
2293  POHCI_EXTENSION OhciExtension = ohciExtension;
2294  POHCI_OPERATIONAL_REGISTERS OperationalRegs;
2295  PULONG InterruptEnableReg;
2296  OHCI_REG_INTERRUPT_ENABLE_DISABLE IntEnable;
2297 
2298  DPRINT_OHCI("OHCI_EnableInterrupts: OhciExtension - %p\n",
2299  OhciExtension);
2300 
2301  OperationalRegs = OhciExtension->OperationalRegs;
2302  InterruptEnableReg = (PULONG)&OperationalRegs->HcInterruptEnable;
2303 
2304  /* Enable interrupt generation */
2305  IntEnable.AsULONG = 0;
2306  IntEnable.MasterInterruptEnable = 1;
2307 
2308  WRITE_REGISTER_ULONG(InterruptEnableReg, IntEnable.AsULONG);
2309 }
2310 
2311 VOID
2312 NTAPI
2313 OHCI_DisableInterrupts(IN PVOID ohciExtension)
2314 {
2315  POHCI_EXTENSION OhciExtension = ohciExtension;
2316  POHCI_OPERATIONAL_REGISTERS OperationalRegs;
2317  PULONG InterruptDisableReg;
2318  OHCI_REG_INTERRUPT_ENABLE_DISABLE IntDisable;
2319 
2320  DPRINT_OHCI("OHCI_DisableInterrupts\n");
2321 
2322  OperationalRegs = OhciExtension->OperationalRegs;
2323  InterruptDisableReg = (PULONG)&OperationalRegs->HcInterruptDisable;
2324 
2325  /* Disable interrupt generation */
2326  IntDisable.AsULONG = 0;
2327  IntDisable.MasterInterruptEnable = 1;
2328 
2329  WRITE_REGISTER_ULONG(InterruptDisableReg, IntDisable.AsULONG);
2330 }
2331 
2332 VOID
2333 NTAPI
2334 OHCI_PollController(IN PVOID ohciExtension)
2335 {
2336  DPRINT1("OHCI_PollController: UNIMPLEMENTED. FIXME\n");
2337 }
2338 
2339 VOID
2340 NTAPI
2341 OHCI_SetEndpointDataToggle(IN PVOID ohciExtension,
2342  IN PVOID ohciEndpoint,
2343  IN ULONG DataToggle)
2344 {
2345  POHCI_ENDPOINT OhciEndpoint = ohciEndpoint;
2346  POHCI_HCD_ED ED;
2347 
2348  DPRINT_OHCI("OHCI_SetEndpointDataToggle: Endpoint - %p, DataToggle - %x\n",
2349  OhciEndpoint,
2350  DataToggle);
2351 
2352  ED = OhciEndpoint->HcdED;
2353 
2354  if (DataToggle)
2355  ED->HwED.HeadPointer |= OHCI_ED_HEAD_POINTER_CARRY;
2356  else
2357  ED->HwED.HeadPointer &= ~OHCI_ED_HEAD_POINTER_CARRY;
2358 }
2359 
2360 ULONG
2361 NTAPI
2362 OHCI_GetEndpointStatus(IN PVOID ohciExtension,
2363  IN PVOID ohciEndpoint)
2364 {
2365  POHCI_ENDPOINT OhciEndpoint = ohciEndpoint;
2366  POHCI_HCD_ED ED;
2367  ULONG EndpointStatus = USBPORT_ENDPOINT_RUN;
2368 
2369  DPRINT_OHCI("OHCI_GetEndpointStatus: ... \n");
2370 
2371  ED = OhciEndpoint->HcdED;
2372 
2373  if ((ED->HwED.HeadPointer & OHCI_ED_HEAD_POINTER_HALT) &&
2374  !(ED->Flags & OHCI_HCD_ED_FLAG_RESET_ON_HALT))
2375  {
2376  EndpointStatus = USBPORT_ENDPOINT_HALT;
2377  }
2378 
2379  return EndpointStatus;
2380 }
2381 
2382 VOID
2383 NTAPI
2384 OHCI_SetEndpointStatus(IN PVOID ohciExtension,
2385  IN PVOID ohciEndpoint,
2386  IN ULONG EndpointStatus)
2387 {
2388  POHCI_EXTENSION OhciExtension = ohciExtension;
2389  POHCI_ENDPOINT OhciEndpoint = ohciEndpoint;
2390  POHCI_HCD_ED ED;
2391 
2392  DPRINT_OHCI("OHCI_SetEndpointStatus: Endpoint - %p, EndpointStatus - %lX\n",
2393  OhciEndpoint,
2394  EndpointStatus);
2395 
2396  if (EndpointStatus == USBPORT_ENDPOINT_RUN)
2397  {
2398  ED = OhciEndpoint->HcdED;
2399  ED->HwED.HeadPointer &= ~OHCI_ED_HEAD_POINTER_HALT;
2400 
2401  OHCI_EnableList(OhciExtension, OhciEndpoint);
2402  }
2403  else if (EndpointStatus == USBPORT_ENDPOINT_HALT)
2404  {
2405  ASSERT(FALSE);
2406  }
2407 }
2408 
2409 VOID
2410 NTAPI
2411 OHCI_ResetController(IN PVOID ohciExtension)
2412 {
2413  POHCI_EXTENSION OhciExtension = ohciExtension;
2414  POHCI_OPERATIONAL_REGISTERS OperationalRegs;
2415  ULONG FrameNumber;
2416  PULONG ControlReg;
2417  PULONG CommandStatusReg;
2418  PULONG InterruptEnableReg;
2419  PULONG FmIntervalReg;
2420  PULONG RhStatusReg;
2421  PULONG PortStatusReg;
2422  OHCI_REG_CONTROL ControlBak;
2423  OHCI_REG_CONTROL Control;
2424  OHCI_REG_COMMAND_STATUS CommandStatus;
2425  OHCI_REG_INTERRUPT_ENABLE_DISABLE IntEnable;
2426  ULONG_PTR HCCA;
2427  ULONG_PTR ControlHeadED;
2428  ULONG_PTR BulkHeadED;
2429  OHCI_REG_FRAME_INTERVAL FrameInterval;
2430  ULONG_PTR PeriodicStart;
2431  ULONG_PTR LSThreshold;
2432  OHCI_REG_RH_STATUS RhStatus;
2433  OHCI_REG_RH_DESCRIPTORA RhDescriptorA;
2434  OHCI_REG_RH_PORT_STATUS PortStatus;
2435  ULONG NumPorts;
2436  ULONG ix;
2437 
2438  DPRINT("OHCI_ResetController: ... \n");
2439 
2440  OperationalRegs = OhciExtension->OperationalRegs;
2441 
2442  ControlReg = (PULONG)&OperationalRegs->HcControl;
2443  CommandStatusReg = (PULONG)&OperationalRegs->HcCommandStatus;
2444  InterruptEnableReg = (PULONG)&OperationalRegs->HcInterruptEnable;
2445  FmIntervalReg = (PULONG)&OperationalRegs->HcFmInterval;
2446  RhStatusReg = (PULONG)&OperationalRegs->HcRhStatus;
2447 
2448  /* Backup FrameNumber from HcHCCA */
2449  FrameNumber = OhciExtension->HcResourcesVA->HcHCCA.FrameNumber;
2450 
2451  /* Backup registers */
2452  ControlBak.AsULONG = READ_REGISTER_ULONG(ControlReg);
2453  HCCA = READ_REGISTER_ULONG(&OperationalRegs->HcHCCA);
2454  ControlHeadED = READ_REGISTER_ULONG(&OperationalRegs->HcControlHeadED);
2455  BulkHeadED = READ_REGISTER_ULONG(&OperationalRegs->HcBulkHeadED);
2456  FrameInterval.AsULONG = READ_REGISTER_ULONG(FmIntervalReg);
2457  PeriodicStart = READ_REGISTER_ULONG(&OperationalRegs->HcPeriodicStart);
2458  LSThreshold = READ_REGISTER_ULONG(&OperationalRegs->HcLSThreshold);
2459 
2460  /* Reset HostController */
2461  CommandStatus.AsULONG = 0;
2462  CommandStatus.HostControllerReset = 1;
2463  WRITE_REGISTER_ULONG(CommandStatusReg, CommandStatus.AsULONG);
2464 
2465  KeStallExecutionProcessor(10);
2466 
2467  /* Restore registers */
2468  WRITE_REGISTER_ULONG(&OperationalRegs->HcHCCA, HCCA);
2469  WRITE_REGISTER_ULONG(&OperationalRegs->HcControlHeadED, ControlHeadED);
2470  WRITE_REGISTER_ULONG(&OperationalRegs->HcBulkHeadED, BulkHeadED);
2471 
2472  /* Set OPERATIONAL state for HC */
2473  Control.AsULONG = 0;
2474  Control.HostControllerFunctionalState = OHCI_HC_STATE_OPERATIONAL;
2475  WRITE_REGISTER_ULONG(ControlReg, Control.AsULONG);
2476 
2477  /* Set Toggle bit for FmInterval register */
2478  FrameInterval.FrameIntervalToggle = 1;
2479  WRITE_REGISTER_ULONG(FmIntervalReg, FrameInterval.AsULONG);
2480 
2481  /* Restore registers */
2482  WRITE_REGISTER_ULONG(&OperationalRegs->HcFmNumber, FrameNumber);
2483  WRITE_REGISTER_ULONG(&OperationalRegs->HcPeriodicStart, PeriodicStart);
2484  WRITE_REGISTER_ULONG(&OperationalRegs->HcLSThreshold, LSThreshold);
2485 
2486  /* Setup RhStatus register */
2487  RhStatus.AsULONG = 0;
2488  RhStatus.SetRemoteWakeupEnable = 1;
2489  RhStatus.SetGlobalPower = 1;
2490  WRITE_REGISTER_ULONG(RhStatusReg, RhStatus.AsULONG);
2491 
2492  /* Setup RH PortStatus registers */
2493  RhDescriptorA = OHCI_ReadRhDescriptorA(OhciExtension);
2494  NumPorts = RhDescriptorA.NumberDownstreamPorts;
2495 
2496  PortStatus.AsULONG = 0;
2497  PortStatus.SetPortPower = 1;
2498 
2499  for (ix = 0; ix < NumPorts; ix++)
2500  {
2501  PortStatusReg = (PULONG)&OperationalRegs->HcRhPortStatus[ix];
2502  WRITE_REGISTER_ULONG(PortStatusReg, PortStatus.AsULONG);
2503  }
2504 
2505  /* Restore HcControl register */
2506  ControlBak.HostControllerFunctionalState = OHCI_HC_STATE_OPERATIONAL;
2507  WRITE_REGISTER_ULONG(ControlReg, ControlBak.AsULONG);
2508 
2509  /* Setup HcInterruptEnable register */
2510  IntEnable.AsULONG = 0xFFFFFFFF;
2511  IntEnable.Reserved1 = 0;
2512  WRITE_REGISTER_ULONG(InterruptEnableReg, IntEnable.AsULONG);
2513 }
2514 
2515 MPSTATUS
2516 NTAPI
2517 OHCI_StartSendOnePacket(IN PVOID ohciExtension,
2518  IN PVOID PacketParameters,
2519  IN PVOID Data,
2520  IN PULONG pDataLength,
2521  IN PVOID BufferVA,
2522  IN PVOID BufferPA,
2523  IN ULONG BufferLength,
2524  IN USBD_STATUS * pUSBDStatus)
2525 {
2526  DPRINT1("OHCI_StartSendOnePacket: UNIMPLEMENTED. FIXME\n");
2527  return MP_STATUS_SUCCESS;
2528 }
2529 
2530 MPSTATUS
2531 NTAPI
2532 OHCI_EndSendOnePacket(IN PVOID ohciExtension,
2533  IN PVOID PacketParameters,
2534  IN PVOID Data,
2535  IN PULONG pDataLength,
2536  IN PVOID BufferVA,
2537  IN PVOID BufferPA,
2538  IN ULONG BufferLength,
2539  IN USBD_STATUS * pUSBDStatus)
2540 {
2541  DPRINT1("OHCI_EndSendOnePacket: UNIMPLEMENTED. FIXME\n");
2542  return MP_STATUS_SUCCESS;
2543 }
2544 
2545 MPSTATUS
2546 NTAPI
2547 OHCI_PassThru(IN PVOID ohciExtension,
2548  IN PVOID passThruParameters,
2549  IN ULONG ParameterLength,
2550  IN PVOID pParameters)
2551 {
2552  DPRINT1("OHCI_PassThru: UNIMPLEMENTED. FIXME\n");
2553  return MP_STATUS_SUCCESS;
2554 }
2555 
2556 VOID
2557 NTAPI
2558 OHCI_Unload(IN PDRIVER_OBJECT DriverObject)
2559 {
2560 #if DBG
2561  DPRINT1("OHCI_Unload: Not supported\n");
2562 #endif
2563  return;
2564 }
2565 
2566 VOID
2567 NTAPI
2568 OHCI_FlushInterrupts(IN PVOID uhciExtension)
2569 {
2570 #if DBG
2571  DPRINT1("OHCI_FlushInterrupts: Not supported\n");
2572 #endif
2573  return;
2574 }
2575 
2576 NTSTATUS
2577 NTAPI
2578 DriverEntry(IN PDRIVER_OBJECT DriverObject,
2579  IN PUNICODE_STRING RegistryPath)
2580 {
2581  NTSTATUS Status;
2582 
2583  DPRINT_OHCI("DriverEntry: DriverObject - %p, RegistryPath - %wZ\n",
2584  DriverObject,
2585  RegistryPath);
2586 
2587  RtlZeroMemory(&RegPacket, sizeof(USBPORT_REGISTRATION_PACKET));
2588 
2589  RegPacket.MiniPortVersion = USB_MINIPORT_VERSION_OHCI;
2590 
2591  RegPacket.MiniPortFlags = USB_MINIPORT_FLAGS_INTERRUPT |
2592  USB_MINIPORT_FLAGS_MEMORY_IO;
2593 
2594  RegPacket.MiniPortBusBandwidth = TOTAL_USB11_BUS_BANDWIDTH;
2595 
2596  RegPacket.MiniPortExtensionSize = sizeof(OHCI_EXTENSION);
2597  RegPacket.MiniPortEndpointSize = sizeof(OHCI_ENDPOINT);
2598  RegPacket.MiniPortTransferSize = sizeof(OHCI_TRANSFER);
2599  RegPacket.MiniPortResourcesSize = sizeof(OHCI_HC_RESOURCES);
2600 
2601  RegPacket.OpenEndpoint = OHCI_OpenEndpoint;
2602  RegPacket.ReopenEndpoint = OHCI_ReopenEndpoint;
2603  RegPacket.QueryEndpointRequirements = OHCI_QueryEndpointRequirements;
2604  RegPacket.CloseEndpoint = OHCI_CloseEndpoint;
2605  RegPacket.StartController = OHCI_StartController;
2606  RegPacket.StopController = OHCI_StopController;
2607  RegPacket.SuspendController = OHCI_SuspendController;
2608  RegPacket.ResumeController = OHCI_ResumeController;
2609  RegPacket.InterruptService = OHCI_InterruptService;
2610  RegPacket.InterruptDpc = OHCI_InterruptDpc;
2611  RegPacket.SubmitTransfer = OHCI_SubmitTransfer;
2612  RegPacket.SubmitIsoTransfer = OHCI_SubmitIsoTransfer;
2613  RegPacket.AbortTransfer = OHCI_AbortTransfer;
2614  RegPacket.GetEndpointState = OHCI_GetEndpointState;
2615  RegPacket.SetEndpointState = OHCI_SetEndpointState;
2616  RegPacket.PollEndpoint = OHCI_PollEndpoint;
2617  RegPacket.CheckController = OHCI_CheckController;
2618  RegPacket.Get32BitFrameNumber = OHCI_Get32BitFrameNumber;
2619  RegPacket.InterruptNextSOF = OHCI_InterruptNextSOF;
2620  RegPacket.EnableInterrupts = OHCI_EnableInterrupts;
2621  RegPacket.DisableInterrupts = OHCI_DisableInterrupts;
2622  RegPacket.PollController = OHCI_PollController;
2623  RegPacket.SetEndpointDataToggle = OHCI_SetEndpointDataToggle;
2624  RegPacket.GetEndpointStatus = OHCI_GetEndpointStatus;
2625  RegPacket.SetEndpointStatus = OHCI_SetEndpointStatus;
2626  RegPacket.ResetController = OHCI_ResetController;
2627  RegPacket.RH_GetRootHubData = OHCI_RH_GetRootHubData;
2628  RegPacket.RH_GetStatus = OHCI_RH_GetStatus;
2629  RegPacket.RH_GetPortStatus = OHCI_RH_GetPortStatus;
2630  RegPacket.RH_GetHubStatus = OHCI_RH_GetHubStatus;
2631  RegPacket.RH_SetFeaturePortReset = OHCI_RH_SetFeaturePortReset;
2632  RegPacket.RH_SetFeaturePortPower = OHCI_RH_SetFeaturePortPower;
2633  RegPacket.RH_SetFeaturePortEnable = OHCI_RH_SetFeaturePortEnable;
2634  RegPacket.RH_SetFeaturePortSuspend = OHCI_RH_SetFeaturePortSuspend;
2635  RegPacket.RH_ClearFeaturePortEnable = OHCI_RH_ClearFeaturePortEnable;
2636  RegPacket.RH_ClearFeaturePortPower = OHCI_RH_ClearFeaturePortPower;
2637  RegPacket.RH_ClearFeaturePortSuspend = OHCI_RH_ClearFeaturePortSuspend;
2638  RegPacket.RH_ClearFeaturePortEnableChange = OHCI_RH_ClearFeaturePortEnableChange;
2639  RegPacket.RH_ClearFeaturePortConnectChange = OHCI_RH_ClearFeaturePortConnectChange;
2640  RegPacket.RH_ClearFeaturePortResetChange = OHCI_RH_ClearFeaturePortResetChange;
2641  RegPacket.RH_ClearFeaturePortSuspendChange = OHCI_RH_ClearFeaturePortSuspendChange;
2642  RegPacket.RH_ClearFeaturePortOvercurrentChange = OHCI_RH_ClearFeaturePortOvercurrentChange;
2643  RegPacket.RH_DisableIrq = OHCI_RH_DisableIrq;
2644  RegPacket.RH_EnableIrq = OHCI_RH_EnableIrq;
2645  RegPacket.StartSendOnePacket = OHCI_StartSendOnePacket;
2646  RegPacket.EndSendOnePacket = OHCI_EndSendOnePacket;
2647  RegPacket.PassThru = OHCI_PassThru;
2648  RegPacket.FlushInterrupts = OHCI_FlushInterrupts;
2649 
2650  DriverObject->DriverUnload = OHCI_Unload;
2651 
2652  Status = USBPORT_RegisterUSBPortDriver(DriverObject,
2653  USB10_MINIPORT_INTERFACE_VERSION,
2654  &RegPacket);
2655 
2656  DPRINT_OHCI("DriverEntry: USBPORT_RegisterUSBPortDriver return Status - %x\n",
2657  Status);
2658 
2659  return Status;
2660 }
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Definition: usbohci.h:32
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MPSTATUS NTAPI OHCI_RH_ClearFeaturePortEnable(IN PVOID ohciExtension, IN USHORT Port)
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ParameterLength
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struct _OHCI_EXTENSION OHCI_EXTENSION
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Definition: usbohci.h:28
OHCI_MapTransferToTD
ULONG NTAPI OHCI_MapTransferToTD(IN POHCI_EXTENSION OhciExtension, IN ULONG MaxPacketSize, IN OUT ULONG TransferedLen, IN POHCI_TRANSFER OhciTransfer, IN POHCI_HCD_TD TD, IN PUSBPORT_SCATTER_GATHER_LIST SGList)
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OHCI_ENDPOINT_CONTROL EndpointControl
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OHCI_PassThru
MPSTATUS NTAPI OHCI_PassThru(IN PVOID ohciExtension, IN PVOID passThruParameters, IN ULONG ParameterLength, IN PVOID pParameters)
Definition: usbohci.c:2547
OHCI_InitializeED
POHCI_HCD_ED NTAPI OHCI_InitializeED(IN POHCI_ENDPOINT OhciEndpoint, IN POHCI_HCD_ED ED, IN POHCI_HCD_TD FirstTD, IN ULONG_PTR EdPA)
Definition: usbohci.c:166
INTERRUPT_ENDPOINTs
#define INTERRUPT_ENDPOINTs
Definition: usbmport.h:32
_OHCI_OPERATIONAL_REGISTERS
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_Outptr_ PUSB_DEVICE_HANDLE _In_ PUSB_DEVICE_HANDLE _In_ USHORT PortStatus
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_In_ PUCHAR BufferEnd
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_OHCI_REG_COMMAND_STATUS::ControlListFilled
ULONG ControlListFilled
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USBPORT_TRANSFER_TYPE_ISOCHRONOUS
#define USBPORT_TRANSFER_TYPE_ISOCHRONOUS
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Control
static const WCHAR Control[]
Definition: interface.c:27
_OHCI_REG_INTERRUPT_STATUS::RootHubStatusChange
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Definition: hardware.h:190
_USBPORT_ENDPOINT_PROPERTIES
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_OHCI_EXTENSION::HcdFmNumber
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Definition: usbohci.h:152
Status
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OHCI_STATIC_ED_TYPE_INTERRUPT
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OHCI_RH_ClearFeaturePortResetChange
MPSTATUS NTAPI OHCI_RH_ClearFeaturePortResetChange(IN PVOID ohciExtension, IN USHORT Port)
Definition: roothub.c:450
_USBPORT_REGISTRATION_PACKET::StartSendOnePacket
PHCI_START_SEND_ONE_PACKET StartSendOnePacket
Definition: usbmport.h:605
_USBPORT_REGISTRATION_PACKET::PollEndpoint
PHCI_POLL_ENDPOINT PollEndpoint
Definition: usbmport.h:572
_USBPORT_ENDPOINT_PROPERTIES::TotalMaxPacketSize
USHORT TotalMaxPacketSize
Definition: usbmport.h:70
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_OHCI_HCD_ED::HcdEDLink
LIST_ENTRY HcdEDLink
Definition: usbohci.h:87
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PHCI_SET_ENDPOINT_DATA_TOGGLE SetEndpointDataToggle
Definition: usbmport.h:579
_OHCI_STATIC_ED::Link
LIST_ENTRY Link
Definition: usbohci.h:107
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OHCI_InterruptService
BOOLEAN NTAPI OHCI_InterruptService(IN PVOID ohciExtension)
Definition: usbohci.c:1020
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ULONG SetGlobalPower
Definition: hardware.h:261
USBD_SHORT_TRANSFER_OK
#define USBD_SHORT_TRANSFER_OK
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OHCI_REG_FRAME_INTERVAL HcFmInterval
Definition: hardware.h:324
_OHCI_HCCA
Definition: hardware.h:138
_OHCI_TRANSFER::Flags
ULONG Flags
Definition: usbohci.h:139
ENDPOINT_INTERRUPT_16ms
#define ENDPOINT_INTERRUPT_16ms
Definition: usbmport.h:29
_OHCI_REG_CONTROL::HostControllerFunctionalState
ULONG HostControllerFunctionalState
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OHCI_RH_ClearFeaturePortOvercurrentChange
MPSTATUS NTAPI OHCI_RH_ClearFeaturePortOvercurrentChange(IN PVOID ohciExtension, IN USHORT Port)
Definition: roothub.c:508
_OHCI_ENDPOINT_CONTROL
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PHCI_STOP_CONTROLLER StopController
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USBPORT_ENDPOINT_PROPERTIES EndpointProperties
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_OHCI_ENDPOINT_CONTROL::Speed
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Definition: hardware.h:112
_USBPORT_REGISTRATION_PACKET::GetEndpointStatus
PHCI_GET_ENDPOINT_STATUS GetEndpointStatus
Definition: usbmport.h:580
OHCI_HCD_ED_FLAG_RESET_ON_HALT
#define OHCI_HCD_ED_FLAG_RESET_ON_HALT
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_USBPORT_REGISTRATION_PACKET::InterruptNextSOF
PHCI_INTERRUPT_NEXT_SOF InterruptNextSOF
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_OHCI_REG_FRAME_INTERVAL::FrameInterval
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Definition: hardware.h:220
_OHCI_OPERATIONAL_REGISTERS::HcFmNumber
ULONG HcFmNumber
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_USBPORT_REGISTRATION_PACKET::RH_ClearFeaturePortEnable
PHCI_RH_CLEAR_FEATURE_PORT_ENABLE RH_ClearFeaturePortEnable
Definition: usbmport.h:593
USHORT
unsigned short USHORT
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OHCI_MAX_INTERRUPT_TD_COUNT
#define OHCI_MAX_INTERRUPT_TD_COUNT
Definition: usbohci.h:40
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ULONG NTAPI OHCI_GetEndpointState(IN PVOID ohciExtension, IN PVOID ohciEndpoint)
Definition: usbohci.c:1856
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PHCI_SUSPEND_CONTROLLER SuspendController
Definition: usbmport.h:563
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Definition: hardware.h:131
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#define InitializeListHead(ListHead)
Definition: env_spec_w32.h:944
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VOID NTAPI OHCI_PollController(IN PVOID ohciExtension)
Definition: usbohci.c:2334
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#define OHCI_ENDPOINT_ISOCHRONOUS_FORMAT
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Definition: typedefs.h:254
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OHCI_QueryEndpointRequirements
VOID NTAPI OHCI_QueryEndpointRequirements(IN PVOID ohciExtension, IN PUSBPORT_ENDPOINT_PROPERTIES EndpointProperties, IN PUSBPORT_ENDPOINT_REQUIREMENTS EndpointRequirements)
Definition: usbohci.c:467
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Definition: hardware.h:195
PULONG
unsigned int * PULONG
Definition: retypes.h:1
OHCI_EndSendOnePacket
MPSTATUS NTAPI OHCI_EndSendOnePacket(IN PVOID ohciExtension, IN PVOID PacketParameters, IN PVOID Data, IN PULONG pDataLength, IN PVOID BufferVA, IN PVOID BufferPA, IN ULONG BufferLength, IN USBD_STATUS *pUSBDStatus)
Definition: usbohci.c:2532
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Definition: usbmport.h:140
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Definition: usbohci.h:134
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Definition: hardware.h:140
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VOID NTAPI OHCI_FlushInterrupts(IN PVOID uhciExtension)
Definition: usbohci.c:2568
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VOID NTAPI OHCI_RH_DisableIrq(IN PVOID ohciExtension)
Definition: roothub.c:550
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#define USBD_STATUS_HALTED
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PHCI_RH_CLEAR_FEATURE_PORT_CONNECT_CHANGE RH_ClearFeaturePortConnectChange
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_OHCI_REG_FRAME_INTERVAL::AsULONG
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_OHCI_HCD_ED::HwED
OHCI_ENDPOINT_DESCRIPTOR HwED
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#define OHCI_HCD_TD_FLAG_PROCESSED
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MPSTATUS NTAPI OHCI_RH_SetFeaturePortEnable(IN PVOID ohciExtension, IN USHORT Port)
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struct _OHCI_HCD_TD * NextHcdTD
Definition: usbohci.h:69
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Definition: usbohci.c:950
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Definition: typedefs.h:39
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MPSTATUS NTAPI OHCI_RH_ClearFeaturePortConnectChange(IN PVOID ohciExtension, IN USHORT Port)
Definition: roothub.c:421
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Definition: usbmport.h:533
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MPSTATUS NTAPI OHCI_RH_ClearFeaturePortPower(IN PVOID ohciExtension, IN USHORT Port)
Definition: roothub.c:334
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Definition: hardware.h:208
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MPSTATUS NTAPI OHCI_RH_ClearFeaturePortEnableChange(IN PVOID ohciExtension, IN USHORT Port)
Definition: roothub.c:392
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Definition: usbohci.h:62
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PHCI_QUERY_ENDPOINT_REQUIREMENTS QueryEndpointRequirements
Definition: usbmport.h:559
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unsigned int ULONG
Definition: retypes.h:1
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PHCI_RH_ENABLE_IRQ RH_EnableIrq
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PHCI_REOPEN_ENDPOINT ReopenEndpoint
Definition: usbmport.h:558
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Definition: typedefs.h:261
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MPSTATUS NTAPI OHCI_RH_GetStatus(IN PVOID ohciExtension, IN PUSHORT Status)
Definition: roothub.c:103
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#define ULONG_PTR
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