ReactOS 0.4.15-dev-5669-g09dde2c
hardware.h
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1/*
2 * PROJECT: ReactOS USB OHCI Miniport Driver
3 * LICENSE: GPL-2.0+ (https://spdx.org/licenses/GPL-2.0+)
4 * PURPOSE: USBOHCI hardware declarations
5 * COPYRIGHT: Copyright 2017-2018 Vadim Galyant <vgal@rambler.ru>
6 */
7
8#define OHCI_NUMBER_OF_INTERRUPTS 32
9#define OHCI_MAX_PORT_COUNT 15
10#define ED_EOF -1
11#define OHCI_MAXIMUM_OVERHEAD 210 // 5.4 FrameInterval Counter, in bit-times
12#define OHCI_DEFAULT_FRAME_INTERVAL 11999 // 6.3.1 Frame Timing
13#define OHCI_MINIMAL_POTPGT 25 // == 50 ms., PowerOnToPowerGoodTime (HcRhDescriptorA Register)
14
15/* Controller states */
16#define OHCI_HC_STATE_RESET 0
17#define OHCI_HC_STATE_RESUME 1
18#define OHCI_HC_STATE_OPERATIONAL 2
19#define OHCI_HC_STATE_SUSPEND 3
20
21/* Endpoint Descriptor Control */
22#define OHCI_ED_DATA_FLOW_DIRECTION_FROM_TD 0
23#define OHCI_ED_DATA_FLOW_DIRECTION_OUT 1
24#define OHCI_ED_DATA_FLOW_DIRECTION_IN 2
25
26#define OHCI_ENDPOINT_FULL_SPEED 0
27#define OHCI_ENDPOINT_LOW_SPEED 1
28
29#define OHCI_ENDPOINT_GENERAL_FORMAT 0
30#define OHCI_ENDPOINT_ISOCHRONOUS_FORMAT 1
31
32/* Transfer Descriptor Control */
33#define OHCI_TD_INTERRUPT_IMMEDIATE 0
34#define OHCI_TD_INTERRUPT_NONE 7
35
36#define OHCI_TD_DIRECTION_PID_SETUP 0
37#define OHCI_TD_DIRECTION_PID_OUT 1
38#define OHCI_TD_DIRECTION_PID_IN 2
39#define OHCI_TD_DIRECTION_PID_RESERVED 3
40
41#define OHCI_TD_DATA_TOGGLE_FROM_ED 0
42#define OHCI_TD_DATA_TOGGLE_DATA0 2
43#define OHCI_TD_DATA_TOGGLE_DATA1 3
44
45#define OHCI_TD_CONDITION_NO_ERROR 0x00
46#define OHCI_TD_CONDITION_CRC_ERROR 0x01
47#define OHCI_TD_CONDITION_BIT_STUFFING 0x02
48#define OHCI_TD_CONDITION_TOGGLE_MISMATCH 0x03
49#define OHCI_TD_CONDITION_STALL 0x04
50#define OHCI_TD_CONDITION_NO_RESPONSE 0x05
51#define OHCI_TD_CONDITION_PID_CHECK_FAILURE 0x06
52#define OHCI_TD_CONDITION_UNEXPECTED_PID 0x07
53#define OHCI_TD_CONDITION_DATA_OVERRUN 0x08
54#define OHCI_TD_CONDITION_DATA_UNDERRUN 0x09
55#define OHCI_TD_CONDITION_BUFFER_OVERRUN 0x0C
56#define OHCI_TD_CONDITION_BUFFER_UNDERRUN 0x0D
57#define OHCI_TD_CONDITION_NOT_ACCESSED 0x0E
58
60 struct {
68 };
71
73
74typedef struct _OHCI_TRANSFER_DESCRIPTOR { // must be aligned to a 16-byte boundary
76 ULONG CurrentBuffer; // physical address of the next memory location
77 ULONG NextTD; // pointer to the next TD on the list of TDs
78 ULONG BufferEnd; // physical address of the last byte
80
82
84 struct {
91 };
94
96
97typedef struct _OHCI_ISO_TRANSFER_DESCRIPTOR { // must be aligned to a 32-byte boundary
99 ULONG BufferPage0; // physical page number of the 1 byte of the data buffer
100 ULONG NextTD; // pointer to the next Isochronous TD on the queue of Isochronous TDs
101 ULONG BufferEnd; // physical address of the last byte in the buffer
102 USHORT Offset[8]; // for determine size and start addr. iso packet | PacketStatusWord - completion code
104
106
108 struct {
117 };
120
122
123/* Bit flags for HeadPointer member of the EP descriptor */
124#define OHCI_ED_HEAD_POINTER_HALT 0x00000001 // hardware stopped bit
125#define OHCI_ED_HEAD_POINTER_CARRY 0x00000002 // hardware toggle carry bit
126#define OHCI_ED_HEAD_POINTER_MASK 0XFFFFFFF0 // mask physical pointer
127#define OHCI_ED_HEAD_POINTER_FLAGS_MASK 0X0000000F // mask bit flags
128
129typedef struct _OHCI_ENDPOINT_DESCRIPTOR { // must be aligned to a 16-byte boundary
131 ULONG TailPointer; // if TailP and HeadP are different, then the list contains a TD to be processed
132 ULONG HeadPointer; // physical pointer to the next TD to be processed for this endpoint
133 ULONG NextED; // entry points to the next ED on the list
135
137
138typedef struct _OHCI_HCCA { // must be located on a 256-byte boundary
146
147C_ASSERT(sizeof(OHCI_HCCA) == 256);
148
149typedef union _OHCI_REG_CONTROL {
150 struct {
161 };
164
165C_ASSERT(sizeof(OHCI_REG_CONTROL) == sizeof(ULONG));
166
168 struct {
176 };
179
181
183 struct {
194 };
197
199
201 struct {
212 };
215
217
219 struct {
224 };
227
229
231 struct {
240 };
243
245
246typedef union _OHCI_REG_RH_STATUS {
247 union {
248 struct { // read
256 };
257 struct { // write
265 };
266 };
269
271
273 struct {
274 union {
275 struct { // read
285 };
286 struct { // write
296 };
297 };
304 };
307
309
struct _OHCI_TRANSFER_DESCRIPTOR * POHCI_TRANSFER_DESCRIPTOR
struct _OHCI_ISO_TRANSFER_DESCRIPTOR * POHCI_ISO_TRANSFER_DESCRIPTOR
union _OHCI_REG_RH_PORT_STATUS OHCI_REG_RH_PORT_STATUS
struct _OHCI_ISO_TRANSFER_DESCRIPTOR OHCI_ISO_TRANSFER_DESCRIPTOR
struct _OHCI_OPERATIONAL_REGISTERS * POHCI_OPERATIONAL_REGISTERS
union _OHCI_REG_FRAME_INTERVAL OHCI_REG_FRAME_INTERVAL
struct _OHCI_OPERATIONAL_REGISTERS OHCI_OPERATIONAL_REGISTERS
struct _OHCI_TRANSFER_DESCRIPTOR OHCI_TRANSFER_DESCRIPTOR
#define OHCI_MAX_PORT_COUNT
Definition: hardware.h:9
#define OHCI_NUMBER_OF_INTERRUPTS
Definition: hardware.h:8
union _OHCI_ENDPOINT_CONTROL OHCI_ENDPOINT_CONTROL
union _OHCI_TRANSFER_CONTROL OHCI_TRANSFER_CONTROL
union _OHCI_ISO_TRANSFER_CONTROL * POHCI_ISO_TRANSFER_CONTROL
union _OHCI_REG_RH_DESCRIPTORA OHCI_REG_RH_DESCRIPTORA
struct _OHCI_ENDPOINT_DESCRIPTOR * POHCI_ENDPOINT_DESCRIPTOR
union _OHCI_REG_INTERRUPT_ENABLE_DISABLE * POHCI_REG_INTERRUPT_ENABLE_DISABLE
union _OHCI_REG_RH_PORT_STATUS * POHCI_REG_RH_PORT_STATUS
union _OHCI_REG_COMMAND_STATUS * POHCI_REG_COMMAND_STATUS
union _OHCI_ISO_TRANSFER_CONTROL OHCI_ISO_TRANSFER_CONTROL
struct _OHCI_HCCA OHCI_HCCA
union _OHCI_REG_CONTROL OHCI_REG_CONTROL
union _OHCI_REG_COMMAND_STATUS OHCI_REG_COMMAND_STATUS
union _OHCI_REG_CONTROL * POHCI_REG_CONTROL
union _OHCI_REG_INTERRUPT_STATUS OHCI_REG_INTERRUPT_STATUS
union _OHCI_REG_INTERRUPT_STATUS * POHCI_REG_INTERRUPT_STATUS
union _OHCI_ENDPOINT_CONTROL * POHCI_ENDPOINT_CONTROL
union _OHCI_REG_FRAME_INTERVAL * POHCI_REG_FRAME_INTERVAL
union _OHCI_REG_RH_STATUS * POHCI_REG_RH_STATUS
union _OHCI_REG_RH_DESCRIPTORA * POHCI_REG_RH_DESCRIPTORA
struct _OHCI_HCCA * POHCI_HCCA
struct _OHCI_ENDPOINT_DESCRIPTOR OHCI_ENDPOINT_DESCRIPTOR
union _OHCI_REG_RH_STATUS OHCI_REG_RH_STATUS
union _OHCI_REG_INTERRUPT_ENABLE_DISABLE OHCI_REG_INTERRUPT_ENABLE_DISABLE
union _OHCI_TRANSFER_CONTROL * POHCI_TRANSFER_CONTROL
#define C_ASSERT(e)
Definition: intsafe.h:73
_In_ ULONG _In_ ULONG Offset
Definition: ntddpcm.h:101
unsigned short USHORT
Definition: pedump.c:61
OHCI_ENDPOINT_CONTROL EndpointControl
Definition: hardware.h:130
USHORT FrameNumber
Definition: hardware.h:140
UCHAR Pad[4]
Definition: hardware.h:144
ULONG DoneHead
Definition: hardware.h:142
USHORT Pad1
Definition: hardware.h:141
ULONG InterrruptTable[OHCI_NUMBER_OF_INTERRUPTS]
Definition: hardware.h:139
UCHAR reserved_hc[116]
Definition: hardware.h:143
OHCI_ISO_TRANSFER_CONTROL Control
Definition: hardware.h:98
OHCI_REG_INTERRUPT_STATUS HcInterruptStatus
Definition: hardware.h:314
OHCI_REG_COMMAND_STATUS HcCommandStatus
Definition: hardware.h:313
OHCI_REG_CONTROL HcControl
Definition: hardware.h:312
OHCI_REG_RH_DESCRIPTORA HcRhDescriptorA
Definition: hardware.h:329
OHCI_REG_INTERRUPT_ENABLE_DISABLE HcInterruptEnable
Definition: hardware.h:315
OHCI_REG_INTERRUPT_ENABLE_DISABLE HcInterruptDisable
Definition: hardware.h:316
OHCI_REG_RH_STATUS HcRhStatus
Definition: hardware.h:331
OHCI_REG_RH_PORT_STATUS HcRhPortStatus[OHCI_MAX_PORT_COUNT]
Definition: hardware.h:332
OHCI_REG_FRAME_INTERVAL HcFmInterval
Definition: hardware.h:324
OHCI_TRANSFER_CONTROL Control
Definition: hardware.h:75
uint32_t ULONG
Definition: typedefs.h:59
ULONG ControlBulkServiceRatio
Definition: hardware.h:151
ULONG PeriodicListEnable
Definition: hardware.h:152
ULONG HostControllerFunctionalState
Definition: hardware.h:156
ULONG BulkListEnable
Definition: hardware.h:155
ULONG ControlListEnable
Definition: hardware.h:154
ULONG IsochronousEnable
Definition: hardware.h:153
ULONG InterruptRouting
Definition: hardware.h:157
ULONG RemoteWakeupConnected
Definition: hardware.h:158
ULONG RemoteWakeupEnable
Definition: hardware.h:159
USHORT PortOverCurrentIndicatorChange
Definition: hardware.h:301
USHORT PortOverCurrentIndicator
Definition: hardware.h:279
USHORT PortSuspendStatusChange
Definition: hardware.h:300
ULONG SetRemoteWakeupEnable
Definition: hardware.h:260
ULONG ClearGlobalPower
Definition: hardware.h:258
ULONG OverCurrentIndicatorChangeR
Definition: hardware.h:254
ULONG ClearRemoteWakeupEnable
Definition: hardware.h:264
ULONG DeviceRemoteWakeupEnable
Definition: hardware.h:252
ULONG LocalPowerStatusChange
Definition: hardware.h:253
ULONG OverCurrentIndicatorChangeW
Definition: hardware.h:262
ULONG LocalPowerStatus
Definition: hardware.h:249
ULONG OverCurrentIndicator
Definition: hardware.h:250
unsigned char UCHAR
Definition: xmlstorage.h:181