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Classes
struct	_INITIALIZATION_BLOCK

struct	_RECEIVE_DESCRIPTOR

struct	_TRANSMIT_DESCRIPTOR

Macros
#define	MASK16(__x__) ((__x__) & 0x0000ffff)

#define	NUMBER_OF_PORTS 0x20 /* number of i/o ports the board requires */

#define	RDP 0x10 /* same address in 16-bit and 32-bit IO mode */

#define	RAP16 0x12

#define	RESET16 0x14

#define	BDP16 0x16

#define	RAP32 0x14

#define	RESET32 0x18

#define	BDP32 0x1c

#define	RAP RAP16

#define	BDP BDP16

#define	PCI_ID 0x20001022

#define	VEN_ID 0x1022

#define	DEV_ID 0x2000

#define	SW_STYLE_0 0

#define	SW_STYLE_1 1

#define	SW_STYLE_2 2

#define	SW_STYLE_3 3

#define	CSR0 0x0 /* controller status register */

#define	CSR1 0x1 /* init block address 0 */

#define	CSR2 0x2 /* init block address 1 */

#define	CSR3 0x3 /* interrupt masks and deferral control */

#define	CSR4 0x4 /* test and features control */

#define	CSR5 0x5 /* extended control and interrupt */

#define	CSR6 0x6 /* rx/tx descriptor table length */

#define	CSR8 0x8 /* logical address filter 0 */

#define	CSR9 0x9 /* logical address filter 1 */

#define	CSR10 0xa /* logical address filter 2 */

#define	CSR11 0xb /* logical address filter 3 */

#define	CSR12 0xc /* physical address register 0 */

#define	CSR13 0xd /* physical address register 1 */

#define	CSR14 0xe /* physical address register 2 */

#define	CSR15 0xf /* Mode */

#define	CSR16 0x10 /* initialization block address lower */

#define	CSR17 0x11 /* initialization block address upper */

#define	CSR18 0x12 /* current receive buffer address lower */

#define	CSR19 0x13 /* current receive buffer address upper */

#define	CSR20 0x14 /* current transmit buffer address lower */

#define	CSR21 0x15 /* current transmit buffer address upper */

#define	CSR22 0x16 /* next receive buffer address lower */

#define	CSR23 0x17 /* next receive buffer address upper */

#define	CSR24 0x18 /* base address of receive descriptor ring lower */

#define	CSR25 0x19 /* base address of receive descriptor ring upper */

#define	CSR26 0x1a /* next receive descriptor address lower */

#define	CSR27 0x1b /* next receive descriptor address upper */

#define	CSR28 0x1c /* current receive descriptor address lower */

#define	CSR29 0x1d /* current receive descriptor address upper */

#define	CSR30 0x1e /* base address of transmit descriptor ring lower */

#define	CSR31 0x1f /* base address of transmit descriptor ring upper */

#define	CSR32 0x20 /* next transmit descriptor address lower */

#define	CSR33 0x21 /* next transmit descriptor address upper */

#define	CSR34 0x22 /* current transmit descriptor address lower */

#define	CSR35 0x23 /* current transmit descriptor address upper */

#define	CSR36 0x24 /* next next receive descriptor address lower */

#define	CSR37 0x25 /* next next receive descriptor address upper */

#define	CSR38 0x26 /* next next transmit descriptor address lower */

#define	CSR39 0x27 /* next next transmit descriptor address upper */

#define	CSR40 0x28 /* current receive byte count */

#define	CSR41 0x29 /* current receive status */

#define	CSR42 0x2a /* current transmit byte count */

#define	CSR43 0x2b /* current transmit status */

#define	CSR44 0x2c /* next receive byte count */

#define	CSR45 0x2d /* next receive status */

#define	CSR46 0x2e /* poll time counter */

#define	CSR47 0x2f /* polling interval */

#define	CSR58 0x3a /* software style */

#define	CSR60 0x3c /* previous transmit descriptor address lower */

#define	CSR61 0x3d /* previous transmit descriptor address upper */

#define	CSR62 0x3e /* previous transmit byte count */

#define	CSR63 0x3f /* previous transmit status */

#define	CSR64 0x40 /* next transmit buffer address lower */

#define	CSR65 0x41 /* next transmit buffer address upper */

#define	CSR66 0x42 /* next transmit byte count */

#define	CSR67 0x43 /* next transmit status */

#define	CSR72 0x48 /* receive descriptor ring counter */

#define	CSR74 0x4a /* transmit descriptor ring counter */

#define	CSR76 0x4c /* receive descriptor ring length */

#define	CSR78 0x4e /* transmit descriptor ring length */

#define	CSR80 0x50 /* dma transfer counter and fifo watermark control */

#define	CSR82 0x52 /* bus activity timer */

#define	CSR84 0x54 /* dma address register lower */

#define	CSR85 0x55 /* dma address register upper */

#define	CSR86 0x56 /* buffer byte counter */

#define	CSR88 0x58 /* chip id register lower */

#define	CSR89 0x59 /* chip id register upper */

#define	CSR94 0x5e /* transmit time domain reflectometry count */

#define	CSR100 0x64 /* bus timeout */

#define	CSR112 0x70 /* missed frame count */

#define	CSR114 0x72 /* receive collision count */

#define	CSR122 0x7a /* advanced feature control */

#define	CSR124 0x7c /* test register control */

#define	BCR2 0x2 /* miscellaneous configuration */

#define	BCR4 0x4 /* link status led */

#define	BCR5 0x5 /* led1 status */

#define	BCR6 0x6 /* led2 status */

#define	BCR7 0x7 /* led3 status */

#define	BCR9 0x9 /* full-duplex control */

#define	BCR16 0x10 /* i/o base address lower */

#define	BCR17 0x11 /* i/o base address upper */

#define	BCR18 0x12 /* burst and bus control register */

#define	BCR19 0x13 /* eeprom control and status */

#define	BCR20 0x14 /* software style */

#define	BCR21 0x15 /* interrupt control */

#define	BCR22 0x16 /* pci latency register */

#define	CSR0_INIT 0x1 /* read initialization block */

#define	CSR0_STRT 0x2 /* start the chip */

#define	CSR0_STOP 0x4 /* stop the chip */

#define	CSR0_TDMD 0x8 /* transmit demand */

#define	CSR0_TXON 0x10 /* transmit on */

#define	CSR0_RXON 0x20 /* receive on */

#define	CSR0_IENA 0x40 /* interrupt enabled */

#define	CSR0_INTR 0x80 /* interrupting */

#define	CSR0_IDON 0x100 /* initialization done */

#define	CSR0_TINT 0x200 /* transmit interrupt */

#define	CSR0_RINT 0x400 /* receive interrupt */

#define	CSR0_MERR 0x800 /* memory error */

#define	CSR0_MISS 0x1000 /* missed frame */

#define	CSR0_CERR 0x2000 /* collision error */

#define	CSR0_BABL 0x4000 /* babble */

#define	CSR0_ERR 0x8000 /* error */

#define	CSR3_BSWP 0x4 /* byte swap */

#define	CSR3_EMBA 0x8 /* enable modified backoff algorithm */

#define	CSR3_DXMT2PD 0x10 /* disable transmit two-part deferral */

#define	CSR3_LAPPEN 0x20 /* lookahead packet processing enable */

#define	CSR3_DXSUFLO 0x40 /* disable transmit stop on underflow */

#define	CSR3_IDONM 0x100 /* initialization done mask */

#define	CSR3_TINTM 0x200 /* transmit interrupt mask */

#define	CSR3_RINTM 0x400 /* receive interrupt mask */

#define	CSR3_MERRM 0x800 /* memory error interrupt mask */

#define	CSR3_MISSM 0x1000 /* missed frame interrupt mask */

#define	CSR3_BABLM 0x4000 /* babble interrupt mask */

#define	CSR4_JABM 0x1 /* jabber interrupt mask */

#define	CSR4_JAB 0x2 /* interrupt on jabber error */

#define	CSR4_TXSTRTM 0x4 /* transmit start interrupt mask */

#define	CSR4_TXSTRT 0x8 /* interrupt on transmit start */

#define	CSR4_RCVCCOM 0x10 /* receive collision counter overflow mask */

#define	CSR4_RCVCCO 0X20 /* interrupt on receive collision counter overflow */

#define	CSR4_UINT 0x40 /* user interrupt */

#define	CSR4_UINTCMD 0x80 /* user interrupt command */

#define	CSR4_MFCOM 0x100 /* missed frame counter overflow mask */

#define	CSR4_MFCO 0x200 /* interrupt on missed frame counter overflow */

#define	CSR4_ASTRP_RCV 0x400 /* auto pad strip on receive */

#define	CSR4_APAD_XMT 0x800 /* auto pad on transmit */

#define	CSR4_DPOLL 0x1000 /* disable transmit polling */

#define	CSR4_TIMER 0x2000 /* enable bus activity timer */

#define	CSR4_DMAPLUS 0x4000 /* set to 1 for pci */

#define	CSR4_EN124 0x8000 /* enable CSR124 access */

#define	CSR5_SPND 0x1 /* suspend */

#define	CSR5_MPMODE 0x2 /* magic packet mode */

#define	CSR5_MPEN 0x4 /* magic packet enable */

#define	CSR5_MPINTE 0x8 /* magic packet interrupt enable */

#define	CSR5_MPINT 0x10 /* magic packet interrupt */

#define	CSR5_MPPLBA 0x20 /* magic packet physical logical broadcast accept */

#define	CSR5_EXDINTE 0x40 /* excessive deferral interrupt enable */

#define	CSR5_EXDINT 0x80 /* excessive deferral interrupt */

#define	CSR5_SLPINTE 0x100 /* sleep interrupt enable */

#define	CSR5_SLPINT 0x200 /* sleep interrupt */

#define	CSR5_SINE 0x400 /* system interrupt enable */

#define	CSR5_SINT 0x800 /* system interrupt */

#define	CSR5_LTINTEN 0x4000 /* last transmit interrupt enable */

#define	CSR5_TOKINTD 0x8000 /* transmit ok interrupt disable */

#define	CSR15_DRX 0x1 /* disable receiver */

#define	CSR15_DTX 0x2 /* disable transmitter */

#define	CSR15_LOOP 0x4 /* loopback enable */

#define	CSR15_DXMTFCS 0x8 /* disable transmit fcs */

#define	CSR15_FCOLL 0x10 /* force collision */

#define	CSR15_DRTY 0x20 /* disable retry */

#define	CSR15_INTL 0x40 /* internal loopback */

#define	CSR15_PORTSEL0 0x80 /* port selection bit 0 */

#define	CSR15_PORTSEL1 0x100 /* port selection bit 1 */

#define	CSR15_LRT 0x200 /* low receive threshold - same as TSEL */

#define	CSR15_TSEL 0x200 /* transmit mode select - same as LRT */

#define	CSR15_MENDECL 0x400 /* mendec loopback mode */

#define	CSR15_DAPC 0x800 /* disable automatic parity correction */

#define	CSR15_DLNKTST 0x1000 /* disable link status */

#define	CSR15_DRCVPA 0x2000 /* disable receive physical address */

#define	CSR15_DRCVBC 0x4000 /* disable receive broadcast */

#define	CSR15_PROM 0x8000 /* promiscuous mode */

#define	CSR58_SSIZE32 0x100 /* 32-bit software size */

#define	CSR58_CSRPCNET 0x200 /* csr pcnet-isa configuration */

#define	CSR58_APERREN 0x400 /* advanced parity error handling enable */

#define	CSR124_RPA 0x4 /* runt packet accept */

#define	BCR2_ASEL 0x2 /* auto-select media */

#define	BCR2_AWAKE 0x4 /* select sleep mode */

#define	BCR2_EADISEL 0x8 /* eadi select */

#define	BCR2_DXCVRPOL 0x10 /* dxcvr polarity */

#define	BCR2_DXCVRCTL 0x20 /* dxcvr control */

#define	BCR2_INTLEVEL 0x80 /* interrupt level/edge */

#define	BCR2_APROMWE 0x100 /* address prom write enable */

#define	BCR2_LEDPE 0x1000 /* LED programming enable */

#define	BCR2_TMAULOOP 0x4000 /* t-mau transmit on loopback */

#define	BCR4_COLE 0x1 /* collision status enable */

#define	BCR4_JABE 0x2 /* jabber status enable */

#define	BCR4_RCVE 0x4 /* receive status enable */

#define	BCR4_RXPOLE 0x8 /* receive polarity status enable */

#define	BCR4_XMTE 0x10 /* transmit status enable */

#define	BCR4_RCVME 0x20 /* receive match status enable */

#define	BCR4_LNKSTE 0x40 /* link status enable */

#define	BCR4_PSE 0x80 /* pulse stretcher enable */

#define	BCR4_FDLSE 0x100 /* full-duplex link status enable */

#define	BCR4_MPSE 0x200 /* magic packet status enable */

#define	BCR4_E100 0x1000 /* link speed */

#define	BCR4_LEDDIS 0x2000 /* led disable */

#define	BCR4_LEDPOL 0x4000 /* led polarity */

#define	BCR4_LEDOUT 0x8000 /* led output pin value */

#define	BCR5_COLE 0x1 /* collision status enable */

#define	BCR5_JABE 0x2 /* jabber status enable */

#define	BCR5_RCVE 0x4 /* receive status enable */

#define	BCR5_RXPOLE 0x8 /* receive polarity status enable */

#define	BCR5_XMTE 0x10 /* transmit status enable */

#define	BCR5_RCVME 0x20 /* receive match status enable */

#define	BCR5_LNKSTE 0x40 /* link status enable */

#define	BCR5_PSE 0x80 /* pulse stretcher enable */

#define	BCR5_FDLSE 0x100 /* full-duplex link status enable */

#define	BCR5_MPSE 0x200 /* magic packet status enable */

#define	BCR5_E100 0x1000 /* link speed */

#define	BCR5_LEDDIS 0x2000 /* led disable */

#define	BCR5_LEDPOL 0x4000 /* led polarity */

#define	BCR5_LEDOUT 0x8000 /* led output pin value */

#define	BCR6_COLE 0x1 /* collision status enable */

#define	BCR6_JABE 0x2 /* jabber status enable */

#define	BCR6_RCVE 0x4 /* receive status enable */

#define	BCR6_RXPOLE 0x8 /* receive polarity status enable */

#define	BCR6_XMTE 0x10 /* transmit status enable */

#define	BCR6_RCVME 0x20 /* receive match status enable */

#define	BCR6_LNKSTE 0x40 /* link status enable */

#define	BCR6_PSE 0x80 /* pulse stretcher enable */

#define	BCR6_FDLSE 0x100 /* full-duplex link status enable */

#define	BCR6_MPSE 0x200 /* magic packet status enable */

#define	BCR6_E100 0x1000 /* link speed */

#define	BCR6_LEDDIS 0x2000 /* led disable */

#define	BCR6_LEDPOL 0x4000 /* led polarity */

#define	BCR6_LEDOUT 0x8000 /* led output pin value */

#define	BCR7_COLE 0x1 /* collision status enable */

#define	BCR7_JABE 0x2 /* jabber status enable */

#define	BCR7_RCVE 0x4 /* receive status enable */

#define	BCR7_RXPOLE 0x8 /* receive polarity status enable */

#define	BCR7_XMTE 0x10 /* transmit status enable */

#define	BCR7_RCVME 0x20 /* receive match status enable */

#define	BCR7_LNKSTE 0x40 /* link status enable */

#define	BCR7_PSE 0x80 /* pulse stretcher enable */

#define	BCR7_FDLSE 0x100 /* full-duplex link status enable */

#define	BCR7_MPSE 0x200 /* magic packet status enable */

#define	BCR7_E100 0x1000 /* link speed */

#define	BCR7_LEDDIS 0x2000 /* led disable */

#define	BCR7_LEDPOL 0x4000 /* led polarity */

#define	BCR7_LEDOUT 0x8000 /* led output pin value */

#define	BCR9_FDEN 0x1 /* full-duplex enable */

#define	BCR9_AUIFD 0x2 /* aui full-duplex */

#define	BCR9_FDRPAD 0x4 /* full-duplex runt packet accept disable */

#define	BCR18_BWRITE 0x20 /* burst write enable */

#define	BCR18_BREADE 0x40 /* burst read enable */

#define	BCR18_DWIO 0x80 /* dword i/o enable */

#define	BCR18_EXTREQ 0x100 /* extended request */

#define	BCR18_MEMCMD 0x200 /* memory command */

#define	BCR19_EDI 0x1 /* eeprom data in - same as EDO */

#define	BCR19_ED0 0x1 /* eeprom data out - same as EDI */

#define	BCR19_ESK 0x2 /* eeprom serial clock */

#define	BCR19_ECS 0x4 /* eeprom chip select */

#define	BCR19_EEN 0x8 /* eeprom port enable */

#define	BCR19_EEDET 0x2000 /* eeprom detect */

#define	BCR19_PREAD 0x4000 /* eeprom read */

#define	BCR19_PVALID 0x8000 /* eeprom valid */

#define	BCR20_SSIZE32 0x100 /* 32-bit software size */

#define	BCR20_CSRPCNET 0x200 /* csr pcnet-isa configuration */

#define	BCR20_APERREN 0x400 /* advanced parity error handling enable */

#define	RD_BAM 0x10 /* broadcast address match */

#define	RD_LAFM 0x20 /* logical address filter match */

#define	RD_PAM 0x40 /* physical address match */

#define	RD_BPE 0x80 /* bus parity error */

#define	RD_ENP 0x100 /* end of packet */

#define	RD_STP 0x200 /* start of packet */

#define	RD_BUFF 0x400 /* buffer error */

#define	RD_CRC 0x800 /* crc error */

#define	RD_OFLO 0x1000 /* overflow error */

#define	RD_FRAM 0x2000 /* framing error */

#define	RD_ERR 0x4000 /* an error bit is set */

#define	RD_OWN 0x8000 /* buffer ownership (0=host, 1=nic) */

#define	TD1_BPE 0x80 /* bus parity error */

#define	TD1_ENP 0x100 /* end of packet */

#define	TD1_STP 0x200 /* start of packet */

#define	TD1_DEF 0x400 /* frame transmission deferred */

#define	TD1_ONE 0x800 /* exactly one retry was needed for transmission */

#define	TD1_MORE 0x1000 /* more than 1 transmission retry required - same as LTINT */

#define	TD1_LTINT 0x1000 /* suppress transmit success interrupt - same as MORE */

#define	TD1_ADD_FCS 0x2000 /* force fcs generation - same as NO_FCS */

#define	TD1_NO_FCS 0x2000 /* prevent fcs generation - same as ADD_FCS */

#define	TD1_ERR 0x4000 /* an error bit is set */

#define	TD1_OWN 0x8000 /* buffer ownership */

#define	TD2_RTRY 0x400 /* retry error */

#define	TD2_LCAR 0x800 /* loss of carrier */

#define	TD2_LCOL 0x1000 /* late collision */

#define	TD2_EXDEF 0x2000 /* excessive deferral */

#define	TD2_UFLO 0x4000 /* buffer underflow */

#define	TD2_BUFF 0x8000 /* buffer error */

Typedefs
typedef struct _INITIALIZATION_BLOCK	INITIALIZATION_BLOCK

typedef struct _INITIALIZATION_BLOCK *	PINITIALIZATION_BLOCK

typedef struct _RECEIVE_DESCRIPTOR	RECEIVE_DESCRIPTOR

typedef struct _RECEIVE_DESCRIPTOR *	PRECEIVE_DESCRIPTOR

typedef struct _TRANSMIT_DESCRIPTOR	TRANSMIT_DESCRIPTOR

typedef struct _TRANSMIT_DESCRIPTOR *	PTRANSMIT_DESCRIPTOR

Macro Definition Documentation

◆ BCR16

#define BCR16 0x10 /* i/o base address lower */

Definition at line 144 of file pcnethw.h.

◆ BCR17

#define BCR17 0x11 /* i/o base address upper */

Definition at line 145 of file pcnethw.h.

◆ BCR18

#define BCR18 0x12 /* burst and bus control register */

Definition at line 146 of file pcnethw.h.

◆ BCR18_BREADE

#define BCR18_BREADE 0x40 /* burst read enable */

Definition at line 326 of file pcnethw.h.

◆ BCR18_BWRITE

#define BCR18_BWRITE 0x20 /* burst write enable */

Definition at line 325 of file pcnethw.h.

◆ BCR18_DWIO

#define BCR18_DWIO 0x80 /* dword i/o enable */

Definition at line 327 of file pcnethw.h.

◆ BCR18_EXTREQ

#define BCR18_EXTREQ 0x100 /* extended request */

Definition at line 328 of file pcnethw.h.

◆ BCR18_MEMCMD

#define BCR18_MEMCMD 0x200 /* memory command */

Definition at line 329 of file pcnethw.h.

◆ BCR19

#define BCR19 0x13 /* eeprom control and status */

Definition at line 147 of file pcnethw.h.

◆ BCR19_ECS

#define BCR19_ECS 0x4 /* eeprom chip select */

Definition at line 335 of file pcnethw.h.

◆ BCR19_ED0

#define BCR19_ED0 0x1 /* eeprom data out - same as EDI */

Definition at line 333 of file pcnethw.h.

◆ BCR19_EDI

#define BCR19_EDI 0x1 /* eeprom data in - same as EDO */

Definition at line 332 of file pcnethw.h.

◆ BCR19_EEDET

#define BCR19_EEDET 0x2000 /* eeprom detect */

Definition at line 337 of file pcnethw.h.

◆ BCR19_EEN

#define BCR19_EEN 0x8 /* eeprom port enable */

Definition at line 336 of file pcnethw.h.

◆ BCR19_ESK

#define BCR19_ESK 0x2 /* eeprom serial clock */

Definition at line 334 of file pcnethw.h.

◆ BCR19_PREAD

#define BCR19_PREAD 0x4000 /* eeprom read */

Definition at line 338 of file pcnethw.h.

◆ BCR19_PVALID

#define BCR19_PVALID 0x8000 /* eeprom valid */

Definition at line 339 of file pcnethw.h.

◆ BCR2

#define BCR2 0x2 /* miscellaneous configuration */

Definition at line 138 of file pcnethw.h.

◆ BCR20

#define BCR20 0x14 /* software style */

Definition at line 148 of file pcnethw.h.

◆ BCR20_APERREN

#define BCR20_APERREN 0x400 /* advanced parity error handling enable */

Definition at line 344 of file pcnethw.h.

◆ BCR20_CSRPCNET

#define BCR20_CSRPCNET 0x200 /* csr pcnet-isa configuration */

Definition at line 343 of file pcnethw.h.

◆ BCR20_SSIZE32

#define BCR20_SSIZE32 0x100 /* 32-bit software size */

Definition at line 342 of file pcnethw.h.

◆ BCR21

#define BCR21 0x15 /* interrupt control */

Definition at line 149 of file pcnethw.h.

◆ BCR22

#define BCR22 0x16 /* pci latency register */

Definition at line 150 of file pcnethw.h.

◆ BCR2_APROMWE

#define BCR2_APROMWE 0x100 /* address prom write enable */

Definition at line 251 of file pcnethw.h.

◆ BCR2_ASEL

#define BCR2_ASEL 0x2 /* auto-select media */

Definition at line 245 of file pcnethw.h.

◆ BCR2_AWAKE

#define BCR2_AWAKE 0x4 /* select sleep mode */

Definition at line 246 of file pcnethw.h.

◆ BCR2_DXCVRCTL

#define BCR2_DXCVRCTL 0x20 /* dxcvr control */

Definition at line 249 of file pcnethw.h.

◆ BCR2_DXCVRPOL

#define BCR2_DXCVRPOL 0x10 /* dxcvr polarity */

Definition at line 248 of file pcnethw.h.

◆ BCR2_EADISEL

#define BCR2_EADISEL 0x8 /* eadi select */

Definition at line 247 of file pcnethw.h.

◆ BCR2_INTLEVEL

#define BCR2_INTLEVEL 0x80 /* interrupt level/edge */

Definition at line 250 of file pcnethw.h.

◆ BCR2_LEDPE

#define BCR2_LEDPE 0x1000 /* LED programming enable */

Definition at line 252 of file pcnethw.h.

◆ BCR2_TMAULOOP

#define BCR2_TMAULOOP 0x4000 /* t-mau transmit on loopback */

Definition at line 253 of file pcnethw.h.

◆ BCR4

#define BCR4 0x4 /* link status led */

Definition at line 139 of file pcnethw.h.

◆ BCR4_COLE

#define BCR4_COLE 0x1 /* collision status enable */

Definition at line 256 of file pcnethw.h.

◆ BCR4_E100

#define BCR4_E100 0x1000 /* link speed */

Definition at line 266 of file pcnethw.h.

◆ BCR4_FDLSE

#define BCR4_FDLSE 0x100 /* full-duplex link status enable */

Definition at line 264 of file pcnethw.h.

◆ BCR4_JABE

#define BCR4_JABE 0x2 /* jabber status enable */

Definition at line 257 of file pcnethw.h.

◆ BCR4_LEDDIS

#define BCR4_LEDDIS 0x2000 /* led disable */

Definition at line 267 of file pcnethw.h.

◆ BCR4_LEDOUT

#define BCR4_LEDOUT 0x8000 /* led output pin value */

Definition at line 269 of file pcnethw.h.

◆ BCR4_LEDPOL

#define BCR4_LEDPOL 0x4000 /* led polarity */

Definition at line 268 of file pcnethw.h.

◆ BCR4_LNKSTE

#define BCR4_LNKSTE 0x40 /* link status enable */

Definition at line 262 of file pcnethw.h.

◆ BCR4_MPSE

#define BCR4_MPSE 0x200 /* magic packet status enable */

Definition at line 265 of file pcnethw.h.

◆ BCR4_PSE

#define BCR4_PSE 0x80 /* pulse stretcher enable */

Definition at line 263 of file pcnethw.h.

◆ BCR4_RCVE

#define BCR4_RCVE 0x4 /* receive status enable */

Definition at line 258 of file pcnethw.h.

◆ BCR4_RCVME

#define BCR4_RCVME 0x20 /* receive match status enable */

Definition at line 261 of file pcnethw.h.

◆ BCR4_RXPOLE

#define BCR4_RXPOLE 0x8 /* receive polarity status enable */

Definition at line 259 of file pcnethw.h.

◆ BCR4_XMTE

#define BCR4_XMTE 0x10 /* transmit status enable */

Definition at line 260 of file pcnethw.h.

◆ BCR5

#define BCR5 0x5 /* led1 status */

Definition at line 140 of file pcnethw.h.

◆ BCR5_COLE

#define BCR5_COLE 0x1 /* collision status enable */

Definition at line 272 of file pcnethw.h.

◆ BCR5_E100

#define BCR5_E100 0x1000 /* link speed */

Definition at line 282 of file pcnethw.h.

◆ BCR5_FDLSE

#define BCR5_FDLSE 0x100 /* full-duplex link status enable */

Definition at line 280 of file pcnethw.h.

◆ BCR5_JABE

#define BCR5_JABE 0x2 /* jabber status enable */

Definition at line 273 of file pcnethw.h.

◆ BCR5_LEDDIS

#define BCR5_LEDDIS 0x2000 /* led disable */

Definition at line 283 of file pcnethw.h.

◆ BCR5_LEDOUT

#define BCR5_LEDOUT 0x8000 /* led output pin value */

Definition at line 285 of file pcnethw.h.

◆ BCR5_LEDPOL

#define BCR5_LEDPOL 0x4000 /* led polarity */

Definition at line 284 of file pcnethw.h.

◆ BCR5_LNKSTE

#define BCR5_LNKSTE 0x40 /* link status enable */

Definition at line 278 of file pcnethw.h.

◆ BCR5_MPSE

#define BCR5_MPSE 0x200 /* magic packet status enable */

Definition at line 281 of file pcnethw.h.

◆ BCR5_PSE

#define BCR5_PSE 0x80 /* pulse stretcher enable */

Definition at line 279 of file pcnethw.h.

◆ BCR5_RCVE

#define BCR5_RCVE 0x4 /* receive status enable */

Definition at line 274 of file pcnethw.h.

◆ BCR5_RCVME

#define BCR5_RCVME 0x20 /* receive match status enable */

Definition at line 277 of file pcnethw.h.

◆ BCR5_RXPOLE

#define BCR5_RXPOLE 0x8 /* receive polarity status enable */

Definition at line 275 of file pcnethw.h.

◆ BCR5_XMTE

#define BCR5_XMTE 0x10 /* transmit status enable */

Definition at line 276 of file pcnethw.h.

◆ BCR6

#define BCR6 0x6 /* led2 status */

Definition at line 141 of file pcnethw.h.

◆ BCR6_COLE

#define BCR6_COLE 0x1 /* collision status enable */

Definition at line 288 of file pcnethw.h.

◆ BCR6_E100

#define BCR6_E100 0x1000 /* link speed */

Definition at line 298 of file pcnethw.h.

◆ BCR6_FDLSE

#define BCR6_FDLSE 0x100 /* full-duplex link status enable */

Definition at line 296 of file pcnethw.h.

◆ BCR6_JABE

#define BCR6_JABE 0x2 /* jabber status enable */

Definition at line 289 of file pcnethw.h.

◆ BCR6_LEDDIS

#define BCR6_LEDDIS 0x2000 /* led disable */

Definition at line 299 of file pcnethw.h.

◆ BCR6_LEDOUT

#define BCR6_LEDOUT 0x8000 /* led output pin value */

Definition at line 301 of file pcnethw.h.

◆ BCR6_LEDPOL

#define BCR6_LEDPOL 0x4000 /* led polarity */

Definition at line 300 of file pcnethw.h.

◆ BCR6_LNKSTE

#define BCR6_LNKSTE 0x40 /* link status enable */

Definition at line 294 of file pcnethw.h.

◆ BCR6_MPSE

#define BCR6_MPSE 0x200 /* magic packet status enable */

Definition at line 297 of file pcnethw.h.

◆ BCR6_PSE

#define BCR6_PSE 0x80 /* pulse stretcher enable */

Definition at line 295 of file pcnethw.h.

◆ BCR6_RCVE

#define BCR6_RCVE 0x4 /* receive status enable */

Definition at line 290 of file pcnethw.h.

◆ BCR6_RCVME

#define BCR6_RCVME 0x20 /* receive match status enable */

Definition at line 293 of file pcnethw.h.

◆ BCR6_RXPOLE

#define BCR6_RXPOLE 0x8 /* receive polarity status enable */

Definition at line 291 of file pcnethw.h.

◆ BCR6_XMTE

#define BCR6_XMTE 0x10 /* transmit status enable */

Definition at line 292 of file pcnethw.h.

◆ BCR7

#define BCR7 0x7 /* led3 status */

Definition at line 142 of file pcnethw.h.

◆ BCR7_COLE

#define BCR7_COLE 0x1 /* collision status enable */

Definition at line 304 of file pcnethw.h.

◆ BCR7_E100

#define BCR7_E100 0x1000 /* link speed */

Definition at line 314 of file pcnethw.h.

◆ BCR7_FDLSE

#define BCR7_FDLSE 0x100 /* full-duplex link status enable */

Definition at line 312 of file pcnethw.h.

◆ BCR7_JABE

#define BCR7_JABE 0x2 /* jabber status enable */

Definition at line 305 of file pcnethw.h.

◆ BCR7_LEDDIS

#define BCR7_LEDDIS 0x2000 /* led disable */

Definition at line 315 of file pcnethw.h.

◆ BCR7_LEDOUT

#define BCR7_LEDOUT 0x8000 /* led output pin value */

Definition at line 317 of file pcnethw.h.

◆ BCR7_LEDPOL

#define BCR7_LEDPOL 0x4000 /* led polarity */

Definition at line 316 of file pcnethw.h.

◆ BCR7_LNKSTE

#define BCR7_LNKSTE 0x40 /* link status enable */

Definition at line 310 of file pcnethw.h.

◆ BCR7_MPSE

#define BCR7_MPSE 0x200 /* magic packet status enable */

Definition at line 313 of file pcnethw.h.

◆ BCR7_PSE

#define BCR7_PSE 0x80 /* pulse stretcher enable */

Definition at line 311 of file pcnethw.h.

◆ BCR7_RCVE

#define BCR7_RCVE 0x4 /* receive status enable */

Definition at line 306 of file pcnethw.h.

◆ BCR7_RCVME

#define BCR7_RCVME 0x20 /* receive match status enable */

Definition at line 309 of file pcnethw.h.

◆ BCR7_RXPOLE

#define BCR7_RXPOLE 0x8 /* receive polarity status enable */

Definition at line 307 of file pcnethw.h.

◆ BCR7_XMTE

#define BCR7_XMTE 0x10 /* transmit status enable */

Definition at line 308 of file pcnethw.h.

◆ BCR9

#define BCR9 0x9 /* full-duplex control */

Definition at line 143 of file pcnethw.h.

◆ BCR9_AUIFD

#define BCR9_AUIFD 0x2 /* aui full-duplex */

Definition at line 321 of file pcnethw.h.

◆ BCR9_FDEN

#define BCR9_FDEN 0x1 /* full-duplex enable */

Definition at line 320 of file pcnethw.h.

◆ BCR9_FDRPAD

#define BCR9_FDRPAD 0x4 /* full-duplex runt packet accept disable */

Definition at line 322 of file pcnethw.h.

◆ BDP

#define BDP BDP16

Definition at line 49 of file pcnethw.h.

◆ BDP16

#define BDP16 0x16

Definition at line 41 of file pcnethw.h.

◆ BDP32

#define BDP32 0x1c

Definition at line 45 of file pcnethw.h.

◆ CSR0

#define CSR0 0x0 /* controller status register */

Definition at line 63 of file pcnethw.h.

◆ CSR0_BABL

#define CSR0_BABL 0x4000 /* babble */

Definition at line 167 of file pcnethw.h.

◆ CSR0_CERR

#define CSR0_CERR 0x2000 /* collision error */

Definition at line 166 of file pcnethw.h.

◆ CSR0_ERR

#define CSR0_ERR 0x8000 /* error */

Definition at line 168 of file pcnethw.h.

◆ CSR0_IDON

#define CSR0_IDON 0x100 /* initialization done */

Definition at line 161 of file pcnethw.h.

◆ CSR0_IENA

#define CSR0_IENA 0x40 /* interrupt enabled */

Definition at line 159 of file pcnethw.h.

◆ CSR0_INIT

#define CSR0_INIT 0x1 /* read initialization block */

Definition at line 153 of file pcnethw.h.

◆ CSR0_INTR

#define CSR0_INTR 0x80 /* interrupting */

Definition at line 160 of file pcnethw.h.

◆ CSR0_MERR

#define CSR0_MERR 0x800 /* memory error */

Definition at line 164 of file pcnethw.h.

◆ CSR0_MISS

#define CSR0_MISS 0x1000 /* missed frame */

Definition at line 165 of file pcnethw.h.

◆ CSR0_RINT

#define CSR0_RINT 0x400 /* receive interrupt */

Definition at line 163 of file pcnethw.h.

◆ CSR0_RXON

#define CSR0_RXON 0x20 /* receive on */

Definition at line 158 of file pcnethw.h.

◆ CSR0_STOP

#define CSR0_STOP 0x4 /* stop the chip */

Definition at line 155 of file pcnethw.h.

◆ CSR0_STRT

#define CSR0_STRT 0x2 /* start the chip */

Definition at line 154 of file pcnethw.h.

◆ CSR0_TDMD

#define CSR0_TDMD 0x8 /* transmit demand */

Definition at line 156 of file pcnethw.h.

◆ CSR0_TINT

#define CSR0_TINT 0x200 /* transmit interrupt */

Definition at line 162 of file pcnethw.h.

◆ CSR0_TXON

#define CSR0_TXON 0x10 /* transmit on */

Definition at line 157 of file pcnethw.h.

◆ CSR1

#define CSR1 0x1 /* init block address 0 */

Definition at line 64 of file pcnethw.h.

◆ CSR10

#define CSR10 0xa /* logical address filter 2 */

Definition at line 72 of file pcnethw.h.

◆ CSR100

#define CSR100 0x64 /* bus timeout */

Definition at line 131 of file pcnethw.h.

◆ CSR11

#define CSR11 0xb /* logical address filter 3 */

Definition at line 73 of file pcnethw.h.

◆ CSR112

#define CSR112 0x70 /* missed frame count */

Definition at line 132 of file pcnethw.h.

◆ CSR114

#define CSR114 0x72 /* receive collision count */

Definition at line 133 of file pcnethw.h.

◆ CSR12

#define CSR12 0xc /* physical address register 0 */

Definition at line 74 of file pcnethw.h.

◆ CSR122

#define CSR122 0x7a /* advanced feature control */

Definition at line 134 of file pcnethw.h.

◆ CSR124

#define CSR124 0x7c /* test register control */

Definition at line 135 of file pcnethw.h.

◆ CSR124_RPA

#define CSR124_RPA 0x4 /* runt packet accept */

Definition at line 242 of file pcnethw.h.

◆ CSR13

#define CSR13 0xd /* physical address register 1 */

Definition at line 75 of file pcnethw.h.

◆ CSR14

#define CSR14 0xe /* physical address register 2 */

Definition at line 76 of file pcnethw.h.

◆ CSR15

#define CSR15 0xf /* Mode */

Definition at line 77 of file pcnethw.h.

◆ CSR15_DAPC

#define CSR15_DAPC 0x800 /* disable automatic parity correction */

Definition at line 230 of file pcnethw.h.

◆ CSR15_DLNKTST

#define CSR15_DLNKTST 0x1000 /* disable link status */

Definition at line 231 of file pcnethw.h.

◆ CSR15_DRCVBC

#define CSR15_DRCVBC 0x4000 /* disable receive broadcast */

Definition at line 233 of file pcnethw.h.

◆ CSR15_DRCVPA

#define CSR15_DRCVPA 0x2000 /* disable receive physical address */

Definition at line 232 of file pcnethw.h.

◆ CSR15_DRTY

#define CSR15_DRTY 0x20 /* disable retry */

Definition at line 223 of file pcnethw.h.

◆ CSR15_DRX

#define CSR15_DRX 0x1 /* disable receiver */

Definition at line 218 of file pcnethw.h.

◆ CSR15_DTX

#define CSR15_DTX 0x2 /* disable transmitter */

Definition at line 219 of file pcnethw.h.

◆ CSR15_DXMTFCS

#define CSR15_DXMTFCS 0x8 /* disable transmit fcs */

Definition at line 221 of file pcnethw.h.

◆ CSR15_FCOLL

#define CSR15_FCOLL 0x10 /* force collision */

Definition at line 222 of file pcnethw.h.

◆ CSR15_INTL

#define CSR15_INTL 0x40 /* internal loopback */

Definition at line 224 of file pcnethw.h.

◆ CSR15_LOOP

#define CSR15_LOOP 0x4 /* loopback enable */

Definition at line 220 of file pcnethw.h.

◆ CSR15_LRT

#define CSR15_LRT 0x200 /* low receive threshold - same as TSEL */

Definition at line 227 of file pcnethw.h.

◆ CSR15_MENDECL

#define CSR15_MENDECL 0x400 /* mendec loopback mode */

Definition at line 229 of file pcnethw.h.

◆ CSR15_PORTSEL0

#define CSR15_PORTSEL0 0x80 /* port selection bit 0 */

Definition at line 225 of file pcnethw.h.

◆ CSR15_PORTSEL1

#define CSR15_PORTSEL1 0x100 /* port selection bit 1 */

Definition at line 226 of file pcnethw.h.

◆ CSR15_PROM

#define CSR15_PROM 0x8000 /* promiscuous mode */

Definition at line 234 of file pcnethw.h.

◆ CSR15_TSEL

#define CSR15_TSEL 0x200 /* transmit mode select - same as LRT */

Definition at line 228 of file pcnethw.h.

◆ CSR16

#define CSR16 0x10 /* initialization block address lower */

Definition at line 78 of file pcnethw.h.

◆ CSR17

#define CSR17 0x11 /* initialization block address upper */

Definition at line 79 of file pcnethw.h.

◆ CSR18

#define CSR18 0x12 /* current receive buffer address lower */

Definition at line 80 of file pcnethw.h.

◆ CSR19

#define CSR19 0x13 /* current receive buffer address upper */

Definition at line 81 of file pcnethw.h.

◆ CSR2

#define CSR2 0x2 /* init block address 1 */

Definition at line 65 of file pcnethw.h.

◆ CSR20

#define CSR20 0x14 /* current transmit buffer address lower */

Definition at line 82 of file pcnethw.h.

◆ CSR21

#define CSR21 0x15 /* current transmit buffer address upper */

Definition at line 83 of file pcnethw.h.

◆ CSR22

#define CSR22 0x16 /* next receive buffer address lower */

Definition at line 84 of file pcnethw.h.

◆ CSR23

#define CSR23 0x17 /* next receive buffer address upper */

Definition at line 85 of file pcnethw.h.

◆ CSR24

#define CSR24 0x18 /* base address of receive descriptor ring lower */

Definition at line 86 of file pcnethw.h.

◆ CSR25

#define CSR25 0x19 /* base address of receive descriptor ring upper */

Definition at line 87 of file pcnethw.h.

◆ CSR26

#define CSR26 0x1a /* next receive descriptor address lower */

Definition at line 88 of file pcnethw.h.

◆ CSR27

#define CSR27 0x1b /* next receive descriptor address upper */

Definition at line 89 of file pcnethw.h.

◆ CSR28

#define CSR28 0x1c /* current receive descriptor address lower */

Definition at line 90 of file pcnethw.h.

◆ CSR29

#define CSR29 0x1d /* current receive descriptor address upper */

Definition at line 91 of file pcnethw.h.

◆ CSR3

#define CSR3 0x3 /* interrupt masks and deferral control */

Definition at line 66 of file pcnethw.h.

◆ CSR30

#define CSR30 0x1e /* base address of transmit descriptor ring lower */

Definition at line 92 of file pcnethw.h.

◆ CSR31

#define CSR31 0x1f /* base address of transmit descriptor ring upper */

Definition at line 93 of file pcnethw.h.

◆ CSR32

#define CSR32 0x20 /* next transmit descriptor address lower */

Definition at line 94 of file pcnethw.h.

◆ CSR33

#define CSR33 0x21 /* next transmit descriptor address upper */

Definition at line 95 of file pcnethw.h.

◆ CSR34

#define CSR34 0x22 /* current transmit descriptor address lower */

Definition at line 96 of file pcnethw.h.

◆ CSR35

#define CSR35 0x23 /* current transmit descriptor address upper */

Definition at line 97 of file pcnethw.h.

◆ CSR36

#define CSR36 0x24 /* next next receive descriptor address lower */

Definition at line 98 of file pcnethw.h.

◆ CSR37

#define CSR37 0x25 /* next next receive descriptor address upper */

Definition at line 99 of file pcnethw.h.

◆ CSR38

#define CSR38 0x26 /* next next transmit descriptor address lower */

Definition at line 100 of file pcnethw.h.

◆ CSR39

#define CSR39 0x27 /* next next transmit descriptor address upper */

Definition at line 101 of file pcnethw.h.

◆ CSR3_BABLM

#define CSR3_BABLM 0x4000 /* babble interrupt mask */

Definition at line 181 of file pcnethw.h.

◆ CSR3_BSWP

#define CSR3_BSWP 0x4 /* byte swap */

Definition at line 171 of file pcnethw.h.

◆ CSR3_DXMT2PD

#define CSR3_DXMT2PD 0x10 /* disable transmit two-part deferral */

Definition at line 173 of file pcnethw.h.

◆ CSR3_DXSUFLO

#define CSR3_DXSUFLO 0x40 /* disable transmit stop on underflow */

Definition at line 175 of file pcnethw.h.

◆ CSR3_EMBA

#define CSR3_EMBA 0x8 /* enable modified backoff algorithm */

Definition at line 172 of file pcnethw.h.

◆ CSR3_IDONM

#define CSR3_IDONM 0x100 /* initialization done mask */

Definition at line 176 of file pcnethw.h.

◆ CSR3_LAPPEN

#define CSR3_LAPPEN 0x20 /* lookahead packet processing enable */

Definition at line 174 of file pcnethw.h.

◆ CSR3_MERRM

#define CSR3_MERRM 0x800 /* memory error interrupt mask */

Definition at line 179 of file pcnethw.h.

◆ CSR3_MISSM

#define CSR3_MISSM 0x1000 /* missed frame interrupt mask */

Definition at line 180 of file pcnethw.h.

◆ CSR3_RINTM

#define CSR3_RINTM 0x400 /* receive interrupt mask */

Definition at line 178 of file pcnethw.h.

◆ CSR3_TINTM

#define CSR3_TINTM 0x200 /* transmit interrupt mask */

Definition at line 177 of file pcnethw.h.

◆ CSR4

#define CSR4 0x4 /* test and features control */

Definition at line 67 of file pcnethw.h.

◆ CSR40

#define CSR40 0x28 /* current receive byte count */

Definition at line 102 of file pcnethw.h.

◆ CSR41

#define CSR41 0x29 /* current receive status */

Definition at line 103 of file pcnethw.h.

◆ CSR42

#define CSR42 0x2a /* current transmit byte count */

Definition at line 104 of file pcnethw.h.

◆ CSR43

#define CSR43 0x2b /* current transmit status */

Definition at line 105 of file pcnethw.h.

◆ CSR44

#define CSR44 0x2c /* next receive byte count */

Definition at line 106 of file pcnethw.h.

◆ CSR45

#define CSR45 0x2d /* next receive status */

Definition at line 107 of file pcnethw.h.

◆ CSR46

#define CSR46 0x2e /* poll time counter */

Definition at line 108 of file pcnethw.h.

◆ CSR47

#define CSR47 0x2f /* polling interval */

Definition at line 109 of file pcnethw.h.

◆ CSR4_APAD_XMT

#define CSR4_APAD_XMT 0x800 /* auto pad on transmit */

Definition at line 195 of file pcnethw.h.

◆ CSR4_ASTRP_RCV

#define CSR4_ASTRP_RCV 0x400 /* auto pad strip on receive */

Definition at line 194 of file pcnethw.h.

◆ CSR4_DMAPLUS

#define CSR4_DMAPLUS 0x4000 /* set to 1 for pci */

Definition at line 198 of file pcnethw.h.

◆ CSR4_DPOLL

#define CSR4_DPOLL 0x1000 /* disable transmit polling */

Definition at line 196 of file pcnethw.h.

◆ CSR4_EN124

#define CSR4_EN124 0x8000 /* enable CSR124 access */

Definition at line 199 of file pcnethw.h.

◆ CSR4_JAB

#define CSR4_JAB 0x2 /* interrupt on jabber error */

Definition at line 185 of file pcnethw.h.

◆ CSR4_JABM

#define CSR4_JABM 0x1 /* jabber interrupt mask */

Definition at line 184 of file pcnethw.h.

◆ CSR4_MFCO

#define CSR4_MFCO 0x200 /* interrupt on missed frame counter overflow */

Definition at line 193 of file pcnethw.h.

◆ CSR4_MFCOM

#define CSR4_MFCOM 0x100 /* missed frame counter overflow mask */

Definition at line 192 of file pcnethw.h.

◆ CSR4_RCVCCO

#define CSR4_RCVCCO 0X20 /* interrupt on receive collision counter overflow */

Definition at line 189 of file pcnethw.h.

◆ CSR4_RCVCCOM

#define CSR4_RCVCCOM 0x10 /* receive collision counter overflow mask */

Definition at line 188 of file pcnethw.h.

◆ CSR4_TIMER

#define CSR4_TIMER 0x2000 /* enable bus activity timer */

Definition at line 197 of file pcnethw.h.

◆ CSR4_TXSTRT

#define CSR4_TXSTRT 0x8 /* interrupt on transmit start */

Definition at line 187 of file pcnethw.h.

◆ CSR4_TXSTRTM

#define CSR4_TXSTRTM 0x4 /* transmit start interrupt mask */

Definition at line 186 of file pcnethw.h.

◆ CSR4_UINT

#define CSR4_UINT 0x40 /* user interrupt */

Definition at line 190 of file pcnethw.h.

◆ CSR4_UINTCMD

#define CSR4_UINTCMD 0x80 /* user interrupt command */

Definition at line 191 of file pcnethw.h.

◆ CSR5

#define CSR5 0x5 /* extended control and interrupt */

Definition at line 68 of file pcnethw.h.

◆ CSR58

#define CSR58 0x3a /* software style */

Definition at line 110 of file pcnethw.h.

◆ CSR58_APERREN

#define CSR58_APERREN 0x400 /* advanced parity error handling enable */

Definition at line 239 of file pcnethw.h.

◆ CSR58_CSRPCNET

#define CSR58_CSRPCNET 0x200 /* csr pcnet-isa configuration */

Definition at line 238 of file pcnethw.h.

◆ CSR58_SSIZE32

#define CSR58_SSIZE32 0x100 /* 32-bit software size */

Definition at line 237 of file pcnethw.h.

◆ CSR5_EXDINT

#define CSR5_EXDINT 0x80 /* excessive deferral interrupt */

Definition at line 209 of file pcnethw.h.

◆ CSR5_EXDINTE

#define CSR5_EXDINTE 0x40 /* excessive deferral interrupt enable */

Definition at line 208 of file pcnethw.h.

◆ CSR5_LTINTEN

#define CSR5_LTINTEN 0x4000 /* last transmit interrupt enable */

Definition at line 214 of file pcnethw.h.

◆ CSR5_MPEN

#define CSR5_MPEN 0x4 /* magic packet enable */

Definition at line 204 of file pcnethw.h.

◆ CSR5_MPINT

#define CSR5_MPINT 0x10 /* magic packet interrupt */

Definition at line 206 of file pcnethw.h.

◆ CSR5_MPINTE

#define CSR5_MPINTE 0x8 /* magic packet interrupt enable */

Definition at line 205 of file pcnethw.h.

◆ CSR5_MPMODE

#define CSR5_MPMODE 0x2 /* magic packet mode */

Definition at line 203 of file pcnethw.h.

◆ CSR5_MPPLBA

#define CSR5_MPPLBA 0x20 /* magic packet physical logical broadcast accept */

Definition at line 207 of file pcnethw.h.

◆ CSR5_SINE

#define CSR5_SINE 0x400 /* system interrupt enable */

Definition at line 212 of file pcnethw.h.

◆ CSR5_SINT

#define CSR5_SINT 0x800 /* system interrupt */

Definition at line 213 of file pcnethw.h.

◆ CSR5_SLPINT

#define CSR5_SLPINT 0x200 /* sleep interrupt */

Definition at line 211 of file pcnethw.h.

◆ CSR5_SLPINTE

#define CSR5_SLPINTE 0x100 /* sleep interrupt enable */

Definition at line 210 of file pcnethw.h.

◆ CSR5_SPND

#define CSR5_SPND 0x1 /* suspend */

Definition at line 202 of file pcnethw.h.

◆ CSR5_TOKINTD

#define CSR5_TOKINTD 0x8000 /* transmit ok interrupt disable */

Definition at line 215 of file pcnethw.h.

◆ CSR6

#define CSR6 0x6 /* rx/tx descriptor table length */

Definition at line 69 of file pcnethw.h.

◆ CSR60

#define CSR60 0x3c /* previous transmit descriptor address lower */

Definition at line 111 of file pcnethw.h.

◆ CSR61

#define CSR61 0x3d /* previous transmit descriptor address upper */

Definition at line 112 of file pcnethw.h.

◆ CSR62

#define CSR62 0x3e /* previous transmit byte count */

Definition at line 113 of file pcnethw.h.

◆ CSR63

#define CSR63 0x3f /* previous transmit status */

Definition at line 114 of file pcnethw.h.

◆ CSR64

#define CSR64 0x40 /* next transmit buffer address lower */

Definition at line 115 of file pcnethw.h.

◆ CSR65

#define CSR65 0x41 /* next transmit buffer address upper */

Definition at line 116 of file pcnethw.h.

◆ CSR66

#define CSR66 0x42 /* next transmit byte count */

Definition at line 117 of file pcnethw.h.

◆ CSR67

#define CSR67 0x43 /* next transmit status */

Definition at line 118 of file pcnethw.h.

◆ CSR72

#define CSR72 0x48 /* receive descriptor ring counter */

Definition at line 119 of file pcnethw.h.

◆ CSR74

#define CSR74 0x4a /* transmit descriptor ring counter */

Definition at line 120 of file pcnethw.h.

◆ CSR76

#define CSR76 0x4c /* receive descriptor ring length */

Definition at line 121 of file pcnethw.h.

◆ CSR78

#define CSR78 0x4e /* transmit descriptor ring length */

Definition at line 122 of file pcnethw.h.

◆ CSR8

#define CSR8 0x8 /* logical address filter 0 */

Definition at line 70 of file pcnethw.h.

◆ CSR80

#define CSR80 0x50 /* dma transfer counter and fifo watermark control */

Definition at line 123 of file pcnethw.h.

◆ CSR82

#define CSR82 0x52 /* bus activity timer */

Definition at line 124 of file pcnethw.h.

◆ CSR84

#define CSR84 0x54 /* dma address register lower */

Definition at line 125 of file pcnethw.h.

◆ CSR85

#define CSR85 0x55 /* dma address register upper */

Definition at line 126 of file pcnethw.h.

◆ CSR86

#define CSR86 0x56 /* buffer byte counter */

Definition at line 127 of file pcnethw.h.

◆ CSR88

#define CSR88 0x58 /* chip id register lower */

Definition at line 128 of file pcnethw.h.

◆ CSR89

#define CSR89 0x59 /* chip id register upper */

Definition at line 129 of file pcnethw.h.

◆ CSR9

#define CSR9 0x9 /* logical address filter 1 */

Definition at line 71 of file pcnethw.h.

◆ CSR94

#define CSR94 0x5e /* transmit time domain reflectometry count */

Definition at line 130 of file pcnethw.h.

◆ DEV_ID

#define DEV_ID 0x2000

Definition at line 54 of file pcnethw.h.

◆ MASK16

#define MASK16 ( __x__ ) ((__x__) & 0x0000ffff)

Definition at line 32 of file pcnethw.h.

◆ NUMBER_OF_PORTS

#define NUMBER_OF_PORTS 0x20 /* number of i/o ports the board requires */

Definition at line 34 of file pcnethw.h.

◆ PCI_ID

#define PCI_ID 0x20001022

Definition at line 52 of file pcnethw.h.

◆ RAP

#define RAP RAP16

Definition at line 48 of file pcnethw.h.

◆ RAP16

#define RAP16 0x12

Definition at line 39 of file pcnethw.h.

◆ RAP32

#define RAP32 0x14

Definition at line 43 of file pcnethw.h.

◆ RD_BAM

#define RD_BAM 0x10 /* broadcast address match */

Definition at line 372 of file pcnethw.h.

◆ RD_BPE

#define RD_BPE 0x80 /* bus parity error */

Definition at line 375 of file pcnethw.h.

◆ RD_BUFF

#define RD_BUFF 0x400 /* buffer error */

Definition at line 378 of file pcnethw.h.

◆ RD_CRC

#define RD_CRC 0x800 /* crc error */

Definition at line 379 of file pcnethw.h.

◆ RD_ENP

#define RD_ENP 0x100 /* end of packet */

Definition at line 376 of file pcnethw.h.

◆ RD_ERR

#define RD_ERR 0x4000 /* an error bit is set */

Definition at line 382 of file pcnethw.h.

◆ RD_FRAM

#define RD_FRAM 0x2000 /* framing error */

Definition at line 381 of file pcnethw.h.

◆ RD_LAFM

#define RD_LAFM 0x20 /* logical address filter match */

Definition at line 373 of file pcnethw.h.

◆ RD_OFLO

#define RD_OFLO 0x1000 /* overflow error */

Definition at line 380 of file pcnethw.h.

◆ RD_OWN

#define RD_OWN 0x8000 /* buffer ownership (0=host, 1=nic) */

Definition at line 383 of file pcnethw.h.

◆ RD_PAM

#define RD_PAM 0x40 /* physical address match */

Definition at line 374 of file pcnethw.h.

◆ RD_STP

#define RD_STP 0x200 /* start of packet */

Definition at line 377 of file pcnethw.h.

◆ RDP

#define RDP 0x10 /* same address in 16-bit and 32-bit IO mode */

Definition at line 37 of file pcnethw.h.

◆ RESET16

#define RESET16 0x14

Definition at line 40 of file pcnethw.h.

◆ RESET32

#define RESET32 0x18

Definition at line 44 of file pcnethw.h.

◆ SW_STYLE_0

#define SW_STYLE_0 0

Definition at line 57 of file pcnethw.h.

◆ SW_STYLE_1

#define SW_STYLE_1 1

Definition at line 58 of file pcnethw.h.

◆ SW_STYLE_2

#define SW_STYLE_2 2

Definition at line 59 of file pcnethw.h.

◆ SW_STYLE_3

#define SW_STYLE_3 3

Definition at line 60 of file pcnethw.h.

◆ TD1_ADD_FCS

#define TD1_ADD_FCS 0x2000 /* force fcs generation - same as NO_FCS */

Definition at line 404 of file pcnethw.h.

◆ TD1_BPE

#define TD1_BPE 0x80 /* bus parity error */

Definition at line 397 of file pcnethw.h.

◆ TD1_DEF

#define TD1_DEF 0x400 /* frame transmission deferred */

Definition at line 400 of file pcnethw.h.

◆ TD1_ENP

#define TD1_ENP 0x100 /* end of packet */

Definition at line 398 of file pcnethw.h.

◆ TD1_ERR

#define TD1_ERR 0x4000 /* an error bit is set */

Definition at line 406 of file pcnethw.h.

◆ TD1_LTINT

#define TD1_LTINT 0x1000 /* suppress transmit success interrupt - same as MORE */

Definition at line 403 of file pcnethw.h.

◆ TD1_MORE

#define TD1_MORE 0x1000 /* more than 1 transmission retry required - same as LTINT */

Definition at line 402 of file pcnethw.h.

◆ TD1_NO_FCS

#define TD1_NO_FCS 0x2000 /* prevent fcs generation - same as ADD_FCS */

Definition at line 405 of file pcnethw.h.

◆ TD1_ONE

#define TD1_ONE 0x800 /* exactly one retry was needed for transmission */

Definition at line 401 of file pcnethw.h.

◆ TD1_OWN

#define TD1_OWN 0x8000 /* buffer ownership */

Definition at line 407 of file pcnethw.h.

◆ TD1_STP

#define TD1_STP 0x200 /* start of packet */

Definition at line 399 of file pcnethw.h.

◆ TD2_BUFF

#define TD2_BUFF 0x8000 /* buffer error */

Definition at line 415 of file pcnethw.h.

◆ TD2_EXDEF

#define TD2_EXDEF 0x2000 /* excessive deferral */

Definition at line 413 of file pcnethw.h.

◆ TD2_LCAR

#define TD2_LCAR 0x800 /* loss of carrier */

Definition at line 411 of file pcnethw.h.

◆ TD2_LCOL

#define TD2_LCOL 0x1000 /* late collision */

Definition at line 412 of file pcnethw.h.

◆ TD2_RTRY

#define TD2_RTRY 0x400 /* retry error */

Definition at line 410 of file pcnethw.h.

◆ TD2_UFLO

#define TD2_UFLO 0x4000 /* buffer underflow */

Definition at line 414 of file pcnethw.h.

◆ VEN_ID

#define VEN_ID 0x1022

Definition at line 53 of file pcnethw.h.

Typedef Documentation

◆ INITIALIZATION_BLOCK

typedef struct _INITIALIZATION_BLOCK INITIALIZATION_BLOCK

◆ PINITIALIZATION_BLOCK

typedef struct _INITIALIZATION_BLOCK * PINITIALIZATION_BLOCK

◆ PRECEIVE_DESCRIPTOR

typedef struct _RECEIVE_DESCRIPTOR * PRECEIVE_DESCRIPTOR

◆ PTRANSMIT_DESCRIPTOR

typedef struct _TRANSMIT_DESCRIPTOR * PTRANSMIT_DESCRIPTOR

◆ RECEIVE_DESCRIPTOR

typedef struct _RECEIVE_DESCRIPTOR RECEIVE_DESCRIPTOR

◆ TRANSMIT_DESCRIPTOR

typedef struct _TRANSMIT_DESCRIPTOR TRANSMIT_DESCRIPTOR

Classes

Macros

Typedefs