ReactOS 0.4.15-dev-8131-g4988de4
pcnethw.h
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1/*
2 * ReactOS AMD PCNet Driver
3 *
4 * Copyright (C) 2003 Vizzini <vizzini@plasmic.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * PURPOSE:
21 * PCNet hardware configuration constants
22 * REVISIONS:
23 * 01-Sept-2003 vizzini - Created
24 * NOTES:
25 * - This file represents a clean re-implementation from the AMD
26 * PCNet II chip documentation (Am79C790A, pub# 19436).
27 */
28
29#pragma once
30
31/* when in 32-bit mode, most registers require the top 16 bits be 0. */
32#define MASK16(__x__) ((__x__) & 0x0000ffff)
33
34#define NUMBER_OF_PORTS 0x20 /* number of i/o ports the board requires */
35
36/* offsets of important registers */
37#define RDP 0x10 /* same address in 16-bit and 32-bit IO mode */
38
39#define RAP16 0x12
40#define RESET16 0x14
41#define BDP16 0x16
42
43#define RAP32 0x14
44#define RESET32 0x18
45#define BDP32 0x1c
46
47/* NOTE: vmware doesn't support 32-bit i/o programming so we use 16-bit */
48#define RAP RAP16
49#define BDP BDP16
50
51/* pci id of the device */
52#define PCI_ID 0x20001022
53#define VEN_ID 0x1022
54#define DEV_ID 0x2000
55
56/* software style constants */
57#define SW_STYLE_0 0
58#define SW_STYLE_1 1
59#define SW_STYLE_2 2
60#define SW_STYLE_3 3
61
62/* control and status registers */
63#define CSR0 0x0 /* controller status register */
64#define CSR1 0x1 /* init block address 0 */
65#define CSR2 0x2 /* init block address 1 */
66#define CSR3 0x3 /* interrupt masks and deferral control */
67#define CSR4 0x4 /* test and features control */
68#define CSR5 0x5 /* extended control and interrupt */
69#define CSR6 0x6 /* rx/tx descriptor table length */
70#define CSR8 0x8 /* logical address filter 0 */
71#define CSR9 0x9 /* logical address filter 1 */
72#define CSR10 0xa /* logical address filter 2 */
73#define CSR11 0xb /* logical address filter 3 */
74#define CSR12 0xc /* physical address register 0 */
75#define CSR13 0xd /* physical address register 1 */
76#define CSR14 0xe /* physical address register 2 */
77#define CSR15 0xf /* Mode */
78#define CSR16 0x10 /* initialization block address lower */
79#define CSR17 0x11 /* initialization block address upper */
80#define CSR18 0x12 /* current receive buffer address lower */
81#define CSR19 0x13 /* current receive buffer address upper */
82#define CSR20 0x14 /* current transmit buffer address lower */
83#define CSR21 0x15 /* current transmit buffer address upper */
84#define CSR22 0x16 /* next receive buffer address lower */
85#define CSR23 0x17 /* next receive buffer address upper */
86#define CSR24 0x18 /* base address of receive descriptor ring lower */
87#define CSR25 0x19 /* base address of receive descriptor ring upper */
88#define CSR26 0x1a /* next receive descriptor address lower */
89#define CSR27 0x1b /* next receive descriptor address upper */
90#define CSR28 0x1c /* current receive descriptor address lower */
91#define CSR29 0x1d /* current receive descriptor address upper */
92#define CSR30 0x1e /* base address of transmit descriptor ring lower */
93#define CSR31 0x1f /* base address of transmit descriptor ring upper */
94#define CSR32 0x20 /* next transmit descriptor address lower */
95#define CSR33 0x21 /* next transmit descriptor address upper */
96#define CSR34 0x22 /* current transmit descriptor address lower */
97#define CSR35 0x23 /* current transmit descriptor address upper */
98#define CSR36 0x24 /* next next receive descriptor address lower */
99#define CSR37 0x25 /* next next receive descriptor address upper */
100#define CSR38 0x26 /* next next transmit descriptor address lower */
101#define CSR39 0x27 /* next next transmit descriptor address upper */
102#define CSR40 0x28 /* current receive byte count */
103#define CSR41 0x29 /* current receive status */
104#define CSR42 0x2a /* current transmit byte count */
105#define CSR43 0x2b /* current transmit status */
106#define CSR44 0x2c /* next receive byte count */
107#define CSR45 0x2d /* next receive status */
108#define CSR46 0x2e /* poll time counter */
109#define CSR47 0x2f /* polling interval */
110#define CSR58 0x3a /* software style */
111#define CSR60 0x3c /* previous transmit descriptor address lower */
112#define CSR61 0x3d /* previous transmit descriptor address upper */
113#define CSR62 0x3e /* previous transmit byte count */
114#define CSR63 0x3f /* previous transmit status */
115#define CSR64 0x40 /* next transmit buffer address lower */
116#define CSR65 0x41 /* next transmit buffer address upper */
117#define CSR66 0x42 /* next transmit byte count */
118#define CSR67 0x43 /* next transmit status */
119#define CSR72 0x48 /* receive descriptor ring counter */
120#define CSR74 0x4a /* transmit descriptor ring counter */
121#define CSR76 0x4c /* receive descriptor ring length */
122#define CSR78 0x4e /* transmit descriptor ring length */
123#define CSR80 0x50 /* dma transfer counter and fifo watermark control */
124#define CSR82 0x52 /* bus activity timer */
125#define CSR84 0x54 /* dma address register lower */
126#define CSR85 0x55 /* dma address register upper */
127#define CSR86 0x56 /* buffer byte counter */
128#define CSR88 0x58 /* chip id register lower */
129#define CSR89 0x59 /* chip id register upper */
130#define CSR94 0x5e /* transmit time domain reflectometry count */
131#define CSR100 0x64 /* bus timeout */
132#define CSR112 0x70 /* missed frame count */
133#define CSR114 0x72 /* receive collision count */
134#define CSR122 0x7a /* advanced feature control */
135#define CSR124 0x7c /* test register control */
136
137/* bus configuration registers */
138#define BCR2 0x2 /* miscellaneous configuration */
139#define BCR4 0x4 /* link status led */
140#define BCR5 0x5 /* led1 status */
141#define BCR6 0x6 /* led2 status */
142#define BCR7 0x7 /* led3 status */
143#define BCR9 0x9 /* full-duplex control */
144#define BCR16 0x10 /* i/o base address lower */
145#define BCR17 0x11 /* i/o base address upper */
146#define BCR18 0x12 /* burst and bus control register */
147#define BCR19 0x13 /* eeprom control and status */
148#define BCR20 0x14 /* software style */
149#define BCR21 0x15 /* interrupt control */
150#define BCR22 0x16 /* pci latency register */
151
152/* CSR0 bits */
153#define CSR0_INIT 0x1 /* read initialization block */
154#define CSR0_STRT 0x2 /* start the chip */
155#define CSR0_STOP 0x4 /* stop the chip */
156#define CSR0_TDMD 0x8 /* transmit demand */
157#define CSR0_TXON 0x10 /* transmit on */
158#define CSR0_RXON 0x20 /* receive on */
159#define CSR0_IENA 0x40 /* interrupt enabled */
160#define CSR0_INTR 0x80 /* interrupting */
161#define CSR0_IDON 0x100 /* initialization done */
162#define CSR0_TINT 0x200 /* transmit interrupt */
163#define CSR0_RINT 0x400 /* receive interrupt */
164#define CSR0_MERR 0x800 /* memory error */
165#define CSR0_MISS 0x1000 /* missed frame */
166#define CSR0_CERR 0x2000 /* collision error */
167#define CSR0_BABL 0x4000 /* babble */
168#define CSR0_ERR 0x8000 /* error */
169
170/* CSR3 bits */
171#define CSR3_BSWP 0x4 /* byte swap */
172#define CSR3_EMBA 0x8 /* enable modified backoff algorithm */
173#define CSR3_DXMT2PD 0x10 /* disable transmit two-part deferral */
174#define CSR3_LAPPEN 0x20 /* lookahead packet processing enable */
175#define CSR3_DXSUFLO 0x40 /* disable transmit stop on underflow */
176#define CSR3_IDONM 0x100 /* initialization done mask */
177#define CSR3_TINTM 0x200 /* transmit interrupt mask */
178#define CSR3_RINTM 0x400 /* receive interrupt mask */
179#define CSR3_MERRM 0x800 /* memory error interrupt mask */
180#define CSR3_MISSM 0x1000 /* missed frame interrupt mask */
181#define CSR3_BABLM 0x4000 /* babble interrupt mask */
182
183/* CSR4 bits */
184#define CSR4_JABM 0x1 /* jabber interrupt mask */
185#define CSR4_JAB 0x2 /* interrupt on jabber error */
186#define CSR4_TXSTRTM 0x4 /* transmit start interrupt mask */
187#define CSR4_TXSTRT 0x8 /* interrupt on transmit start */
188#define CSR4_RCVCCOM 0x10 /* receive collision counter overflow mask */
189#define CSR4_RCVCCO 0X20 /* interrupt on receive collision counter overflow */
190#define CSR4_UINT 0x40 /* user interrupt */
191#define CSR4_UINTCMD 0x80 /* user interrupt command */
192#define CSR4_MFCOM 0x100 /* missed frame counter overflow mask */
193#define CSR4_MFCO 0x200 /* interrupt on missed frame counter overflow */
194#define CSR4_ASTRP_RCV 0x400 /* auto pad strip on receive */
195#define CSR4_APAD_XMT 0x800 /* auto pad on transmit */
196#define CSR4_DPOLL 0x1000 /* disable transmit polling */
197#define CSR4_TIMER 0x2000 /* enable bus activity timer */
198#define CSR4_DMAPLUS 0x4000 /* set to 1 for pci */
199#define CSR4_EN124 0x8000 /* enable CSR124 access */
200
201/* CSR5 bits */
202#define CSR5_SPND 0x1 /* suspend */
203#define CSR5_MPMODE 0x2 /* magic packet mode */
204#define CSR5_MPEN 0x4 /* magic packet enable */
205#define CSR5_MPINTE 0x8 /* magic packet interrupt enable */
206#define CSR5_MPINT 0x10 /* magic packet interrupt */
207#define CSR5_MPPLBA 0x20 /* magic packet physical logical broadcast accept */
208#define CSR5_EXDINTE 0x40 /* excessive deferral interrupt enable */
209#define CSR5_EXDINT 0x80 /* excessive deferral interrupt */
210#define CSR5_SLPINTE 0x100 /* sleep interrupt enable */
211#define CSR5_SLPINT 0x200 /* sleep interrupt */
212#define CSR5_SINE 0x400 /* system interrupt enable */
213#define CSR5_SINT 0x800 /* system interrupt */
214#define CSR5_LTINTEN 0x4000 /* last transmit interrupt enable */
215#define CSR5_TOKINTD 0x8000 /* transmit ok interrupt disable */
216
217/* CSR15 bits */
218#define CSR15_DRX 0x1 /* disable receiver */
219#define CSR15_DTX 0x2 /* disable transmitter */
220#define CSR15_LOOP 0x4 /* loopback enable */
221#define CSR15_DXMTFCS 0x8 /* disable transmit fcs */
222#define CSR15_FCOLL 0x10 /* force collision */
223#define CSR15_DRTY 0x20 /* disable retry */
224#define CSR15_INTL 0x40 /* internal loopback */
225#define CSR15_PORTSEL0 0x80 /* port selection bit 0 */
226#define CSR15_PORTSEL1 0x100 /* port selection bit 1 */
227#define CSR15_LRT 0x200 /* low receive threshold - same as TSEL */
228#define CSR15_TSEL 0x200 /* transmit mode select - same as LRT */
229#define CSR15_MENDECL 0x400 /* mendec loopback mode */
230#define CSR15_DAPC 0x800 /* disable automatic parity correction */
231#define CSR15_DLNKTST 0x1000 /* disable link status */
232#define CSR15_DRCVPA 0x2000 /* disable receive physical address */
233#define CSR15_DRCVBC 0x4000 /* disable receive broadcast */
234#define CSR15_PROM 0x8000 /* promiscuous mode */
235
236/* CSR58 bits */
237#define CSR58_SSIZE32 0x100 /* 32-bit software size */
238#define CSR58_CSRPCNET 0x200 /* csr pcnet-isa configuration */
239#define CSR58_APERREN 0x400 /* advanced parity error handling enable */
240
241/* CSR124 bits */
242#define CSR124_RPA 0x4 /* runt packet accept */
243
244/* BCR2 bits */
245#define BCR2_ASEL 0x2 /* auto-select media */
246#define BCR2_AWAKE 0x4 /* select sleep mode */
247#define BCR2_EADISEL 0x8 /* eadi select */
248#define BCR2_DXCVRPOL 0x10 /* dxcvr polarity */
249#define BCR2_DXCVRCTL 0x20 /* dxcvr control */
250#define BCR2_INTLEVEL 0x80 /* interrupt level/edge */
251#define BCR2_APROMWE 0x100 /* address prom write enable */
252#define BCR2_LEDPE 0x1000 /* LED programming enable */
253#define BCR2_TMAULOOP 0x4000 /* t-mau transmit on loopback */
254
255/* BCR4 bits */
256#define BCR4_COLE 0x1 /* collision status enable */
257#define BCR4_JABE 0x2 /* jabber status enable */
258#define BCR4_RCVE 0x4 /* receive status enable */
259#define BCR4_RXPOLE 0x8 /* receive polarity status enable */
260#define BCR4_XMTE 0x10 /* transmit status enable */
261#define BCR4_RCVME 0x20 /* receive match status enable */
262#define BCR4_LNKSTE 0x40 /* link status enable */
263#define BCR4_PSE 0x80 /* pulse stretcher enable */
264#define BCR4_FDLSE 0x100 /* full-duplex link status enable */
265#define BCR4_MPSE 0x200 /* magic packet status enable */
266#define BCR4_E100 0x1000 /* link speed */
267#define BCR4_LEDDIS 0x2000 /* led disable */
268#define BCR4_LEDPOL 0x4000 /* led polarity */
269#define BCR4_LEDOUT 0x8000 /* led output pin value */
270
271/* BCR5 bits */
272#define BCR5_COLE 0x1 /* collision status enable */
273#define BCR5_JABE 0x2 /* jabber status enable */
274#define BCR5_RCVE 0x4 /* receive status enable */
275#define BCR5_RXPOLE 0x8 /* receive polarity status enable */
276#define BCR5_XMTE 0x10 /* transmit status enable */
277#define BCR5_RCVME 0x20 /* receive match status enable */
278#define BCR5_LNKSTE 0x40 /* link status enable */
279#define BCR5_PSE 0x80 /* pulse stretcher enable */
280#define BCR5_FDLSE 0x100 /* full-duplex link status enable */
281#define BCR5_MPSE 0x200 /* magic packet status enable */
282#define BCR5_E100 0x1000 /* link speed */
283#define BCR5_LEDDIS 0x2000 /* led disable */
284#define BCR5_LEDPOL 0x4000 /* led polarity */
285#define BCR5_LEDOUT 0x8000 /* led output pin value */
286
287/* BCR6 bits */
288#define BCR6_COLE 0x1 /* collision status enable */
289#define BCR6_JABE 0x2 /* jabber status enable */
290#define BCR6_RCVE 0x4 /* receive status enable */
291#define BCR6_RXPOLE 0x8 /* receive polarity status enable */
292#define BCR6_XMTE 0x10 /* transmit status enable */
293#define BCR6_RCVME 0x20 /* receive match status enable */
294#define BCR6_LNKSTE 0x40 /* link status enable */
295#define BCR6_PSE 0x80 /* pulse stretcher enable */
296#define BCR6_FDLSE 0x100 /* full-duplex link status enable */
297#define BCR6_MPSE 0x200 /* magic packet status enable */
298#define BCR6_E100 0x1000 /* link speed */
299#define BCR6_LEDDIS 0x2000 /* led disable */
300#define BCR6_LEDPOL 0x4000 /* led polarity */
301#define BCR6_LEDOUT 0x8000 /* led output pin value */
302
303/* BCR7 bits */
304#define BCR7_COLE 0x1 /* collision status enable */
305#define BCR7_JABE 0x2 /* jabber status enable */
306#define BCR7_RCVE 0x4 /* receive status enable */
307#define BCR7_RXPOLE 0x8 /* receive polarity status enable */
308#define BCR7_XMTE 0x10 /* transmit status enable */
309#define BCR7_RCVME 0x20 /* receive match status enable */
310#define BCR7_LNKSTE 0x40 /* link status enable */
311#define BCR7_PSE 0x80 /* pulse stretcher enable */
312#define BCR7_FDLSE 0x100 /* full-duplex link status enable */
313#define BCR7_MPSE 0x200 /* magic packet status enable */
314#define BCR7_E100 0x1000 /* link speed */
315#define BCR7_LEDDIS 0x2000 /* led disable */
316#define BCR7_LEDPOL 0x4000 /* led polarity */
317#define BCR7_LEDOUT 0x8000 /* led output pin value */
318
319/* BCR9 bits */
320#define BCR9_FDEN 0x1 /* full-duplex enable */
321#define BCR9_AUIFD 0x2 /* aui full-duplex */
322#define BCR9_FDRPAD 0x4 /* full-duplex runt packet accept disable */
323
324/* BCR18 bits */
325#define BCR18_BWRITE 0x20 /* burst write enable */
326#define BCR18_BREADE 0x40 /* burst read enable */
327#define BCR18_DWIO 0x80 /* dword i/o enable */
328#define BCR18_EXTREQ 0x100 /* extended request */
329#define BCR18_MEMCMD 0x200 /* memory command */
330
331/* BCR19 bits */
332#define BCR19_EDI 0x1 /* eeprom data in - same as EDO */
333#define BCR19_ED0 0x1 /* eeprom data out - same as EDI */
334#define BCR19_ESK 0x2 /* eeprom serial clock */
335#define BCR19_ECS 0x4 /* eeprom chip select */
336#define BCR19_EEN 0x8 /* eeprom port enable */
337#define BCR19_EEDET 0x2000 /* eeprom detect */
338#define BCR19_PREAD 0x4000 /* eeprom read */
339#define BCR19_PVALID 0x8000 /* eeprom valid */
340
341/* BCR20 bits */
342#define BCR20_SSIZE32 0x100 /* 32-bit software size */
343#define BCR20_CSRPCNET 0x200 /* csr pcnet-isa configuration */
344#define BCR20_APERREN 0x400 /* advanced parity error handling enable */
345
346/* initialization block for 32-bit software style */
348{
349 USHORT MODE; /* card mode (csr15) */
350 UCHAR RLEN; /* encoded number of receive descriptor ring entries */
351 UCHAR TLEN; /* encoded number of transmit descriptor ring entries */
352 UCHAR PADR[6]; /* physical address */
353 USHORT RES; /* reserved */
354 UCHAR LADR[8]; /* logical address */
355 ULONG RDRA; /* receive descriptor ring address */
356 ULONG TDRA; /* transmit descriptor ring address */
358
359/* receive descriptor, software stle 2 (32-bit) */
361{
362 ULONG RBADR; /* receive buffer address */
363 USHORT BCNT; /* two's compliment buffer byte count - NOTE: always OR with 0xf000 */
364 USHORT FLAGS; /* flags - always and with 0xfff0 */
365 USHORT MCNT; /* message byte count ; always AND with 0x0fff */
366 UCHAR RPC; /* runt packet count */
367 UCHAR RCC; /* receive collision count */
368 ULONG RES; /* reserved */
370
371/* receive descriptor flags */
372#define RD_BAM 0x10 /* broadcast address match */
373#define RD_LAFM 0x20 /* logical address filter match */
374#define RD_PAM 0x40 /* physical address match */
375#define RD_BPE 0x80 /* bus parity error */
376#define RD_ENP 0x100 /* end of packet */
377#define RD_STP 0x200 /* start of packet */
378#define RD_BUFF 0x400 /* buffer error */
379#define RD_CRC 0x800 /* crc error */
380#define RD_OFLO 0x1000 /* overflow error */
381#define RD_FRAM 0x2000 /* framing error */
382#define RD_ERR 0x4000 /* an error bit is set */
383#define RD_OWN 0x8000 /* buffer ownership (0=host, 1=nic) */
384
385/* transmit descriptor, software style 2 */
387{
388 ULONG TBADR; /* transmit buffer address */
389 USHORT BCNT; /* two's compliment buffer byte count - OR with 0xf000 */
390 USHORT FLAGS; /* flags */
391 USHORT TRC; /* transmit retry count (AND with 0x000f */
392 USHORT FLAGS2; /* more flags */
393 ULONG RES; /* reserved */
395
396/* transmit descriptor flags */
397#define TD1_BPE 0x80 /* bus parity error */
398#define TD1_ENP 0x100 /* end of packet */
399#define TD1_STP 0x200 /* start of packet */
400#define TD1_DEF 0x400 /* frame transmission deferred */
401#define TD1_ONE 0x800 /* exactly one retry was needed for transmission */
402#define TD1_MORE 0x1000 /* more than 1 transmission retry required - same as LTINT */
403#define TD1_LTINT 0x1000 /* suppress transmit success interrupt - same as MORE */
404#define TD1_ADD_FCS 0x2000 /* force fcs generation - same as NO_FCS */
405#define TD1_NO_FCS 0x2000 /* prevent fcs generation - same as ADD_FCS */
406#define TD1_ERR 0x4000 /* an error bit is set */
407#define TD1_OWN 0x8000 /* buffer ownership */
408
409/* transmit descriptor flags2 flags */
410#define TD2_RTRY 0x400 /* retry error */
411#define TD2_LCAR 0x800 /* loss of carrier */
412#define TD2_LCOL 0x1000 /* late collision */
413#define TD2_EXDEF 0x2000 /* excessive deferral */
414#define TD2_UFLO 0x4000 /* buffer underflow */
415#define TD2_BUFF 0x8000 /* buffer error */
struct _RECEIVE_DESCRIPTOR * PRECEIVE_DESCRIPTOR
struct _TRANSMIT_DESCRIPTOR TRANSMIT_DESCRIPTOR
struct _RECEIVE_DESCRIPTOR RECEIVE_DESCRIPTOR
struct _INITIALIZATION_BLOCK INITIALIZATION_BLOCK
struct _TRANSMIT_DESCRIPTOR * PTRANSMIT_DESCRIPTOR
struct _INITIALIZATION_BLOCK * PINITIALIZATION_BLOCK
unsigned short USHORT
Definition: pedump.c:61
uint32_t ULONG
Definition: typedefs.h:59
unsigned char UCHAR
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