dma.h File Reference

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Go to the source code of this file.

Classes
struct	_DMA_CHANNEL
struct	_DMA_CONTROLLER
struct	_DMA_PAGE_REGISTER

Macros
#define	DMA_CONTROLLERS   2
#define	DMA_CONTROLLER_CHANNELS   4

Typedefs
typedef struct _DMA_CHANNEL	DMA_CHANNEL
typedef struct _DMA_CHANNEL *	PDMA_CHANNEL
typedef struct _DMA_CONTROLLER	DMA_CONTROLLER
typedef struct _DMA_CONTROLLER *	PDMA_CONTROLLER
typedef struct _DMA_PAGE_REGISTER	DMA_PAGE_REGISTER
typedef struct _DMA_PAGE_REGISTER *	PDMA_PAGE_REGISTER

Functions
DWORD	DmaRequest (IN WORD iChannel, IN OUT PVOID Buffer, IN DWORD length)
VOID	DmaInitialize (VOID)

Macro Definition Documentation

DMA_CONTROLLER_CHANNELS

#define DMA_CONTROLLER_CHANNELS   4

Definition at line 16 of file dma.h.

DMA_CONTROLLERS

#define DMA_CONTROLLERS   2

Definition at line 15 of file dma.h.

Typedef Documentation

DMA_CHANNEL

typedef struct _DMA_CHANNEL DMA_CHANNEL

DMA_CONTROLLER

typedef struct _DMA_CONTROLLER DMA_CONTROLLER

DMA_PAGE_REGISTER

typedef struct _DMA_PAGE_REGISTER DMA_PAGE_REGISTER

PDMA_CHANNEL

typedef struct _DMA_CHANNEL * PDMA_CHANNEL

PDMA_CONTROLLER

typedef struct _DMA_CONTROLLER * PDMA_CONTROLLER

PDMA_PAGE_REGISTER

typedef struct _DMA_PAGE_REGISTER * PDMA_PAGE_REGISTER

Function Documentation

DmaInitialize()

VOID DmaInitialize

(

VOID

)

Definition at line 549 of file dma.c.

{
    /* Register the I/O Ports */
 
    /* Channels 0(Reserved)..3 */
    RegisterIoPort(0x00, DmaReadPort, DmaWritePort);    /* Current(R) / Start(W) Address Register 0 (Reserved) */
    RegisterIoPort(0x01, DmaReadPort, DmaWritePort);    /* Current(R) / Base (W) Count Register 0 (Reserved) */
    RegisterIoPort(0x02, DmaReadPort, DmaWritePort);    /* Current(R) / Start(W) Address Register 1 */
    RegisterIoPort(0x03, DmaReadPort, DmaWritePort);    /* Current(R) / Base (W) Count Register 1 */
    RegisterIoPort(0x04, DmaReadPort, DmaWritePort);    /* Current(R) / Start(W) Address Register 2 */
    RegisterIoPort(0x05, DmaReadPort, DmaWritePort);    /* Current(R) / Base (W) Count Register 2 */
    RegisterIoPort(0x06, DmaReadPort, DmaWritePort);    /* Current(R) / Start(W) Address Register 3 */
    RegisterIoPort(0x07, DmaReadPort, DmaWritePort);    /* Current(R) / Base (W) Count Register 3 */
 
    RegisterIoPort(0x08, DmaReadPort, DmaWritePort);    /* Status (Read) / Command (Write) Registers */
    RegisterIoPort(0x09,        NULL, DmaWritePort);    /* Request Register */
    RegisterIoPort(0x0A,        NULL, DmaWritePort);    /* Single Channel Mask Register */
    RegisterIoPort(0x0B,        NULL, DmaWritePort);    /* Mode Register */
    RegisterIoPort(0x0C,        NULL, DmaWritePort);    /* Flip-Flop Reset Register */
    RegisterIoPort(0x0D, DmaReadPort, DmaWritePort);    /* Intermediate (Read) / Master Reset (Write) Registers */
    RegisterIoPort(0x0E,        NULL, DmaWritePort);    /* Mask Reset Register */
    RegisterIoPort(0x0F, DmaReadPort, DmaWritePort);    /* Multi-Channel Mask Register */
 
 
    /* Channels 4(Reserved)..7 */
    RegisterIoPort(0xC0, DmaReadPort, DmaWritePort);    /* Current(R) / Start(W) Address Register 4 (Reserved) */
    RegisterIoPort(0xC2, DmaReadPort, DmaWritePort);    /* Current(R) / Base (W) Count Register 4 (Reserved) */
    RegisterIoPort(0xC4, DmaReadPort, DmaWritePort);    /* Current(R) / Start(W) Address Register 5 */
    RegisterIoPort(0xC6, DmaReadPort, DmaWritePort);    /* Current(R) / Base (W) Count Register 5 */
    RegisterIoPort(0xC8, DmaReadPort, DmaWritePort);    /* Current(R) / Start(W) Address Register 6 */
    RegisterIoPort(0xCA, DmaReadPort, DmaWritePort);    /* Current(R) / Base (W) Count Register 6 */
    RegisterIoPort(0xCC, DmaReadPort, DmaWritePort);    /* Current(R) / Start(W) Address Register 7 */
    RegisterIoPort(0xCE, DmaReadPort, DmaWritePort);    /* Current(R) / Base (W) Count Register 7 */
 
    RegisterIoPort(0xD0, DmaReadPort, DmaWritePort);    /* Status (Read) / Command (Write) Registers */
    RegisterIoPort(0xD2,        NULL, DmaWritePort);    /* Request Register */
    RegisterIoPort(0xD4,        NULL, DmaWritePort);    /* Single Channel Mask Register */
    RegisterIoPort(0xD6,        NULL, DmaWritePort);    /* Mode Register */
    RegisterIoPort(0xD8,        NULL, DmaWritePort);    /* Flip-Flop Reset Register */
    RegisterIoPort(0xDA, DmaReadPort, DmaWritePort);    /* Intermediate (Read) / Master Reset (Write) Registers */
    RegisterIoPort(0xDC,        NULL, DmaWritePort);    /* Mask Reset Register */
    RegisterIoPort(0xDE, DmaReadPort, DmaWritePort);    /* Multi-Channel Mask Register */
 
 
    /* Channels Page Address Registers */
    RegisterIoPort(0x87, DmaPageReadPort, DmaPageWritePort);    /* Channel 0 (Reserved) */
    RegisterIoPort(0x83, DmaPageReadPort, DmaPageWritePort);    /* Channel 1 */
    RegisterIoPort(0x81, DmaPageReadPort, DmaPageWritePort);    /* Channel 2 */
    RegisterIoPort(0x82, DmaPageReadPort, DmaPageWritePort);    /* Channel 3 */
    RegisterIoPort(0x8F, DmaPageReadPort, DmaPageWritePort);    /* Channel 4 (Reserved) */
    RegisterIoPort(0x8B, DmaPageReadPort, DmaPageWritePort);    /* Channel 5 */
    RegisterIoPort(0x89, DmaPageReadPort, DmaPageWritePort);    /* Channel 6 */
    RegisterIoPort(0x8A, DmaPageReadPort, DmaPageWritePort);    /* Channel 7 */
}

Referenced by EmulatorInitialize().

DmaRequest()

DWORD DmaRequest	(	IN WORD	iChannel,
		IN OUT PVOID	Buffer,
		IN DWORD	length
	)

Definition at line 386 of file dma.c.

{
/*
 * NOTE: This function is adapted from Wine's krnl386.exe,
 * DMA emulation by Christian Costa.
 */
    PDMA_CONTROLLER pDcp;
    WORD Channel;
 
    DWORD i, Size, ret = 0;
    BYTE RegMode, OpMode, Increment, Autoinit, TrMode;
    PBYTE dmabuf = Buffer;
 
    ULONG CurrAddress;
 
    if (iChannel >= DMA_CONTROLLERS * DMA_CONTROLLER_CHANNELS)
    {
        SetLastError(ERROR_INVALID_ADDRESS);
        return 0;
    }
 
    pDcp    = &DmaControllers[iChannel / DMA_CONTROLLER_CHANNELS];
    Channel = iChannel % DMA_CONTROLLER_CHANNELS; // == (iChannel & 0x03)
 
    RegMode = pDcp->DmaChannel[Channel].Mode;
 
    DPRINT1("DMA_Command = %x length=%d\n", RegMode, length);
 
    /* Exit if the controller is disabled or the channel is masked */
    if ((pDcp->Command & 0x04) || (pDcp->Mask & (1 << Channel)))
        return 0;
 
    OpMode    =  (RegMode & 0xC0) >> 6;
    Increment = !(RegMode & 0x20);
    Autoinit  =   RegMode & 0x10;
    TrMode    =  (RegMode & 0x0C) >> 2;
 
    /* Process operating mode */
    switch (OpMode)
    {
        case 0:
            /* Request mode */
            DPRINT1("Request Mode - Not Implemented\n");
            return 0;
        case 1:
            /* Single Mode */
            break;
        case 2:
            /* Request mode */
            DPRINT1("Block Mode - Not Implemented\n");
            return 0;
        case 3:
            /* Cascade Mode */
            DPRINT1("Cascade Mode should not be used by regular apps\n");
            return 0;
    }
 
    /* Perform one the 4 transfer modes */
    if (TrMode == 4)
    {
        /* Illegal */
        DPRINT1("DMA Transfer Type Illegal\n");
        return 0;
    }
 
    /* Transfer size : 8 bits for channels 0..3, 16 bits for channels 4..7 */
    Size = (iChannel < 4) ? sizeof(BYTE) : sizeof(WORD);
 
    // FIXME: Handle wrapping?
    /* Get the number of elements to transfer */
    ret = min(pDcp->DmaChannel[Channel].CurrElemCnt, length / Size);
    length = ret * Size;
 
    /* 16-bit mode addressing, see: http://wiki.osdev.org/ISA_DMA#16_bit_issues */
    CurrAddress = (iChannel < 4) ? (DmaPageRegisters[iChannel].Page << 16) | ((pDcp->DmaChannel[Channel].CurrAddress << 0) & 0xFFFF)
                                 : (DmaPageRegisters[iChannel].Page << 16) | ((pDcp->DmaChannel[Channel].CurrAddress << 1) & 0xFFFF);
 
    switch (TrMode)
    {
        /* Verification (no real transfer) */
        case 0:
        {
            DPRINT1("Verification DMA operation\n");
            break;
        }
 
        /* Write */
        case 1:
        {
            DPRINT1("Perform Write transfer of %d elements (%d bytes) at 0x%x %s with count %x\n",
                    ret, length, CurrAddress, Increment ? "up" : "down", pDcp->DmaChannel[Channel].CurrElemCnt);
 
            if (Increment)
            {
                EmulatorWriteMemory(&EmulatorContext, CurrAddress, dmabuf, length);
            }
            else
            {
                for (i = 0; i < length; i++)
                {
                    EmulatorWriteMemory(&EmulatorContext, CurrAddress - i, dmabuf + i, sizeof(BYTE));
                }
            }
 
            break;
        }
 
        /* Read */
        case 2:
        {
            DPRINT1("Perform Read transfer of %d elements (%d bytes) at 0x%x %s with count %x\n",
                    ret, length, CurrAddress, Increment ? "up" : "down", pDcp->DmaChannel[Channel].CurrElemCnt);
 
            if (Increment)
            {
                EmulatorReadMemory(&EmulatorContext, CurrAddress, dmabuf, length);
            }
            else
            {
                for (i = 0; i < length; i++)
                {
                    EmulatorReadMemory(&EmulatorContext, CurrAddress - i, dmabuf + i, sizeof(BYTE));
                }
            }
 
            break;
        }
    }
 
    /* Update DMA registers */
    pDcp->DmaChannel[Channel].CurrElemCnt -= ret;
    if (Increment)
        pDcp->DmaChannel[Channel].CurrAddress += ret;
    else
        pDcp->DmaChannel[Channel].CurrAddress -= ret;
 
    /* Check for end of transfer */
    if (pDcp->DmaChannel[Channel].CurrElemCnt == 0)
    {
        DPRINT1("DMA buffer empty\n");
 
        /* Update status register of the DMA chip corresponding to the channel */
        pDcp->Status |=   1 <<  Channel;       /* Mark transfer as finished */
        pDcp->Status &= ~(1 << (Channel + 4)); /* Reset soft request if any */
 
        if (Autoinit)
        {
            /* Reload Current* registers to their initial values */
            pDcp->DmaChannel[Channel].CurrAddress = pDcp->DmaChannel[Channel].BaseAddress;
            pDcp->DmaChannel[Channel].CurrElemCnt = pDcp->DmaChannel[Channel].BaseElemCnt;
        }
        else
        {
            /* Set the mask bit for the channel */
            pDcp->Mask |= (1 << Channel);
        }
    }
 
    return length;
}

Referenced by VDDRequestDMA().