halinit.c File Reference

#include <hal.h>
#include "apicp.h"
#include <smp.h>
#include <debug.h>

Include dependency graph for halinit.c:

Go to the source code of this file.

Macros
#define	NDEBUG

Functions
VOID NTAPI	ApicInitializeLocalApic (ULONG Cpu)
VOID NTAPI	HalpInitProcessor (IN ULONG ProcessorNumber, IN PLOADER_PARAMETER_BLOCK LoaderBlock)
VOID	HalpInitPhase0 (IN PLOADER_PARAMETER_BLOCK LoaderBlock)
VOID	HalpInitPhase1 (VOID)

Macro Definition Documentation

NDEBUG

#define NDEBUG

Definition at line 13 of file halinit.c.

Function Documentation

ApicInitializeLocalApic()

VOID NTAPI ApicInitializeLocalApic

(

ULONG

Cpu

)

Definition at line 292 of file apic.c.

{
    APIC_BASE_ADDRESS_REGISTER BaseRegister;
    APIC_SPURIOUS_INERRUPT_REGISTER SpIntRegister;
    LVT_REGISTER LvtEntry;
 
    /* Enable the APIC if it wasn't yet */
    BaseRegister.LongLong = __readmsr(MSR_APIC_BASE);
    BaseRegister.Enable = 1;
    BaseRegister.BootStrapCPUCore = (Cpu == 0);
    __writemsr(MSR_APIC_BASE, BaseRegister.LongLong);
 
    /* Set spurious vector and SoftwareEnable to 1 */
    SpIntRegister.Long = ApicRead(APIC_SIVR);
    SpIntRegister.Vector = APIC_SPURIOUS_VECTOR;
    SpIntRegister.SoftwareEnable = 1;
    SpIntRegister.FocusCPUCoreChecking = 0;
    ApicWrite(APIC_SIVR, SpIntRegister.Long);
 
    /* Read the version and save it globally */
    if (Cpu == 0) ApicVersion = ApicRead(APIC_VER);
 
    /* Set the mode to flat (max 8 CPUs supported!) */
    ApicWrite(APIC_DFR, APIC_DF_Flat);
 
    /* Set logical apic ID */
    ApicWrite(APIC_LDR, ApicLogicalId(Cpu) << 24);
 
    /* Set the spurious ISR */
    KeRegisterInterruptHandler(APIC_SPURIOUS_VECTOR, ApicSpuriousService);
 
    /* Create a template LVT */
    LvtEntry.Long = 0;
    LvtEntry.Vector = APIC_FREE_VECTOR;
    LvtEntry.MessageType = APIC_MT_Fixed;
    LvtEntry.DeliveryStatus = 0;
    LvtEntry.RemoteIRR = 0;
    LvtEntry.TriggerMode = APIC_TGM_Edge;
    LvtEntry.Mask = 1;
    LvtEntry.TimerMode = 0;
 
    /* Initialize and mask LVTs */
    ApicWrite(APIC_TMRLVTR, LvtEntry.Long);
    ApicWrite(APIC_THRMLVTR, LvtEntry.Long);
    ApicWrite(APIC_PCLVTR, LvtEntry.Long);
    ApicWrite(APIC_EXT0LVTR, LvtEntry.Long);
    ApicWrite(APIC_EXT1LVTR, LvtEntry.Long);
    ApicWrite(APIC_EXT2LVTR, LvtEntry.Long);
    ApicWrite(APIC_EXT3LVTR, LvtEntry.Long);
 
    /* LINT0 */
    LvtEntry.Vector = APIC_SPURIOUS_VECTOR;
    LvtEntry.MessageType = APIC_MT_ExtInt;
    ApicWrite(APIC_LINT0, LvtEntry.Long);
 
    /* Enable LINT1 (NMI) */
    LvtEntry.Mask = 0;
    LvtEntry.Vector = APIC_NMI_VECTOR;
    LvtEntry.MessageType = APIC_MT_NMI;
    LvtEntry.TriggerMode = APIC_TGM_Level;
    ApicWrite(APIC_LINT1, LvtEntry.Long);
 
    /* Enable error LVTR */
    LvtEntry.Vector = APIC_ERROR_VECTOR;
    LvtEntry.MessageType = APIC_MT_Fixed;
    ApicWrite(APIC_ERRLVTR, LvtEntry.Long);
 
    /* Set the IRQL from the PCR */
    ApicSetIrql(KeGetPcr()->Irql);
#ifdef APIC_LAZY_IRQL
    /* Save the new hard IRQL in the IRR field */
    KeGetPcr()->IRR = KeGetPcr()->Irql;
#endif
}

Referenced by HalpInitProcessor().

HalpInitPhase0()

VOID HalpInitPhase0

(

IN PLOADER_PARAMETER_BLOCK

LoaderBlock

)

Definition at line 46 of file halinit.c.

{
    DPRINT1("Using HAL: APIC %s %s\n",
            (HalpBuildType & PRCB_BUILD_UNIPROCESSOR) ? "UP" : "SMP",
            (HalpBuildType & PRCB_BUILD_DEBUG) ? "DBG" : "REL");
 
    HalpPrintApicTables();
 
    /* Enable clock interrupt handler */
    HalpEnableInterruptHandler(IDT_INTERNAL,
                               0,
                               APIC_CLOCK_VECTOR,
                               CLOCK2_LEVEL,
                               HalpClockInterrupt,
                               Latched);
 
    /* Enable profile interrupt handler */
    HalpEnableInterruptHandler(IDT_DEVICE,
                               0,
                               APIC_PROFILE_VECTOR,
                               APIC_PROFILE_LEVEL,
                               HalpProfileInterrupt,
                               Latched);
}

HalpInitPhase1()

VOID HalpInitPhase1

(

VOID

)

Definition at line 72 of file halinit.c.

{
    /* Initialize DMA. NT does this in Phase 0 */
    HalpInitDma();
}

HalpInitProcessor()

VOID NTAPI HalpInitProcessor	(	IN ULONG	ProcessorNumber,
		IN PLOADER_PARAMETER_BLOCK	LoaderBlock
	)

Definition at line 24 of file halinit.c.

{
    if (ProcessorNumber == 0)
    {
        HalpParseApicTables(LoaderBlock);
    }
 
    HalpSetupProcessorsTable(ProcessorNumber);
 
    /* Initialize the local APIC for this cpu */
    ApicInitializeLocalApic(ProcessorNumber);
 
    /* Initialize profiling data (but don't start it) */
    HalInitializeProfiling();
 
    /* Initialize the timer */
    //ApicInitializeTimer(ProcessorNumber);
}

Referenced by HalInitializeProcessor().