ReactOS 0.4.15-dev-7677-g8209aa5
halinit.c File Reference
#include <hal.h>
#include "apicp.h"
#include <smp.h>
#include <debug.h>
Include dependency graph for halinit.c:

Go to the source code of this file.

Macros

#define NDEBUG
 

Functions

VOID NTAPI ApicInitializeLocalApic (ULONG Cpu)
 
VOID NTAPI HalpInitProcessor (IN ULONG ProcessorNumber, IN PLOADER_PARAMETER_BLOCK LoaderBlock)
 
VOID HalpInitPhase0 (IN PLOADER_PARAMETER_BLOCK LoaderBlock)
 
VOID HalpInitPhase1 (VOID)
 

Macro Definition Documentation

◆ NDEBUG

#define NDEBUG

Definition at line 13 of file halinit.c.

Function Documentation

◆ ApicInitializeLocalApic()

VOID NTAPI ApicInitializeLocalApic ( ULONG  Cpu)

Definition at line 291 of file apic.c.

292{
293 APIC_BASE_ADDRESS_REGISTER BaseRegister;
295 LVT_REGISTER LvtEntry;
296
297 /* Enable the APIC if it wasn't yet */
298 BaseRegister.LongLong = __readmsr(MSR_APIC_BASE);
299 BaseRegister.Enable = 1;
300 BaseRegister.BootStrapCPUCore = (Cpu == 0);
301 __writemsr(MSR_APIC_BASE, BaseRegister.LongLong);
302
303 /* Set spurious vector and SoftwareEnable to 1 */
304 SpIntRegister.Long = ApicRead(APIC_SIVR);
305 SpIntRegister.Vector = APIC_SPURIOUS_VECTOR;
306 SpIntRegister.SoftwareEnable = 1;
307 SpIntRegister.FocusCPUCoreChecking = 0;
308 ApicWrite(APIC_SIVR, SpIntRegister.Long);
309
310 /* Read the version and save it globally */
311 if (Cpu == 0) ApicVersion = ApicRead(APIC_VER);
312
313 /* Set the mode to flat (max 8 CPUs supported!) */
315
316 /* Set logical apic ID */
317 ApicWrite(APIC_LDR, ApicLogicalId(Cpu) << 24);
318
319 /* Set the spurious ISR */
321
322 /* Create a template LVT */
323 LvtEntry.Long = 0;
324 LvtEntry.Vector = APIC_FREE_VECTOR;
325 LvtEntry.MessageType = APIC_MT_Fixed;
326 LvtEntry.DeliveryStatus = 0;
327 LvtEntry.RemoteIRR = 0;
328 LvtEntry.TriggerMode = APIC_TGM_Edge;
329 LvtEntry.Mask = 1;
330 LvtEntry.TimerMode = 0;
331
332 /* Initialize and mask LVTs */
333 ApicWrite(APIC_TMRLVTR, LvtEntry.Long);
334 ApicWrite(APIC_THRMLVTR, LvtEntry.Long);
335 ApicWrite(APIC_PCLVTR, LvtEntry.Long);
336 ApicWrite(APIC_EXT0LVTR, LvtEntry.Long);
337 ApicWrite(APIC_EXT1LVTR, LvtEntry.Long);
338 ApicWrite(APIC_EXT2LVTR, LvtEntry.Long);
339 ApicWrite(APIC_EXT3LVTR, LvtEntry.Long);
340
341 /* LINT0 */
342 LvtEntry.Vector = APIC_SPURIOUS_VECTOR;
343 LvtEntry.MessageType = APIC_MT_ExtInt;
344 ApicWrite(APIC_LINT0, LvtEntry.Long);
345
346 /* Enable LINT1 (NMI) */
347 LvtEntry.Mask = 0;
348 LvtEntry.Vector = APIC_NMI_VECTOR;
349 LvtEntry.MessageType = APIC_MT_NMI;
350 LvtEntry.TriggerMode = APIC_TGM_Level;
351 ApicWrite(APIC_LINT1, LvtEntry.Long);
352
353 /* Enable error LVTR */
354 LvtEntry.Vector = APIC_ERROR_VECTOR;
355 LvtEntry.MessageType = APIC_MT_Fixed;
356 ApicWrite(APIC_ERRLVTR, LvtEntry.Long);
357
358 /* Set the IRQL from the PCR */
360#ifdef APIC_LAZY_IRQL
361 /* Save the new hard IRQL in the IRR field */
362 KeGetPcr()->IRR = KeGetPcr()->Irql;
363#endif
364}
ULONG ApicVersion
Definition: apic.c:27
FORCEINLINE VOID ApicSetIrql(KIRQL Irql)
Definition: apic.c:221
#define MSR_APIC_BASE
Definition: apicp.h:113
@ APIC_DF_Flat
Definition: apicp.h:160
#define APIC_NMI_VECTOR
Definition: apicp.h:51
#define APIC_FREE_VECTOR
Definition: apicp.h:59
@ APIC_MT_Fixed
Definition: apicp.h:124
@ APIC_MT_NMI
Definition: apicp.h:128
@ APIC_MT_ExtInt
Definition: apicp.h:131
#define APIC_SPURIOUS_VECTOR
Definition: apicp.h:40
#define APIC_ERROR_VECTOR
Definition: apicp.h:47
#define ApicLogicalId(Cpu)
Definition: apicp.h:116
VOID __cdecl ApicSpuriousService(VOID)
FORCEINLINE ULONG ApicRead(APIC_REGISTER Register)
Definition: apicp.h:315
FORCEINLINE VOID ApicWrite(APIC_REGISTER Register, ULONG Value)
Definition: apicp.h:322
@ APIC_LINT1
Definition: apicp.h:99
@ APIC_EXT3LVTR
Definition: apicp.h:110
@ APIC_EXT1LVTR
Definition: apicp.h:108
@ APIC_VER
Definition: apicp.h:80
@ APIC_LDR
Definition: apicp.h:86
@ APIC_ERRLVTR
Definition: apicp.h:100
@ APIC_PCLVTR
Definition: apicp.h:97
@ APIC_EXT2LVTR
Definition: apicp.h:109
@ APIC_THRMLVTR
Definition: apicp.h:96
@ APIC_TMRLVTR
Definition: apicp.h:95
@ APIC_DFR
Definition: apicp.h:87
@ APIC_LINT0
Definition: apicp.h:98
@ APIC_SIVR
Definition: apicp.h:88
@ APIC_EXT0LVTR
Definition: apicp.h:107
@ APIC_TGM_Level
Definition: apicp.h:138
@ APIC_TGM_Edge
Definition: apicp.h:137
_Out_ PKIRQL Irql
Definition: csq.h:179
PPC_QUAL void __writemsr(const unsigned long Value)
Definition: intrin_ppc.h:748
PPC_QUAL unsigned long long __readmsr()
Definition: intrin_ppc.h:741
FORCEINLINE VOID KeRegisterInterruptHandler(IN ULONG Vector, IN PVOID Handler)
Definition: ke.h:301
#define KeGetPcr()
Definition: ke.h:26
UINT32 RemoteIRR
Definition: apicp.h:271
UINT32 MessageType
Definition: apicp.h:267
UINT32 TimerMode
Definition: apicp.h:274
UINT32 Long
Definition: apicp.h:263
UINT32 Vector
Definition: apicp.h:266
UINT32 Mask
Definition: apicp.h:273
UINT32 TriggerMode
Definition: apicp.h:272
UINT32 DeliveryStatus
Definition: apicp.h:269

Referenced by HalpInitProcessor().

◆ HalpInitPhase0()

VOID HalpInitPhase0 ( IN PLOADER_PARAMETER_BLOCK  LoaderBlock)

Definition at line 46 of file halinit.c.

47{
48 DPRINT1("Using HAL: APIC %s %s\n",
49 (HalpBuildType & PRCB_BUILD_UNIPROCESSOR) ? "UP" : "SMP",
50 (HalpBuildType & PRCB_BUILD_DEBUG) ? "DBG" : "REL");
51
53
54 /* Enable clock interrupt handler */
56 0,
60 Latched);
61}
#define APIC_CLOCK_VECTOR
Definition: apicp.h:44
#define DPRINT1
Definition: precomp.h:8
const USHORT HalpBuildType
Definition: buildtype.c:14
#define CLOCK2_LEVEL
Definition: env_spec_w32.h:700
VOID HalpClockInterrupt(VOID)
Definition: timer.c:30
VOID NTAPI HalpEnableInterruptHandler(IN UCHAR Flags, IN ULONG BusVector, IN ULONG SystemVector, IN KIRQL Irql, IN PVOID Handler, IN KINTERRUPT_MODE Mode)
Definition: usage.c:49
#define IDT_INTERNAL
Definition: halp.h:21
VOID HalpPrintApicTables(VOID)
Definition: madt.c:76
#define PRCB_BUILD_UNIPROCESSOR
Definition: ketypes.h:309
#define PRCB_BUILD_DEBUG
Definition: ketypes.h:308
@ Latched
Definition: miniport.h:81

◆ HalpInitPhase1()

VOID HalpInitPhase1 ( VOID  )

Definition at line 64 of file halinit.c.

65{
66 /* Initialize DMA. NT does this in Phase 0 */
68}
VOID HalpInitDma(VOID)
Definition: dma.c:185

◆ HalpInitProcessor()

VOID NTAPI HalpInitProcessor ( IN ULONG  ProcessorNumber,
IN PLOADER_PARAMETER_BLOCK  LoaderBlock 
)

Definition at line 24 of file halinit.c.

27{
28 if (ProcessorNumber == 0)
29 {
30 HalpParseApicTables(LoaderBlock);
31 }
32
33 HalpSetupProcessorsTable(ProcessorNumber);
34
35 /* Initialize the local APIC for this cpu */
36 ApicInitializeLocalApic(ProcessorNumber);
37
38 /* Initialize profiling data (but don't start it) */
40
41 /* Initialize the timer */
42 //ApicInitializeTimer(ProcessorNumber);
43}
VOID NTAPI HalInitializeProfiling(VOID)
Definition: apictimer.c:76
VOID NTAPI ApicInitializeLocalApic(ULONG Cpu)
Definition: apic.c:291
VOID HalpParseApicTables(_In_ PLOADER_PARAMETER_BLOCK LoaderBlock)
Definition: madt.c:30
VOID HalpSetupProcessorsTable(_In_ UINT32 NTProcessorNumber)
Definition: up.c:37

Referenced by HalInitializeProcessor().