23#define TIMEOUT_COUNT 1024 * 200
48 for (
i = 0;
i < 3;
i++)
51 for (
i = 0;
i < 3;
i++)
62 for (
i = 0;
i < 6;
i++)
396 if (!(Lsr & ExpectedValue))
409 if (!(Lsr & ExpectedValue))
426 if (!(Lsr & ExpectedValue))
452 UCHAR SuccessFlags, ErrorFlags;
470 if (Lsr & SuccessFlags)
473 if (Lsr & ErrorFlags)
VOID NTAPI CpPutByte(IN PCPPORT Port, IN UCHAR Byte)
NTSTATUS NTAPI CpInitialize(IN PCPPORT Port, IN PUCHAR Address, IN ULONG BaudRate)
VOID NTAPI CpEnableFifo(IN PUCHAR Address, IN BOOLEAN Enable)
static struct @4300 Rs232ComPort[]
static BOOLEAN CpIsNekoProject(VOID)
USHORT NTAPI CpGetByte(IN PCPPORT Port, OUT PUCHAR Byte, IN BOOLEAN Wait, IN BOOLEAN Poll)
VOID NTAPI CpSetBaud(IN PCPPORT Port, IN ULONG BaudRate)
static BOOLEAN ComPortTest2(IN PUCHAR Address)
static BOOLEAN ComPortTest1(IN PUCHAR Address)
static BOOLEAN IsNekoProject
BOOLEAN NTAPI CpDoesPortExist(IN PUCHAR Address)
UCHAR NTAPI CpReadLsr(IN PCPPORT Port, IN UCHAR ExpectedValue)
#define CPPORT_FLAG_MODEM_CONTROL
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
_In_ ULONGLONG _In_ ULONGLONG _In_ BOOLEAN Enable
#define READ_PORT_UCHAR(p)
#define WRITE_PORT_UCHAR(p, d)
#define CPU_IO_o_ARTIC_DELAY
#define TIMER_FREQUENCY_1
FORCEINLINE VOID Write8253Timer(TIMER_CONTROL_PORT_REGISTER TimerControl, USHORT Count)
#define TIMER_FREQUENCY_2
#define SER1_IO_o_TRANSMITTER_BUFFER
#define SER1_COMMMAND_DTR
#define SER1_STATUS_RxRDY
#define SER1_IO_i_LINE_STATUS
#define SER1_IO_i_INTERRUPT_ID
#define SER2_MCR_RTS_STATE
#define SER2_IO_o_TRANSMITTER_BUFFER
#define SER1_COMMMAND_RTS
#define SER2_IO_o_FIFO_CONTROL
#define SER1_MODE_CLOCKx16
#define SER2_IO_o_DIVISOR_LATCH_LSB
#define SER2_IO_i_LINE_STATUS
#define SER2_LCR_NO_PARITY
#define SER1_COMMMAND_TxEN
#define SER2_LCR_LENGTH_8
#define SER1_IO_o_DIVISOR_LATCH
#define SER2_IO_o_DIVISOR_LATCH_MSB
#define SER1_IO_i_RECEIVER_BUFFER
#define SER2_LSR_THR_EMPTY
#define SER2_IO_o_SCRATCH
#define SER2_MCR_DTR_STATE
#define SER1_IO_o_MODE_COMMAND
#define SER1_DLR_MODE_LEGACY
#define SER2_MCR_LOOPBACK
#define SER2_IO_i_MODEM_CONTROL
#define SER1_MODE_LENGTH_8
#define SER2_IO_i_MODEM_STATUS
#define SER2_IO_i_LINE_CONTROL
#define SER2_IO_o_INTERRUPT_EN
#define SER2_IO_i_SCRATCH
#define SER1_IO_i_MODEM_STATUS
#define SER1_COMMMAND_RxEN
#define SER2_IO_o_LINE_CONTROL
#define SER_FCR_TXMT_RESET
#define SER1_IIR_FIFOS_ENABLED
#define SER2_IIR_HAS_FIFO
#define SER_FCR_RCVR_RESET
#define SER1_STATUS_TxRDY
#define SER2_IO_i_INTERRUPT_ID
#define SER2_IO_o_MODEM_CONTROL
#define SER1_IO_o_FIFO_CONTROL
#define SER2_IO_i_RECEIVER_BUFFER
#define STATUS_INVALID_PARAMETER
UCHAR InterruptEnableTxReady
UCHAR InterruptEnableRxReady
UCHAR InterruptEnableTxEmpty
_In_ WDFDPC _In_ BOOLEAN Wait