ReactOS  0.4.15-dev-4921-g25fcdc5
cport_pc98.c
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1 /*
2  * PROJECT: ReactOS ComPort Library for NEC PC-98 series
3  * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
4  * PURPOSE: Provides a serial port library for KDCOM, INIT, and FREELDR
5  * COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
6  */
7 
8 /* Note: ns16550 code from cportlib.c */
9 
10 /* INCLUDES *******************************************************************/
11 
12 #include <intrin.h>
13 #include <ioaccess.h>
14 #include <ntstatus.h>
15 #include <cportlib/cportlib.h>
16 #include <drivers/pc98/serial.h>
17 #include <drivers/pc98/sysport.h>
18 #include <drivers/pc98/pit.h>
19 #include <drivers/pc98/cpu.h>
20 
21 /* GLOBALS ********************************************************************/
22 
23 #define TIMEOUT_COUNT 1024 * 200
24 
25 static struct
26 {
31 } Rs232ComPort[] =
32 {
33  { (PUCHAR)0x030, FALSE, FALSE, 0 },
34  { (PUCHAR)0x238, FALSE, FALSE, 0 }
35 };
36 
38 
39 /* FUNCTIONS ******************************************************************/
40 
41 static BOOLEAN
43 {
44  UCHAR Input[4] = "NP2";
45  UCHAR Output[4] = {0};
46  UCHAR i;
47 
48  for (i = 0; i < 3; i++)
49  WRITE_PORT_UCHAR((PUCHAR)0x7EF, Input[i]);
50 
51  for (i = 0; i < 3; i++)
52  Output[i] = READ_PORT_UCHAR((PUCHAR)0x7EF);
53 
54  return (*(PULONG)Input == *(PULONG)Output);
55 }
56 
57 static VOID
59 {
60  UCHAR i;
61 
62  for (i = 0; i < 6; i++)
64 }
65 
66 VOID
67 NTAPI
71 {
72  /* Set FIFO and clear the receive/transmit buffers */
74  {
75  if (Enable)
78  else
80  Rs232ComPort[0].FifoEnabled = Enable;
81  }
82  else if (Address == Rs232ComPort[1].Address && Rs232ComPort[1].HasFifo)
83  {
84  if (Enable)
87  else
89  Rs232ComPort[1].FifoEnabled = Enable;
90  }
91  CpWait();
92 }
93 
94 VOID
95 NTAPI
97  IN PCPPORT Port,
98  IN ULONG BaudRate)
99 {
100  UCHAR Lcr;
101  USHORT Count;
102  TIMER_CONTROL_PORT_REGISTER TimerControl;
103 
104  if (Port->Address == Rs232ComPort[0].Address)
105  {
106  if (Rs232ComPort[0].HasFifo)
108 
109  TimerControl.BcdMode = FALSE;
110  TimerControl.OperatingMode = PitOperatingMode3;
111  TimerControl.AccessMode = PitAccessModeLowHigh;
112  TimerControl.Channel = PitChannel2;
113  if (IsNekoProject)
114  {
115  /* The horrible text input lag happens by about 6 seconds on my PC */
116  Count = 3;
117  }
118  else
119  {
120  Count = (READ_PORT_UCHAR((PUCHAR)0x42) & 0x20) ?
121  (TIMER_FREQUENCY_1 / (BaudRate * 16)) : (TIMER_FREQUENCY_2 / (BaudRate * 16));
122  }
123  Write8253Timer(TimerControl, Count);
124 
125  /* Save baud rate in port */
126  Port->BaudRate = BaudRate;
127  }
128  else if (Port->Address == Rs232ComPort[1].Address)
129  {
130  /* Set the DLAB on */
133 
134  /* Set the baud rate */
135  Count = SER2_CLOCK_RATE / BaudRate;
138 
139  /* Reset DLAB */
141 
142  /* Save baud rate in port */
143  Port->BaudRate = BaudRate;
144  }
145 }
146 
147 NTSTATUS
148 NTAPI
150  IN PCPPORT Port,
151  IN PUCHAR Address,
152  IN ULONG BaudRate)
153 {
154  SYSTEM_CONTROL_PORT_C_REGISTER SystemControl;
155  UCHAR FifoStatus;
156 
157  if (Port == NULL || Address == NULL || BaudRate == 0)
159 
160  if (!CpDoesPortExist(Address))
161  return STATUS_NOT_FOUND;
162 
163  /* Initialize port data */
164  Port->Address = Address;
165  Port->BaudRate = 0;
166  Port->Flags = 0;
167 
169 
170  if (Port->Address == Rs232ComPort[0].Address)
171  {
172  /* FIFO test */
174  CpWait();
176 
177  /* Disable the interrupts */
178  SystemControl.Bits = READ_PORT_UCHAR((PUCHAR)PPI_IO_i_PORT_C);
179  SystemControl.InterruptEnableRxReady = FALSE;
180  SystemControl.InterruptEnableTxEmpty = FALSE;
181  SystemControl.InterruptEnableTxReady = FALSE;
182  WRITE_PORT_UCHAR((PUCHAR)PPI_IO_o_PORT_C, SystemControl.Bits);
183 
184  /* Turn off FIFO */
185  if (Rs232ComPort[0].HasFifo)
187 
188  /* Set the baud rate */
189  CpSetBaud(Port, BaudRate);
190 
191  /* Software reset */
193  CpWait();
195  CpWait();
197  CpWait();
199  CpWait();
200 
201  /* Mode instruction - asynchronous mode, 8 data bits, 1 stop bit, no parity, 16x clock divisor */
204  CpWait();
205 
206  /* Command instruction - transmit enable, turn on DTR and RTS, receive enable, clear error flag */
210  CpWait();
211 
212  /* Disable the interrupts again */
213  WRITE_PORT_UCHAR((PUCHAR)PPI_IO_o_PORT_C, SystemControl.Bits);
214 
215  /* Turn on FIFO */
216  if (Rs232ComPort[0].HasFifo)
218 
219  /* Read junk out of the data register */
220  if (Rs232ComPort[0].HasFifo)
222  else
224 
225  return STATUS_SUCCESS;
226  }
227  else if (Port->Address == Rs232ComPort[1].Address)
228  {
229  /* Disable the interrupts */
232 
233  /* Turn on DTR, RTS and OUT2 */
236 
237  /* Set the baud rate */
238  CpSetBaud(Port, BaudRate);
239 
240  /* Set 8 data bits, 1 stop bit, no parity, no break */
243 
244  /* FIFO test */
246 
247  /* Turn on FIFO */
248  if (Rs232ComPort[1].HasFifo)
250 
251  /* Read junk out of the RBR */
253 
254  return STATUS_SUCCESS;
255  }
256 
257  return STATUS_NOT_FOUND;
258 }
259 
260 static BOOLEAN
262 {
263  /*
264  * See "Building Hardware and Firmware to Complement Microsoft Windows Headless Operation"
265  * Out-of-Band Management Port Device Requirements:
266  * The device must act as a 16550 or 16450 UART.
267  * Windows Server 2003 will test this device using the following process:
268  * 1. Save off the current modem status register.
269  * 2. Place the UART into diagnostic mode (The UART is placed into loopback mode
270  * by writing SERIAL_MCR_LOOP to the modem control register).
271  * 3. The modem status register is read and the high bits are checked. This means
272  * SERIAL_MSR_CTS, SERIAL_MSR_DSR, SERIAL_MSR_RI and SERIAL_MSR_DCD should
273  * all be clear.
274  * 4. Place the UART in diagnostic mode and turn on OUTPUT (Loopback Mode and
275  * OUTPUT are both turned on by writing (SERIAL_MCR_LOOP | SERIAL_MCR_OUT1)
276  * to the modem control register).
277  * 5. The modem status register is read and the ring indicator is checked.
278  * This means SERIAL_MSR_RI should be set.
279  * 6. Restore original modem status register.
280  *
281  * REMARK: Strangely enough, the Virtual PC 2007 virtual machine
282  * doesn't pass this test.
283  */
284 
285  BOOLEAN RetVal = FALSE;
286  UCHAR Mcr, Msr;
287 
288  /* Save the Modem Control Register */
290 
291  /* Enable loop (diagnostic) mode (set Bit 4 of the MCR) */
293 
294  /* Clear all modem output bits */
296 
297  /* Read the Modem Status Register */
299 
300  /*
301  * The upper nibble of the MSR (modem output bits) must be
302  * equal to the lower nibble of the MCR (modem input bits).
303  */
304  if ((Msr & (SER_MSR_CTS | SER_MSR_DSR | SER_MSR_RI | SER_MSR_DCD)) == 0x00)
305  {
306  /* Set all modem output bits */
308  SER2_MCR_OUT_1 | SER2_MCR_LOOPBACK); // Windows
309 /* ReactOS
310  WRITE_PORT_UCHAR((PUCHAR)SER2_IO_o_MODEM_CONTROL,
311  SER2_MCR_DTR_STATE | SER2_MCR_RTS_STATE |
312  SER2_MCR_OUT_1 | SER2_MCR_OUT_2 | SER2_MCR_LOOPBACK);
313 */
314 
315  /* Read the Modem Status Register */
317 
318  /*
319  * The upper nibble of the MSR (modem output bits) must be
320  * equal to the lower nibble of the MCR (modem input bits).
321  */
322  if (Msr & SER_MSR_RI) // Windows
323  // if (Msr & (SER_MSR_CTS | SER_MSR_DSR | SER_MSR_RI | SER_MSR_DCD) == 0xF0) // ReactOS
324  {
325  RetVal = TRUE;
326  }
327  }
328 
329  /* Restore the MCR */
331 
332  return RetVal;
333 }
334 
335 static BOOLEAN
337 {
338  /*
339  * This test checks whether the 16450/16550 scratch register is available.
340  * If not, the serial port is considered as unexisting.
341  */
342 
343  UCHAR Byte = 0;
344 
345  do
346  {
348 
350  return FALSE;
351 
352  }
353  while (++Byte != 0);
354 
355  return TRUE;
356 }
357 
358 BOOLEAN
359 NTAPI
361 {
362  UCHAR Data, Status;
363 
364  if (Address == Rs232ComPort[0].Address || Address == (PUCHAR)0x41)
365  {
368  if ((Data & Status) == 0xFF || (Data | Status) == 0x00)
369  return FALSE;
370  else
371  return TRUE;
372  }
373  else if (Address == Rs232ComPort[1].Address)
374  {
376  }
377 
378  return FALSE;
379 }
380 
381 UCHAR
382 NTAPI
384  IN PCPPORT Port,
385  IN UCHAR ExpectedValue)
386 {
387  UCHAR Lsr, Msr;
388  SYSTEM_CONTROL_PORT_B_REGISTER SystemControl;
389 
390  if (Port->Address == Rs232ComPort[0].Address)
391  {
392  /* Read the LSR and check if the expected value is present */
393  if (Rs232ComPort[0].HasFifo)
394  {
396  if (!(Lsr & ExpectedValue))
397  {
399 
400  /* If the ring indicator reaches 3, we've seen this on/off twice */
401  Rs232ComPort[0].RingIndicator |= (Msr & SER_MSR_RI) ? 1 : 2;
402  if (Rs232ComPort[0].RingIndicator == 3)
404  }
405  }
406  else
407  {
409  if (!(Lsr & ExpectedValue))
410  {
411  SystemControl.Bits = READ_PORT_UCHAR((PUCHAR)PPI_IO_i_PORT_B);
412 
413  /* If the ring indicator reaches 3, we've seen this on/off twice */
414  Rs232ComPort[0].RingIndicator |= SystemControl.RingIndicator ? 1 : 2;
415  if (Rs232ComPort[0].RingIndicator == 3)
417  }
418  }
419 
420  return Lsr;
421  }
422  else if (Port->Address == Rs232ComPort[1].Address)
423  {
424  /* Read the LSR and check if the expected value is present */
426  if (!(Lsr & ExpectedValue))
427  {
429 
430  /* If the indicator reaches 3, we've seen this on/off twice */
431  Rs232ComPort[1].RingIndicator |= (Msr & SER_MSR_RI) ? 1 : 2;
432  if (Rs232ComPort[1].RingIndicator == 3)
434  }
435 
436  return Lsr;
437  }
438 
439  return 0;
440 }
441 
442 USHORT
443 NTAPI
445  IN PCPPORT Port,
446  OUT PUCHAR Byte,
447  IN BOOLEAN Wait,
448  IN BOOLEAN Poll)
449 {
450  UCHAR Lsr;
451  ULONG LimitCount = Wait ? TIMEOUT_COUNT : 1;
452  UCHAR SuccessFlags, ErrorFlags;
454 
455  /* Handle early read-before-init */
456  if (!Port->Address)
457  return CP_GET_NODATA;
458 
459  if (Port->Address == Rs232ComPort[0].Address)
460  {
461  SuccessFlags = Rs232ComPort[0].HasFifo ? SER1_LSR_RxRDY : SER1_STATUS_RxRDY;
462  ErrorFlags = Rs232ComPort[0].HasFifo ? (SER1_LSR_PE | SER1_LSR_OE) :
464 
465  /* If "wait" mode enabled, spin many times, otherwise attempt just once */
466  while (LimitCount--)
467  {
468  /* Read LSR for data ready */
469  Lsr = CpReadLsr(Port, SuccessFlags);
470  if (Lsr & SuccessFlags)
471  {
472  /* If an error happened, clear the byte and fail */
473  if (Lsr & ErrorFlags)
474  {
475  /* Save the last FIFO state */
476  FifoEnabled = Rs232ComPort[0].FifoEnabled;
477 
478  /* Turn off FIFO */
479  if (FifoEnabled)
481 
482  /* Clear error flag */
486 
487  /* Turn on FIFO */
488  if (FifoEnabled)
490 
491  *Byte = 0;
492  return CP_GET_ERROR;
493  }
494 
495  /* If only polling was requested by caller, return now */
496  if (Poll)
497  return CP_GET_SUCCESS;
498 
499  /* Otherwise read the byte and return it */
500  if (Rs232ComPort[0].HasFifo)
502  else
504 
505  /* TODO: Handle CD if port is in modem control mode */
506 
507  /* Byte was read */
508  return CP_GET_SUCCESS;
509  }
510  else if (IsNekoProject && Rs232ComPort[0].HasFifo)
511  {
512  /*
513  * Neko Project 21/W doesn't set RxRDY without reading any data from 0x136.
514  * TODO: Check real hardware behavior.
515  */
517  }
518  }
519 
520  /* Reset LSR, no data was found */
521  CpReadLsr(Port, 0);
522  }
523  else if (Port->Address == Rs232ComPort[1].Address)
524  {
525  /* If "wait" mode enabled, spin many times, otherwise attempt just once */
526  while (LimitCount--)
527  {
528  /* Read LSR for data ready */
529  Lsr = CpReadLsr(Port, SER2_LSR_DR);
530  if ((Lsr & SER2_LSR_DR) == SER2_LSR_DR)
531  {
532  /* If an error happened, clear the byte and fail */
533  if (Lsr & (SER2_LSR_FE | SER2_LSR_PE | SER2_LSR_OE))
534  {
535  *Byte = 0;
536  return CP_GET_ERROR;
537  }
538 
539  /* If only polling was requested by caller, return now */
540  if (Poll)
541  return CP_GET_SUCCESS;
542 
543  /* Otherwise read the byte and return it */
545 
546  /* TODO: Handle CD if port is in modem control mode */
547 
548  /* Byte was read */
549  return CP_GET_SUCCESS;
550  }
551  }
552 
553  /* Reset LSR, no data was found */
554  CpReadLsr(Port, 0);
555  }
556 
557  return CP_GET_NODATA;
558 }
559 
560 VOID
561 NTAPI
563  IN PCPPORT Port,
564  IN UCHAR Byte)
565 {
566  if (Port->Address == Rs232ComPort[0].Address)
567  {
568  /* TODO: Check if port is in modem control to handle CD */
569 
570  if (Rs232ComPort[0].HasFifo)
571  {
572  while ((CpReadLsr(Port, SER1_LSR_TxRDY) & SER1_LSR_TxRDY) == 0)
573  NOTHING;
574 
576  }
577  else
578  {
580  NOTHING;
581 
583  }
584  }
585  else if (Port->Address == Rs232ComPort[1].Address)
586  {
587  /* TODO: Check if port is in modem control to handle CD */
588 
590  NOTHING;
591 
593  }
594 }
#define SER1_IO_o_FIFO_CONTROL
Definition: serial.h:86
CPPORT Port[4]
Definition: headless.c:35
BOOLEAN NTAPI CpDoesPortExist(IN PUCHAR Address)
Definition: cport_pc98.c:360
#define IN
Definition: typedefs.h:39
#define SER2_IO_i_SCRATCH
Definition: serial.h:135
#define SER2_MCR_RTS_STATE
Definition: serial.h:177
#define CP_GET_ERROR
Definition: cportlib.h:20
#define SER1_STATUS_TxRDY
Definition: serial.h:17
#define SER1_STATUS_RxRDY
Definition: serial.h:18
#define SER_MSR_RI
Definition: serial.h:40
#define SER2_IO_i_MODEM_CONTROL
Definition: serial.h:123
#define SER2_IIR_HAS_FIFO
Definition: serial.h:120
#define READ_PORT_UCHAR(p)
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#define SER1_IO_i_RECEIVER_BUFFER
Definition: serial.h:25
#define TIMEOUT_COUNT
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#define TRUE
Definition: types.h:120
#define SER_MSR_DCD
Definition: serial.h:41
#define STATUS_INVALID_PARAMETER
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BOOLEAN FifoEnabled
Definition: cport_pc98.c:29
_In_ WDFDPC _In_ BOOLEAN Wait
Definition: wdfdpc.h:167
#define SER2_MCR_OUT_2
Definition: serial.h:179
unsigned char * PUCHAR
Definition: retypes.h:3
BOOLEAN HasFifo
Definition: cport_pc98.c:28
_Must_inspect_result_ _In_ WDFDEVICE _In_ PWDF_DEVICE_PROPERTY_DATA _In_ DEVPROPTYPE _In_ ULONG _In_opt_ PVOID Data
Definition: wdfdevice.h:4527
LONG NTSTATUS
Definition: precomp.h:26
_In_ ULONGLONG _In_ ULONGLONG _In_ BOOLEAN Enable
Definition: ntddpcm.h:140
#define SER1_STATUS_OE
Definition: serial.h:21
Definition: arc.h:84
#define SER1_COMMMAND_IR
Definition: serial.h:83
#define SER1_COMMMAND_DTR
Definition: serial.h:78
FORCEINLINE VOID Write8253Timer(TIMER_CONTROL_PORT_REGISTER TimerControl, USHORT Count)
Definition: pit.h:90
UCHAR NTAPI CpReadLsr(IN PCPPORT Port, IN UCHAR ExpectedValue)
Definition: cport_pc98.c:383
#define SER1_IIR_FIFOS_ENABLED
Definition: serial.h:51
#define SER_MSR_DSR
Definition: serial.h:39
#define SER2_IO_o_INTERRUPT_EN
Definition: serial.h:150
static BOOLEAN ComPortTest2(IN PUCHAR Address)
Definition: cport_pc98.c:336
#define SER2_IO_o_MODEM_CONTROL
Definition: serial.h:175
#define SER2_LSR_THR_EMPTY
Definition: serial.h:130
#define SER1_LSR_RxRDY
Definition: serial.h:29
#define SER2_IO_o_TRANSMITTER_BUFFER
Definition: serial.h:137
#define PPI_IO_o_PORT_C
Definition: sysport.h:10
#define SER1_LSR_TxRDY
Definition: serial.h:28
#define SER2_LSR_DR
Definition: serial.h:125
#define SER2_IO_o_LINE_CONTROL
Definition: serial.h:158
#define SER1_IO_i_INTERRUPT_ID
Definition: serial.h:42
#define SER1_IO_o_DIVISOR_LATCH
Definition: serial.h:96
#define SER2_IO_i_MODEM_STATUS
Definition: serial.h:133
NTSTATUS(* NTAPI)(IN PFILE_FULL_EA_INFORMATION EaBuffer, IN ULONG EaLength, OUT PULONG ErrorOffset)
Definition: IoEaTest.cpp:117
USHORT NTAPI CpGetByte(IN PCPPORT Port, OUT PUCHAR Byte, IN BOOLEAN Wait, IN BOOLEAN Poll)
Definition: cport_pc98.c:444
#define FALSE
Definition: types.h:117
#define SER1_IO_o_DATA
Definition: serial.h:55
#define SER1_LSR_OE
Definition: serial.h:30
USHORT Flags
Definition: cportlib.h:31
#define SER2_LCR_DLAB
Definition: serial.h:174
#define SER2_IO_i_LINE_STATUS
Definition: serial.h:124
#define SER2_LCR_NO_PARITY
Definition: serial.h:168
static VOID CpWait(VOID)
Definition: cport_pc98.c:58
static BOOLEAN IsNekoProject
Definition: cport_pc98.c:37
VOID NTAPI CpSetBaud(IN PCPPORT Port, IN ULONG BaudRate)
Definition: cport_pc98.c:96
#define SER_MSR_CTS
Definition: serial.h:38
unsigned char BOOLEAN
#define SER2_CLOCK_RATE
Definition: serial.h:184
#define SER2_IO_o_FIFO_CONTROL
Definition: serial.h:155
#define SER1_IO_i_MODEM_STATUS
Definition: serial.h:33
#define SER1_STATUS_FE
Definition: serial.h:22
#define SER2_LCR_LENGTH_8
Definition: serial.h:163
static BOOLEAN CpIsNekoProject(VOID)
Definition: cport_pc98.c:42
Status
Definition: gdiplustypes.h:24
static struct @4073 Rs232ComPort[]
#define STATUS_NOT_FOUND
Definition: shellext.h:72
int Count
Definition: noreturn.cpp:7
#define SER1_IO_o_TRANSMITTER_BUFFER
Definition: serial.h:85
#define SER1_IO_i_LINE_STATUS
Definition: serial.h:26
UCHAR RingIndicator
Definition: cport_pc98.c:30
#define SER1_DLR_MODE_LEGACY
Definition: serial.h:105
#define SER2_MCR_DTR_STATE
Definition: serial.h:176
#define SER_FCR_ENABLE
Definition: serial.h:88
#define SER2_LSR_PE
Definition: serial.h:127
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Definition: sysport.h:20
#define SER1_COMMMAND_ER
Definition: serial.h:81
#define SER2_LSR_OE
Definition: serial.h:126
#define SER_FCR_RCVR_RESET
Definition: serial.h:89
unsigned char UCHAR
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#define SER2_MCR_LOOPBACK
Definition: serial.h:180
NTSTATUS NTAPI CpInitialize(IN PCPPORT Port, IN PUCHAR Address, IN ULONG BaudRate)
Definition: cport_pc98.c:149
#define WRITE_PORT_UCHAR(p, d)
Definition: pc98vid.h:21
Definition: arc.h:85
#define VOID
Definition: acefi.h:82
#define SER2_IO_o_SCRATCH
Definition: serial.h:182
#define NOTHING
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#define SER2_IO_i_RECEIVER_BUFFER
Definition: serial.h:112
PUCHAR Address
Definition: cportlib.h:29
PUCHAR Address
Definition: cport_pc98.c:27
#define TIMER_FREQUENCY_1
Definition: pit.h:16
#define SER1_COMMMAND_RTS
Definition: serial.h:82
#define SER2_IO_o_DIVISOR_LATCH_MSB
Definition: serial.h:149
#define CPU_IO_o_ARTIC_DELAY
Definition: cpu.h:22
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
#define SER1_MODE_LENGTH_8
Definition: serial.h:66
#define SER2_MCR_OUT_1
Definition: serial.h:178
unsigned short USHORT
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#define CPPORT_FLAG_MODEM_CONTROL
Definition: cportlib.h:25
#define SER1_COMMMAND_TxEN
Definition: serial.h:77
ULONG BaudRate
Definition: cportlib.h:30
unsigned int * PULONG
Definition: retypes.h:1
#define NULL
Definition: types.h:112
#define SER2_IO_i_LINE_CONTROL
Definition: serial.h:122
#define CP_GET_SUCCESS
Definition: cportlib.h:18
#define SER2_LSR_FE
Definition: serial.h:128
#define SER1_IO_i_DATA
Definition: serial.h:15
#define SER2_LCR_ST1
Definition: serial.h:165
#define SER2_IO_o_DIVISOR_LATCH_LSB
Definition: serial.h:138
#define SER1_MODE_1_STOP
Definition: serial.h:73
#define SER1_MODE_CLOCKx16
Definition: serial.h:70
unsigned char Byte
Definition: zlib.h:37
#define SER1_IO_o_MODE_COMMAND
Definition: serial.h:56
#define PPI_IO_i_PORT_B
Definition: sysport.h:19
#define SER1_IO_i_STATUS
Definition: serial.h:16
#define OUT
Definition: typedefs.h:40
unsigned int ULONG
Definition: retypes.h:1
#define SER1_STATUS_PE
Definition: serial.h:20
#define SER2_IO_i_INTERRUPT_ID
Definition: serial.h:116
VOID NTAPI CpEnableFifo(IN PUCHAR Address, IN BOOLEAN Enable)
Definition: cport_pc98.c:68
#define SER1_LSR_PE
Definition: serial.h:31
#define SER_FCR_TXMT_RESET
Definition: serial.h:90
#define STATUS_SUCCESS
Definition: shellext.h:65
#define CP_GET_NODATA
Definition: cportlib.h:19
#define SER1_COMMMAND_RxEN
Definition: serial.h:79
VOID NTAPI CpPutByte(IN PCPPORT Port, IN UCHAR Byte)
Definition: cport_pc98.c:562
#define SER_FCR_DISABLE
Definition: serial.h:87
static BOOLEAN ComPortTest1(IN PUCHAR Address)
Definition: cport_pc98.c:261
#define TIMER_FREQUENCY_2
Definition: pit.h:17