ReactOS 0.4.15-dev-8145-ga541a46
pit.h
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1/*
2 * PROJECT: NEC PC-98 series on-board hardware
3 * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
4 * PURPOSE: Intel 8253A PIT header file
5 * COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
6 */
7
8#pragma once
9
10#define TIMER_CHANNEL0_DATA_PORT 0x71
11#define TIMER_CHANNEL1_DATA_PORT 0x73
12#define TIMER_CHANNEL2_DATA_PORT 0x75
13#define TIMER_CONTROL_PORT 0x77
14
15/* Tick rate of PIT depends on system clock frequency */
16#define TIMER_FREQUENCY_1 1996800 /* 8 MHz */
17#define TIMER_FREQUENCY_2 2457600 /* 10 MHz, 5 MHz */
18
20{
21 /* Interrupt On Terminal Count */
23
24 /* Hardware Re-triggerable One-Shot */
26
27 /* Rate Generator */
29
30 /* Square Wave Generator */
32
33 /* Software Triggered Strobe */
35
36 /* Hardware Triggered Strobe */
39
41{
47
48typedef enum _TIMER_CHANNELS
49{
50 /* IRQ 0 */
52
53 /* PC Speaker */
55
56 /* RS-232 chipset */
58
59 /* Execute multiple latch command */
62
64{
65 struct
66 {
67 UCHAR BcdMode:1;
70 UCHAR Channel:2;
71 };
72 UCHAR Bits;
74
78{
80
83 Count |= READ_PORT_UCHAR((PUCHAR)(TIMER_CHANNEL0_DATA_PORT + TimerChannel * 2)) << 8;
84
85 return Count;
86}
87
89VOID
91 TIMER_CONTROL_PORT_REGISTER TimerControl,
93{
95 WRITE_PORT_UCHAR((PUCHAR)(TIMER_CHANNEL0_DATA_PORT + TimerControl.Channel * 2), Count & 0xFF);
96 WRITE_PORT_UCHAR((PUCHAR)(TIMER_CHANNEL0_DATA_PORT + TimerControl.Channel * 2), (Count >> 8) & 0xFF);
97}
_TIMER_CHANNELS
Definition: halhw.h:101
_TIMER_ACCESS_MODES
Definition: halhw.h:93
enum _TIMER_CHANNELS TIMER_CHANNELS
_TIMER_OPERATING_MODES
Definition: halhw.h:81
int Count
Definition: noreturn.cpp:7
#define READ_PORT_UCHAR(p)
Definition: pc98vid.h:22
#define WRITE_PORT_UCHAR(p, d)
Definition: pc98vid.h:21
unsigned short USHORT
Definition: pedump.c:61
enum _TIMER_ACCESS_MODES TIMER_ACCESS_MODES
FORCEINLINE ULONG Read8253Timer(TIMER_CHANNELS TimerChannel)
Definition: pit.h:77
@ PitChannel0
Definition: pit.h:51
@ MultipleLatch
Definition: pit.h:60
@ PitChannel2
Definition: pit.h:57
@ PitChannel1
Definition: pit.h:54
FORCEINLINE VOID Write8253Timer(TIMER_CONTROL_PORT_REGISTER TimerControl, USHORT Count)
Definition: pit.h:90
enum _TIMER_OPERATING_MODES TIMER_OPERATING_MODES
#define TIMER_CONTROL_PORT
Definition: pit.h:13
@ PitAccessModeLow
Definition: pit.h:43
@ PitAccessModeCounterLatch
Definition: pit.h:42
@ PitAccessModeHigh
Definition: pit.h:44
@ PitAccessModeLowHigh
Definition: pit.h:45
enum _TIMER_CHANNELS TIMER_CHANNELS
union _TIMER_CONTROL_PORT_REGISTER * PTIMER_CONTROL_PORT_REGISTER
@ PitOperatingMode3
Definition: pit.h:31
@ PitOperatingMode2
Definition: pit.h:28
@ PitOperatingMode5
Definition: pit.h:37
@ PitOperatingMode0
Definition: pit.h:22
@ PitOperatingMode4
Definition: pit.h:34
@ PitOperatingMode1
Definition: pit.h:25
union _TIMER_CONTROL_PORT_REGISTER TIMER_CONTROL_PORT_REGISTER
#define TIMER_CHANNEL0_DATA_PORT
Definition: pit.h:10
unsigned char * PUCHAR
Definition: typedefs.h:53
uint32_t ULONG
Definition: typedefs.h:59
#define FORCEINLINE
Definition: wdftypes.h:67
unsigned char UCHAR
Definition: xmlstorage.h:181