ReactOS  0.4.15-dev-1374-g8d3e80e
pit.h
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1 /*
2  * PROJECT: NEC PC-98 series on-board hardware
3  * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
4  * PURPOSE: Intel 8253A PIT header file
5  * COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
6  */
7 
8 #pragma once
9 
10 #define TIMER_CHANNEL0_DATA_PORT 0x71
11 #define TIMER_CHANNEL1_DATA_PORT 0x73
12 #define TIMER_CHANNEL2_DATA_PORT 0x75
13 #define TIMER_CONTROL_PORT 0x77
14 
15 /* Tick rate of PIT depends on system clock frequency */
16 #define TIMER_FREQUENCY_1 1996800 /* 8 MHz */
17 #define TIMER_FREQUENCY_2 2457600 /* 10 MHz, 5 MHz */
18 
20 {
21  /* Interrupt On Terminal Count */
23 
24  /* Hardware Re-triggerable One-Shot */
26 
27  /* Rate Generator */
29 
30  /* Square Wave Generator */
32 
33  /* Software Triggered Strobe */
35 
36  /* Hardware Triggered Strobe */
39 
40 typedef enum _TIMER_ACCESS_MODES
41 {
47 
48 typedef enum _TIMER_CHANNELS
49 {
50  /* IRQ 0 */
52 
53  /* PC Speaker */
55 
56  /* RS-232 chipset */
58 
59  /* Execute multiple latch command */
62 
63 typedef union _TIMER_CONTROL_PORT_REGISTER
64 {
65  struct
66  {
67  UCHAR BcdMode:1;
69  UCHAR AccessMode:2;
70  UCHAR Channel:2;
71  };
72  UCHAR Bits;
74 
76 ULONG
78 {
79  ULONG Count;
80 
82  Count = READ_PORT_UCHAR((PUCHAR)(TIMER_CHANNEL0_DATA_PORT + TimerChannel * 2));
83  Count |= READ_PORT_UCHAR((PUCHAR)(TIMER_CHANNEL0_DATA_PORT + TimerChannel * 2)) << 8;
84 
85  return Count;
86 }
87 
89 VOID
91  TIMER_CONTROL_PORT_REGISTER TimerControl,
92  USHORT Count)
93 {
95  WRITE_PORT_UCHAR((PUCHAR)(TIMER_CHANNEL0_DATA_PORT + TimerControl.Channel * 2), Count & 0xFF);
96  WRITE_PORT_UCHAR((PUCHAR)(TIMER_CHANNEL0_DATA_PORT + TimerControl.Channel * 2), (Count >> 8) & 0xFF);
97 }
#define READ_PORT_UCHAR(p)
Definition: pc98vid.h:22
unsigned char * PUCHAR
Definition: retypes.h:3
FORCEINLINE VOID Write8253Timer(TIMER_CONTROL_PORT_REGISTER TimerControl, USHORT Count)
Definition: pit.h:90
enum _TIMER_ACCESS_MODES TIMER_ACCESS_MODES
_TIMER_OPERATING_MODES
Definition: halhw.h:80
enum _TIMER_OPERATING_MODES TIMER_OPERATING_MODES
_TIMER_ACCESS_MODES
Definition: halhw.h:92
enum _TIMER_CHANNELS TIMER_CHANNELS
#define TIMER_CHANNEL0_DATA_PORT
Definition: pit.h:10
int Count
Definition: noreturn.cpp:7
FORCEINLINE ULONG Read8253Timer(TIMER_CHANNELS TimerChannel)
Definition: pit.h:77
unsigned char UCHAR
Definition: xmlstorage.h:181
#define WRITE_PORT_UCHAR(p, d)
Definition: pc98vid.h:21
union _TIMER_CONTROL_PORT_REGISTER TIMER_CONTROL_PORT_REGISTER
unsigned short USHORT
Definition: pedump.c:61
#define FORCEINLINE
Definition: wdftypes.h:67
union _TIMER_CONTROL_PORT_REGISTER * PTIMER_CONTROL_PORT_REGISTER
unsigned int ULONG
Definition: retypes.h:1
_TIMER_CHANNELS
Definition: halhw.h:100
#define TIMER_CONTROL_PORT
Definition: pit.h:13
enum _TIMER_CHANNELS TIMER_CHANNELS