sil680.c File Reference

#include "pciidex.h"

Include dependency graph for sil680.c:

Go to the source code of this file.

Macros
#define	PCI_DEV_SIL0680   0x0680
#define	SIL_REG_XFER_MODE(Channel)   (0x80 + ((Channel) << 2))
#define	SIL_REG_SYS_CFG   0x8A
#define	SIL_REG_CFG(Channel)   (0xA0 + ((Channel) << 4))
#define	SIL_REG_STATUS(Channel)   (0xA1 + ((Channel) << 4))
#define	SIL_REG_TF_TIM(Channel)   (0xA2 + ((Channel) << 4))
#define	SIL_REG_PIO_TIMING(Channel, Drive)   (0xA4 + ((Channel) << 4) + ((Drive) << 1))
#define	SIL_REG_DMA_TIMING(Channel, Drive)   (0xA8 + ((Channel) << 4) + ((Drive) << 1))
#define	SIL_REG_UDMA_TIMING(Channel, Drive)   (0xAC + ((Channel) << 4) + ((Drive) << 1))
#define	SIL_CFG_CABLE_80   0x00000001
#define	SIL_CFG_MONITOR_IORDY   0x00000200
#define	SIL_STATUS_INTR   0x08
#define	SIL_CLK_MASK   0x30
#define	SIL_CLK_100MHZ   0x00
#define	SIL_CLK_133MHZ   0x10
#define	SIL_CLK_X2   0x20
#define	SIL_CLK_DISABLED   0x30

Functions
static VOID	Sil680SetTransferMode (_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *DeviceList)
static BOOLEAN	Sil680CheckInterrupt (_In_ PCHANNEL_DATA_PATA ChanData)
NTSTATUS	Sil680GetControllerProperties (_Inout_ PATA_CONTROLLER Controller)

Variables
static const USHORT	Sil680TaskFileTimings []
static const USHORT	Sil680PioTimings []
static const USHORT	Sil680MwDmaTimings []
static const UCHAR	Sil680UdmaTimings [2][7]

Macro Definition Documentation

PCI_DEV_SIL0680

#define PCI_DEV_SIL0680   0x0680

Definition at line 14 of file sil680.c.

SIL_CFG_CABLE_80

#define SIL_CFG_CABLE_80   0x00000001

Definition at line 25 of file sil680.c.

SIL_CFG_MONITOR_IORDY

#define SIL_CFG_MONITOR_IORDY   0x00000200

Definition at line 26 of file sil680.c.

SIL_CLK_100MHZ

#define SIL_CLK_100MHZ   0x00

Definition at line 30 of file sil680.c.

SIL_CLK_133MHZ

#define SIL_CLK_133MHZ   0x10

Definition at line 31 of file sil680.c.

SIL_CLK_DISABLED

#define SIL_CLK_DISABLED   0x30

Definition at line 33 of file sil680.c.

SIL_CLK_MASK

#define SIL_CLK_MASK   0x30

Definition at line 29 of file sil680.c.

SIL_CLK_X2

#define SIL_CLK_X2   0x20

Definition at line 32 of file sil680.c.

SIL_REG_CFG

#define SIL_REG_CFG

(

Channel

)

(0xA0 + ((Channel) << 4))

Definition at line 18 of file sil680.c.

SIL_REG_DMA_TIMING

#define SIL_REG_DMA_TIMING	(		Channel,
			Drive
	)		(0xA8 + ((Channel) << 4) + ((Drive) << 1))

Definition at line 22 of file sil680.c.

SIL_REG_PIO_TIMING

#define SIL_REG_PIO_TIMING	(		Channel,
			Drive
	)		(0xA4 + ((Channel) << 4) + ((Drive) << 1))

Definition at line 21 of file sil680.c.

SIL_REG_STATUS

#define SIL_REG_STATUS

(

Channel

)

(0xA1 + ((Channel) << 4))

Definition at line 19 of file sil680.c.

SIL_REG_SYS_CFG

#define SIL_REG_SYS_CFG   0x8A

Definition at line 17 of file sil680.c.

SIL_REG_TF_TIM

#define SIL_REG_TF_TIM

(

Channel

)

(0xA2 + ((Channel) << 4))

Definition at line 20 of file sil680.c.

SIL_REG_UDMA_TIMING

#define SIL_REG_UDMA_TIMING	(		Channel,
			Drive
	)		(0xAC + ((Channel) << 4) + ((Drive) << 1))

Definition at line 23 of file sil680.c.

SIL_REG_XFER_MODE

#define SIL_REG_XFER_MODE

(

Channel

)

(0x80 + ((Channel) << 2))

Definition at line 16 of file sil680.c.

SIL_STATUS_INTR

#define SIL_STATUS_INTR   0x08

Definition at line 27 of file sil680.c.

Function Documentation

Sil680CheckInterrupt()

static BOOLEAN Sil680CheckInterrupt ( _In_ PCHANNEL_DATA_PATA  ChanData )

static

Definition at line 202 of file sil680.c.

{
    PATA_CONTROLLER Controller = ChanData->Controller;
    UCHAR Status;
 
    Status = PciRead8(Controller, SIL_REG_STATUS(ChanData->Channel));
    return !!(Status & SIL_STATUS_INTR);
}

Referenced by Sil680GetControllerProperties().

Sil680GetControllerProperties()

NTSTATUS Sil680GetControllerProperties

(

_Inout_ PATA_CONTROLLER

Controller

)

Definition at line 214 of file sil680.c.

{
    NTSTATUS Status;
    ULONG i;
 
    PAGED_CODE();
    ASSERT(Controller->Pci.VendorID == PCI_VEN_CMD);
 
    if (Controller->Pci.VendorID != PCI_DEV_SIL0680)
        return STATUS_NO_MATCH;
 
    Status = PciIdeCreateChannelData(Controller, 0);
    if (!NT_SUCCESS(Status))
        return Status;
 
    for (i = 0; i < Controller->MaxChannels; ++i)
    {
        PCHANNEL_DATA_PATA ChanData = Controller->Channels[i];
        UCHAR Config;
 
        ChanData->CheckInterrupt = Sil680CheckInterrupt;
        ChanData->SetTransferMode = Sil680SetTransferMode;
        ChanData->TransferModeSupported = PIO_ALL | MWDMA_ALL | UDMA_MODES(0, 6);
 
        /* Check for 80-conductor cable */
        Config = PciRead8(Controller, SIL_REG_CFG(i));
        if (!(Config & SIL_CFG_CABLE_80))
        {
            INFO("CH %lu: BIOS detected 40-conductor cable\n", ChanData->Channel);
            ChanData->TransferModeSupported &= ~UDMA_80C_ALL;
        }
    }
 
    return STATUS_NOT_IMPLEMENTED;
}

Referenced by PciIdeGetControllerProperties().

Sil680SetTransferMode()

static VOID Sil680SetTransferMode ( _In_ PATA_CONTROLLER  Controller, _In_ ULONG  Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *  DeviceList  )

static

Definition at line 71 of file sil680.c.

{
    ULONG i, SlowestPioMode, Config;
    UCHAR ModeReg;
    BOOLEAN MonitorIoReady = FALSE;
 
    INFO("CH %lu: Config (before)\n"
         "MODE %08lX\n"
         "CFG  %08lX\n"
         "PIO  %08lX\n"
         "DMA  %08lX\n"
         "UDMA %08lX\n",
         Channel,
         PciRead32(Controller, SIL_REG_XFER_MODE(Channel)),
         PciRead32(Controller, SIL_REG_CFG(Channel)),
         PciRead32(Controller, SIL_REG_PIO_TIMING(Channel, 0)),
         PciRead32(Controller, SIL_REG_DMA_TIMING(Channel, 0)),
         PciRead32(Controller, SIL_REG_UDMA_TIMING(Channel, 0)));
 
    SlowestPioMode = UDMA_MODE(0);
    ModeReg = PciRead8(Controller, SIL_REG_XFER_MODE(Channel));
 
    for (i = 0; i < MAX_IDE_DEVICE; ++i)
    {
        PCHANNEL_DEVICE_CONFIG Device = DeviceList[i];
        UCHAR XferMode, SysConfig;
 
        if (!Device)
            continue;
 
        /* PIO timings */
        SlowestPioMode = min(SlowestPioMode, Device->PioMode);
        PciWrite16(Controller, SIL_REG_PIO_TIMING(Channel, i), Sil680PioTimings[Device->PioMode]);
 
        if (Device->PioMode >= PIO_MODE(3))
            MonitorIoReady = TRUE;
 
        if (Device->DmaMode >= UDMA_MODE(0))
        {
            SysConfig = PciRead8(Controller, SIL_REG_SYS_CFG);
 
            /* Try to enable the 133MHz IDE clock */
            if ((SysConfig & SIL_CLK_MASK) == SIL_CLK_100MHZ)
            {
                PciWrite8(Controller, SIL_REG_SYS_CFG, SysConfig | SIL_CLK_133MHZ);
 
                SysConfig = PciRead8(Controller, SIL_REG_SYS_CFG);
            }
 
            /* If we are unable to do so, skip UDMA6 selection */
            if ((Device->DmaMode == UDMA_MODE(6)) &&
                (SysConfig & SIL_CLK_MASK) == SIL_CLK_100MHZ)
            {
                ULONG SupportedModes = Device->SupportedModes & ~(PIO_ALL | UDMA_MODE6);
 
                if (!_BitScanReverse(&Device->DmaMode, SupportedModes))
                    Device->DmaMode = PIO_MODE(0);
            }
        }
 
        /* UDMA timings */
        if (Device->DmaMode >= UDMA_MODE(0))
        {
            ULONG ClockIndex = ((SysConfig & SIL_CLK_MASK) == SIL_CLK_100MHZ) ? 0 : 1;
            USHORT UdmaTim;
 
            XferMode = 3;
 
            UdmaTim = PciRead16(Controller, SIL_REG_UDMA_TIMING(Channel, i));
            UdmaTim &= ~0x003F;
            UdmaTim |= Sil680UdmaTimings[ClockIndex][Device->DmaMode - UDMA_MODE(0)];
            PciWrite16(Controller, SIL_REG_UDMA_TIMING(Channel, i), UdmaTim);
        }
        /* DMA timings */
        else if (Device->DmaMode != PIO_MODE(0))
        {
            ULONG ModeIndex = Device->DmaMode - MWDMA_MODE(0);
 
            XferMode = 2;
 
            PciWrite16(Controller, SIL_REG_DMA_TIMING(Channel, i), Sil680MwDmaTimings[ModeIndex]);
        }
        else
        {
            if (Device->IoReadySupported)
                XferMode = 1;
            else
                XferMode = 0;
        }
 
        ModeReg &= ~(0x03 << (i * 4));
        ModeReg |= XferMode << (i * 4);
    }
 
    /* Transfer mode */
    PciWrite8(Controller, SIL_REG_XFER_MODE(Channel), ModeReg);
 
    Config = PciRead32(Controller, SIL_REG_CFG(Channel));
    if (MonitorIoReady)
        Config |= SIL_CFG_MONITOR_IORDY;
    else
        Config &= ~SIL_CFG_MONITOR_IORDY;
 
    /* Task file timings */
    if (SlowestPioMode != UDMA_MODE(0))
    {
        Config &= ~0xFFFF0000;
        Config |= Sil680TaskFileTimings[SlowestPioMode] << 16;
    }
 
    PciWrite32(Controller, SIL_REG_CFG(Channel), Config);
 
    INFO("CH %lu: Config (after)\n"
         "MODE %08lX\n"
         "CFG  %08lX\n"
         "PIO  %08lX\n"
         "DMA  %08lX\n"
         "UDMA %08lX\n",
         Channel,
         PciRead32(Controller, SIL_REG_XFER_MODE(Channel)),
         Config,
         PciRead32(Controller, SIL_REG_PIO_TIMING(Channel, 0)),
         PciRead32(Controller, SIL_REG_DMA_TIMING(Channel, 0)),
         PciRead32(Controller, SIL_REG_UDMA_TIMING(Channel, 0)));
}

Referenced by Sil680GetControllerProperties().

Variable Documentation

Sil680MwDmaTimings

const USHORT Sil680MwDmaTimings[]

static

Initial value:

=
{
    0x2208, 
    0x10C2, 
    0x10C1, 
}

Definition at line 53 of file sil680.c.

Referenced by Sil680SetTransferMode().

Sil680PioTimings

const USHORT Sil680PioTimings[]

static

Initial value:

=
{
    0x328A, 
    0x2283, 
    0x1104, 
    0x10C3, 
    0x10C1  
}

Definition at line 44 of file sil680.c.

Referenced by Sil680SetTransferMode().

Sil680TaskFileTimings

const USHORT Sil680TaskFileTimings[]

static

Initial value:

=
{
    0x328A, 
    0x2283, 
    0x1281, 
    0x10C3, 
    0x10C1  
}

Definition at line 35 of file sil680.c.

Referenced by Sil680SetTransferMode().

Sil680UdmaTimings

const UCHAR Sil680UdmaTimings[2][7]

static

Initial value:

=
{
    
    { 0x0B, 0x07, 0x05, 0x04, 0x02, 0x01       }, 
    { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, 
}

Definition at line 60 of file sil680.c.

Referenced by Sil680SetTransferMode().