amd.c File Reference

#include "pciidex.h"

Include dependency graph for amd.c:

Go to the source code of this file.

Macros
#define	PCI_DEV_AMD_756   0x7409
#define	PCI_DEV_AMD_766   0x7411
#define	PCI_DEV_AMD_768   0x7441
#define	PCI_DEV_AMD_8111   0x7469
#define	PCI_DEV_AMD_CS5536   0x2092
#define	PCI_DEV_AMD_CS5536_2   0x209A
#define	PCI_DEV_NFORCE_IDE   0x01BC
#define	PCI_DEV_NFORCE2_IDE   0x0065
#define	PCI_DEV_NFORCE2_IDE_2   0x0085
#define	PCI_DEV_NFORCE3_IDE   0x00D5
#define	PCI_DEV_NFORCE3_IDE_2   0x00E5
#define	PCI_DEV_CK804_IDE   0x0053
#define	PCI_DEV_MCP04_IDE   0x0035
#define	PCI_DEV_MCP51_IDE   0x0265
#define	PCI_DEV_MCP55_IDE   0x036E
#define	PCI_DEV_MCP61_IDE   0x03EC
#define	PCI_DEV_MCP65_IDE   0x0448
#define	PCI_DEV_MCP67_IDE   0x0560
#define	PCI_DEV_MCP73_IDE   0x056C
#define	PCI_DEV_MCP77_IDE   0x0759
#define	PCI_DEV_NFORCE2_SATA   0x008E
#define	PCI_DEV_NFORCE3_SATA   0x00E3
#define	PCI_DEV_NFORCE3_SATA_2   0x00EE
#define	PCI_DEV_CK804_SATA   0x0054
#define	PCI_DEV_CK804_SATA_2   0x0055
#define	PCI_DEV_MCP04_SATA   0x0036
#define	PCI_DEV_MCP04_SATA_2   0x003E
#define	PCI_DEV_MCP51_SATA   0x0266
#define	PCI_DEV_MCP51_SATA_2   0x0267
#define	PCI_DEV_MCP55_SATA   0x037E
#define	PCI_DEV_MCP55_SATA_2   0x037F
#define	PCI_DEV_MCP61_SATA   0x03E7
#define	PCI_DEV_MCP61_SATA_2   0x03F6
#define	PCI_DEV_MCP61_SATA_3   0x03F7
#define	PCI_DEV_MCP89_SATA   0x0D85
#define	PCI_SUBSYSTEM_AMD_SERENADE   0x36C0
#define	AMD_CONFIG_BASE   0x40
#define	NV_CONFIG_BASE   0x50
#define	AMD_PCI_CLOCK   30000
#define	AMD_REG_CONFIG_PREFETCH(IoBase)   ((IoBase) + 0x01)
#define	AMD_REG_CONFIG_CR(IoBase)   ((IoBase) + 0x02)
#define	AMD_REG_TIMING_CTRL(IoBase)   ((IoBase) + 0x08)
#define	AMD_REG_ADDRESS_SETUP(IoBase)   ((IoBase) + 0x0C)
#define	AMD_REG_UDMA(IoBase, Channel)   ((IoBase) + 0x10 + (2 - ((Channel) * 2)))
#define	AMD_CONFIG_PREFETCH(Channel)   (0xC0 >> ((Channel) * 2))
#define	AMD_CONFIG_CR(Channel)   (0x03 << ((Channel) * 2))
#define	AMD_UDMA_TIME(x)   (x)
#define	AMD_UDMA_EN   0xC0
#define	AMD_UDMA_CTRL(Drive, Value)   ((Value) << ((1 - (Drive)) * 8))
#define	HW_FLAGS_UDMA4   0x0001
#define	HW_FLAGS_UDMA5   0x0002
#define	HW_FLAGS_CHECK_SYSBOARD   0x0004
#define	HW_FLAGS_NO_PREFETCH   0x0008
#define	HW_FLAGS_SATA   0x0010

Functions
static ULONG	AmdGetPciConfigIoBase (_In_ PATA_CONTROLLER Controller)
static VOID	AmdEnablePostedWriteBuffer (_In_ PATA_CONTROLLER Controller, _In_ PCHANNEL_DATA_PATA ChanData, _In_ ULONG Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *DeviceList, _In_ ULONG IoBase)
static VOID	AmdSetTransferMode (_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *DeviceList)
static VOID	AmdControllerStart (_In_ PATA_CONTROLLER Controller)
static BOOLEAN	NvHasUdmaCable (_In_ USHORT UdmaTimReg, _In_ ULONG Drive)
NTSTATUS	AmdGetControllerProperties (_Inout_ PATA_CONTROLLER Controller)

Variables
struct {
USHORT   VendorID
USHORT   DeviceID
USHORT   Flags
}	AmdControllerList []
static const UCHAR	AmdUdmaSettings []
static const ULONG	AmdTimingControlShift [MAX_IDE_CHANNEL][MAX_IDE_DEVICE]
static const ULONG	AmdAddressSetupShift [MAX_IDE_CHANNEL][MAX_IDE_DEVICE]
static const ULONG	AmdPortTimShift [MAX_IDE_CHANNEL]
static PCIIDEX_PAGED_DATA const ATA_PCI_ENABLE_BITS	AmdEnableBits [MAX_IDE_CHANNEL]
static PCIIDEX_PAGED_DATA const ATA_PCI_ENABLE_BITS	NvEnableBits [MAX_IDE_CHANNEL]

Macro Definition Documentation

AMD_CONFIG_BASE

#define AMD_CONFIG_BASE   0x40

Definition at line 54 of file amd.c.

AMD_CONFIG_CR

#define AMD_CONFIG_CR

(

Channel

)

(0x03 << ((Channel) * 2))

Definition at line 66 of file amd.c.

AMD_CONFIG_PREFETCH

#define AMD_CONFIG_PREFETCH

(

Channel

)

(0xC0 >> ((Channel) * 2))

Definition at line 65 of file amd.c.

AMD_PCI_CLOCK

#define AMD_PCI_CLOCK   30000

Definition at line 57 of file amd.c.

AMD_REG_ADDRESS_SETUP

#define AMD_REG_ADDRESS_SETUP

(

IoBase

)

((IoBase) + 0x0C)

Definition at line 62 of file amd.c.

AMD_REG_CONFIG_CR

#define AMD_REG_CONFIG_CR

(

IoBase

)

((IoBase) + 0x02)

Definition at line 60 of file amd.c.

AMD_REG_CONFIG_PREFETCH

#define AMD_REG_CONFIG_PREFETCH

(

IoBase

)

((IoBase) + 0x01)

Definition at line 59 of file amd.c.

AMD_REG_TIMING_CTRL

#define AMD_REG_TIMING_CTRL

(

IoBase

)

((IoBase) + 0x08)

Definition at line 61 of file amd.c.

AMD_REG_UDMA

#define AMD_REG_UDMA	(		IoBase,
			Channel
	)		((IoBase) + 0x10 + (2 - ((Channel) * 2)))

Definition at line 63 of file amd.c.

AMD_UDMA_CTRL

#define AMD_UDMA_CTRL	(		Drive,
			Value
	)		((Value) << ((1 - (Drive)) * 8))

Definition at line 71 of file amd.c.

AMD_UDMA_EN

#define AMD_UDMA_EN   0xC0

Definition at line 69 of file amd.c.

AMD_UDMA_TIME

#define AMD_UDMA_TIME

(

x

)

(x)

Definition at line 68 of file amd.c.

HW_FLAGS_CHECK_SYSBOARD

#define HW_FLAGS_CHECK_SYSBOARD   0x0004

Definition at line 81 of file amd.c.

HW_FLAGS_NO_PREFETCH

#define HW_FLAGS_NO_PREFETCH   0x0008

Definition at line 82 of file amd.c.

HW_FLAGS_SATA

#define HW_FLAGS_SATA   0x0010

Definition at line 83 of file amd.c.

HW_FLAGS_UDMA4

#define HW_FLAGS_UDMA4   0x0001

Definition at line 79 of file amd.c.

HW_FLAGS_UDMA5

#define HW_FLAGS_UDMA5   0x0002

Definition at line 80 of file amd.c.

NV_CONFIG_BASE

#define NV_CONFIG_BASE   0x50

Definition at line 55 of file amd.c.

PCI_DEV_AMD_756

#define PCI_DEV_AMD_756   0x7409

Definition at line 14 of file amd.c.

PCI_DEV_AMD_766

#define PCI_DEV_AMD_766   0x7411

Definition at line 15 of file amd.c.

PCI_DEV_AMD_768

#define PCI_DEV_AMD_768   0x7441

Definition at line 16 of file amd.c.

PCI_DEV_AMD_8111

#define PCI_DEV_AMD_8111   0x7469

Definition at line 17 of file amd.c.

PCI_DEV_AMD_CS5536

#define PCI_DEV_AMD_CS5536   0x2092

Definition at line 18 of file amd.c.

PCI_DEV_AMD_CS5536_2

#define PCI_DEV_AMD_CS5536_2   0x209A

Definition at line 19 of file amd.c.

PCI_DEV_CK804_IDE

#define PCI_DEV_CK804_IDE   0x0053

Definition at line 26 of file amd.c.

PCI_DEV_CK804_SATA

#define PCI_DEV_CK804_SATA   0x0054

Definition at line 39 of file amd.c.

PCI_DEV_CK804_SATA_2

#define PCI_DEV_CK804_SATA_2   0x0055

Definition at line 40 of file amd.c.

PCI_DEV_MCP04_IDE

#define PCI_DEV_MCP04_IDE   0x0035

Definition at line 27 of file amd.c.

PCI_DEV_MCP04_SATA

#define PCI_DEV_MCP04_SATA   0x0036

Definition at line 41 of file amd.c.

PCI_DEV_MCP04_SATA_2

#define PCI_DEV_MCP04_SATA_2   0x003E

Definition at line 42 of file amd.c.

PCI_DEV_MCP51_IDE

#define PCI_DEV_MCP51_IDE   0x0265

Definition at line 28 of file amd.c.

PCI_DEV_MCP51_SATA

#define PCI_DEV_MCP51_SATA   0x0266

Definition at line 43 of file amd.c.

PCI_DEV_MCP51_SATA_2

#define PCI_DEV_MCP51_SATA_2   0x0267

Definition at line 44 of file amd.c.

PCI_DEV_MCP55_IDE

#define PCI_DEV_MCP55_IDE   0x036E

Definition at line 29 of file amd.c.

PCI_DEV_MCP55_SATA

#define PCI_DEV_MCP55_SATA   0x037E

Definition at line 45 of file amd.c.

PCI_DEV_MCP55_SATA_2

#define PCI_DEV_MCP55_SATA_2   0x037F

Definition at line 46 of file amd.c.

PCI_DEV_MCP61_IDE

#define PCI_DEV_MCP61_IDE   0x03EC

Definition at line 30 of file amd.c.

PCI_DEV_MCP61_SATA

#define PCI_DEV_MCP61_SATA   0x03E7

Definition at line 47 of file amd.c.

PCI_DEV_MCP61_SATA_2

#define PCI_DEV_MCP61_SATA_2   0x03F6

Definition at line 48 of file amd.c.

PCI_DEV_MCP61_SATA_3

#define PCI_DEV_MCP61_SATA_3   0x03F7

Definition at line 49 of file amd.c.

PCI_DEV_MCP65_IDE

#define PCI_DEV_MCP65_IDE   0x0448

Definition at line 31 of file amd.c.

PCI_DEV_MCP67_IDE

#define PCI_DEV_MCP67_IDE   0x0560

Definition at line 32 of file amd.c.

PCI_DEV_MCP73_IDE

#define PCI_DEV_MCP73_IDE   0x056C

Definition at line 33 of file amd.c.

PCI_DEV_MCP77_IDE

#define PCI_DEV_MCP77_IDE   0x0759

Definition at line 34 of file amd.c.

PCI_DEV_MCP89_SATA

#define PCI_DEV_MCP89_SATA   0x0D85

Definition at line 50 of file amd.c.

PCI_DEV_NFORCE2_IDE

#define PCI_DEV_NFORCE2_IDE   0x0065

Definition at line 22 of file amd.c.

PCI_DEV_NFORCE2_IDE_2

#define PCI_DEV_NFORCE2_IDE_2   0x0085

Definition at line 23 of file amd.c.

PCI_DEV_NFORCE2_SATA

#define PCI_DEV_NFORCE2_SATA   0x008E

Definition at line 36 of file amd.c.

PCI_DEV_NFORCE3_IDE

#define PCI_DEV_NFORCE3_IDE   0x00D5

Definition at line 24 of file amd.c.

PCI_DEV_NFORCE3_IDE_2

#define PCI_DEV_NFORCE3_IDE_2   0x00E5

Definition at line 25 of file amd.c.

PCI_DEV_NFORCE3_SATA

#define PCI_DEV_NFORCE3_SATA   0x00E3

Definition at line 37 of file amd.c.

PCI_DEV_NFORCE3_SATA_2

#define PCI_DEV_NFORCE3_SATA_2   0x00EE

Definition at line 38 of file amd.c.

PCI_DEV_NFORCE_IDE

#define PCI_DEV_NFORCE_IDE   0x01BC

Definition at line 21 of file amd.c.

PCI_SUBSYSTEM_AMD_SERENADE

#define PCI_SUBSYSTEM_AMD_SERENADE   0x36C0

Definition at line 52 of file amd.c.

Function Documentation

AmdControllerStart()

static VOID AmdControllerStart ( _In_ PATA_CONTROLLER  Controller )

static

Definition at line 297 of file amd.c.

{
    UCHAR ConfigReg;
 
    ASSERT(Controller->Pci.VendorID == PCI_VEN_AMD);
 
    /* Initialize controller before issuing the identify command */
    ConfigReg = PciRead8(Controller, AMD_REG_CONFIG_PREFETCH(AMD_CONFIG_BASE));
    ConfigReg &= ~(AMD_CONFIG_PREFETCH(0) | AMD_CONFIG_PREFETCH(1));
    PciWrite8(Controller, AMD_REG_CONFIG_PREFETCH(AMD_CONFIG_BASE), ConfigReg);
}

Referenced by AmdGetControllerProperties().

AmdEnablePostedWriteBuffer()

static VOID AmdEnablePostedWriteBuffer ( _In_ PATA_CONTROLLER  Controller, _In_ PCHANNEL_DATA_PATA  ChanData, _In_ ULONG  Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *  DeviceList, _In_ ULONG  IoBase  )

static

Definition at line 181 of file amd.c.

{
    UCHAR ConfigReg;
    ULONG i;
 
    ConfigReg = PciRead8(Controller, AMD_REG_CONFIG_PREFETCH(IoBase));
    if (ChanData->HwFlags & HW_FLAGS_NO_PREFETCH)
    {
        /* Errata: IDE Read / Write Prefetch Hangs PCI Bus */
        ConfigReg &= ~(AMD_CONFIG_PREFETCH(0) | AMD_CONFIG_PREFETCH(1));
    }
    else
    {
        ConfigReg |= AMD_CONFIG_PREFETCH(Channel);
 
        for (i = 0; i < MAX_IDE_DEVICE; ++i)
        {
            PCHANNEL_DEVICE_CONFIG Device = DeviceList[i];
 
            if (Device && !Device->IsFixedDisk)
            {
                ConfigReg &= ~AMD_CONFIG_PREFETCH(Channel);
                break;
            }
        }
    }
    PciWrite8(Controller, AMD_REG_CONFIG_PREFETCH(IoBase), ConfigReg);
}

Referenced by AmdSetTransferMode().

AmdGetControllerProperties()

NTSTATUS AmdGetControllerProperties

(

_Inout_ PATA_CONTROLLER

Controller

)

Definition at line 329 of file amd.c.

{
    NTSTATUS Status;
    ULONG i, HwFlags, SupportedMode;
 
    PAGED_CODE();
    ASSERT(Controller->Pci.VendorID == PCI_VEN_AMD || Controller->Pci.VendorID == PCI_VEN_NVIDIA);
 
    for (i = 0; i < RTL_NUMBER_OF(AmdControllerList); ++i)
    {
        HwFlags = AmdControllerList[i].Flags;
 
        if ((Controller->Pci.VendorID == AmdControllerList[i].VendorID) &&
            (Controller->Pci.DeviceID == AmdControllerList[i].DeviceID))
        {
            break;
        }
    }
    if (i == RTL_NUMBER_OF(AmdControllerList))
        return STATUS_NO_MATCH;
 
    Status = PciIdeCreateChannelData(Controller, 0);
    if (!NT_SUCCESS(Status))
        return Status;
 
    if (HwFlags & HW_FLAGS_SATA)
    {
        SupportedMode = SATA_ALL;
    }
    else
    {
        SupportedMode = PIO_ALL | MWDMA_ALL | UDMA_ALL;
 
        if (HwFlags & HW_FLAGS_CHECK_SYSBOARD)
        {
            if (Controller->Pci.SubSystemID == PCI_SUBSYSTEM_AMD_SERENADE)
                SupportedMode &= ~UDMA_MODE6;
        }
        else
        {
            if (HwFlags & HW_FLAGS_UDMA5)
                SupportedMode &= ~UDMA_MODE6;
            else if (HwFlags & HW_FLAGS_UDMA4)
                SupportedMode &= ~UDMA_MODES(5, 6);
        }
 
        if (Controller->Pci.VendorID == PCI_VEN_AMD)
        {
            Controller->ChannelEnableBits = AmdEnableBits;
            Controller->Start = AmdControllerStart;
        }
        else
        {
            Controller->ChannelEnableBits = NvEnableBits;
        }
    }
 
    for (i = 0; i < Controller->MaxChannels; ++i)
    {
        PCHANNEL_DATA_PATA ChanData = Controller->Channels[i];
 
        ChanData->HwFlags = HwFlags;
        ChanData->TransferModeSupported = SupportedMode;
 
        if (HwFlags & HW_FLAGS_SATA)
        {
            ChanData->ChanInfo |= CHANNEL_FLAG_NO_SLAVE;
            ChanData->SetTransferMode = SataSetTransferMode;
        }
        else
        {
            ChanData->SetTransferMode = AmdSetTransferMode;
 
            /* Check for 80-conductor cable */
            if (Controller->Pci.VendorID == PCI_VEN_AMD)
            {
                UCHAR ConfigReg = PciRead8(Controller, AMD_REG_CONFIG_CR(AMD_CONFIG_BASE));
 
                if (!(ConfigReg & AMD_REG_CONFIG_CR(i)))
                {
                    INFO("CH %lu: BIOS detected 40-conductor cable\n", i);
                    ChanData->TransferModeSupported &= ~UDMA_80C_ALL;
                }
            }
            else
            {
                USHORT UdmaTimReg = PciRead16(Controller, AMD_REG_UDMA(NV_CONFIG_BASE, i));
 
                if (!NvHasUdmaCable(UdmaTimReg, 0) && !NvHasUdmaCable(UdmaTimReg, 1))
                {
                    INFO("CH %lu: BIOS hasn't selected mode faster than UDMA 2, "
                         "assume 40-conductor cable\n",
                         ChanData->Channel);
                    ChanData->TransferModeSupported &= ~UDMA_80C_ALL;
                }
            }
        }
    }
 
    return STATUS_SUCCESS;
}

Referenced by PciIdeGetControllerProperties().

AmdGetPciConfigIoBase()

static ULONG AmdGetPciConfigIoBase ( _In_ PATA_CONTROLLER  Controller )

static

Definition at line 170 of file amd.c.

{
    if (Controller->Pci.VendorID == PCI_VEN_AMD)
        return AMD_CONFIG_BASE;
 
    return NV_CONFIG_BASE;
}

Referenced by AmdSetTransferMode().

AmdSetTransferMode()

static VOID AmdSetTransferMode ( _In_ PATA_CONTROLLER  Controller, _In_ ULONG  Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *  DeviceList  )

static

Definition at line 217 of file amd.c.

{
    PCHANNEL_DATA_PATA ChanData = Controller->Channels[Channel];
    const ULONG IoBase = AmdGetPciConfigIoBase(Controller);
    ATA_TIMING DeviceTimings[MAX_IDE_DEVICE];
    ULONG i, DriveTimReg, PortTimReg, UdmaTimReg;
 
    AtaSelectTimings(DeviceList, DeviceTimings, AMD_PCI_CLOCK, SHARED_CMD_TIMINGS);
 
    DriveTimReg = PciRead32(Controller, AMD_REG_TIMING_CTRL(IoBase));
    PortTimReg = PciRead32(Controller, AMD_REG_ADDRESS_SETUP(IoBase));
    UdmaTimReg = PciRead32(Controller, AMD_REG_UDMA(IoBase, 1));
 
    INFO("CH %lu: Config (before)\n"
         "DRV  %08lX\n"
         "PORT %08lX\n"
         "UDMA %08lX\n"
         "CFG  %08lX\n",
         Channel, DriveTimReg, PortTimReg, UdmaTimReg, PciRead32(Controller, IoBase));
 
    for (i = 0; i < MAX_IDE_DEVICE; ++i)
    {
        PCHANNEL_DEVICE_CONFIG Device = DeviceList[i];
        PATA_TIMING Timing = &DeviceTimings[i];
        ULONG Value;
 
        /* UDMA timings */
        if (Device && (Device->DmaMode >= UDMA_MODE(0)))
        {
            Value = AmdUdmaSettings[Device->DmaMode - UDMA_MODE(0)];
        }
        else
        {
            /* Set "Slow UDMA mode 0" by default */
            if (Controller->Pci.VendorID == PCI_VEN_AMD)
                Value = AMD_UDMA_TIME(3);
            else
                Value = 0;
        }
        UdmaTimReg &= ~(0xFF << AmdTimingControlShift[Channel][i]);
        UdmaTimReg |= Value << AmdTimingControlShift[Channel][i];
 
        if (!Device)
            continue;
 
        /* PIO and DMA timings */
        ViaClampTimings(Timing);
 
        Value = Timing->AddressSetup;
        PortTimReg &= ~(0x03 << AmdAddressSetupShift[Channel][i]);
        PortTimReg |= Value << AmdAddressSetupShift[Channel][i];
 
        Value = (Timing->CmdActive << 4) | Timing->CmdRecovery;
        PortTimReg &= ~(0xFF << AmdPortTimShift[Channel]);
        PortTimReg |= Value << AmdPortTimShift[Channel];
 
        Value = (Timing->DataActive << 4) | Timing->DataRecovery;
        DriveTimReg &= ~(0xFF << AmdTimingControlShift[Channel][i]);
        DriveTimReg |= Value << AmdTimingControlShift[Channel][i];
    }
 
    AmdEnablePostedWriteBuffer(Controller, ChanData, Channel, DeviceList, IoBase);
 
    PciWrite32(Controller, AMD_REG_TIMING_CTRL(IoBase), DriveTimReg);
    PciWrite32(Controller, AMD_REG_ADDRESS_SETUP(IoBase), PortTimReg);
    PciWrite32(Controller, AMD_REG_UDMA(IoBase, 1), UdmaTimReg);
 
    INFO("CH %lu: Config (after)\n"
         "DRV  %08lX\n"
         "PORT %08lX\n"
         "UDMA %08lX\n"
         "CFG  %08lX\n",
         Channel, DriveTimReg, PortTimReg, UdmaTimReg, PciRead32(Controller, IoBase));
}

Referenced by AmdGetControllerProperties().

NvHasUdmaCable()

static BOOLEAN NvHasUdmaCable ( _In_ USHORT  UdmaTimReg, _In_ ULONG  Drive  )

static

Definition at line 313 of file amd.c.

{
    PAGED_CODE();
 
    /* UDMA was disabled by BIOS */
    if ((AMD_UDMA_CTRL(Drive, UdmaTimReg) & AMD_UDMA_EN) != AMD_UDMA_EN)
        return FALSE;
 
    /* Check clock settings, see if UDMA3 or higher mode is active */
    return !!((AMD_UDMA_CTRL(Drive, UdmaTimReg) & 0x7) & AMD_UDMA_TIME(4));
}

Referenced by AmdGetControllerProperties().

Variable Documentation

AmdAddressSetupShift

const ULONG AmdAddressSetupShift[MAX_IDE_CHANNEL][MAX_IDE_DEVICE]

static

Initial value:

=
{
    
    { 6, 4 }, 
    { 2, 0 }, 
}

Definition at line 140 of file amd.c.

Referenced by AmdSetTransferMode().

PCIIDEX_PAGED_DATA const struct { ... } AmdControllerList[]

Referenced by AmdGetControllerProperties().

AmdEnableBits

PCIIDEX_PAGED_DATA const ATA_PCI_ENABLE_BITS AmdEnableBits[MAX_IDE_CHANNEL]

static

Initial value:

=
{
    { AMD_CONFIG_BASE, 0x02, 0x02 },
    { AMD_CONFIG_BASE, 0x01, 0x01 },
}

Definition at line 153 of file amd.c.

Referenced by AmdGetControllerProperties().

AmdPortTimShift

const ULONG AmdPortTimShift[MAX_IDE_CHANNEL]

static

Initial value:

=
{
    24, 
    16  
}

Definition at line 146 of file amd.c.

Referenced by AmdSetTransferMode().

AmdTimingControlShift

const ULONG AmdTimingControlShift[MAX_IDE_CHANNEL][MAX_IDE_DEVICE]

static

Initial value:

=
{
    
    { 24, 16 }, 
    { 8,  0  }, 
}

Definition at line 134 of file amd.c.

Referenced by AmdSetTransferMode().

AmdUdmaSettings

const UCHAR AmdUdmaSettings[]

static

Initial value:

=
{
    AMD_UDMA_EN | AMD_UDMA_TIME(2), 
    AMD_UDMA_EN | AMD_UDMA_TIME(1), 
    AMD_UDMA_EN | AMD_UDMA_TIME(0), 
    AMD_UDMA_EN | AMD_UDMA_TIME(4), 
    AMD_UDMA_EN | AMD_UDMA_TIME(5), 
    AMD_UDMA_EN | AMD_UDMA_TIME(6), 
    AMD_UDMA_EN | AMD_UDMA_TIME(7), 
}

Definition at line 123 of file amd.c.

Referenced by AmdSetTransferMode().

DeviceID

USHORT DeviceID

Definition at line 77 of file amd.c.

Flags

USHORT Flags

Definition at line 78 of file amd.c.

NvEnableBits

PCIIDEX_PAGED_DATA const ATA_PCI_ENABLE_BITS NvEnableBits[MAX_IDE_CHANNEL]

static

Initial value:

=
{
    { NV_CONFIG_BASE, 0x02, 0x02 },
    { NV_CONFIG_BASE, 0x01, 0x01 },
}

Definition at line 160 of file amd.c.

Referenced by AmdGetControllerProperties().

VendorID

USHORT VendorID

Definition at line 76 of file amd.c.