ReactOS 0.4.15-dev-8102-g108db8f
haldma.h
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1#pragma once
2
3/*
4 * DMA Page Register Structure
5 * 080 DMA RESERVED
6 * 081 DMA Page Register (channel 2)
7 * 082 DMA Page Register (channel 3)
8 * 083 DMA Page Register (channel 1)
9 * 084 DMA RESERVED
10 * 085 DMA RESERVED
11 * 086 DMA RESERVED
12 * 087 DMA Page Register (channel 0)
13 * 088 DMA RESERVED
14 * 089 PS/2-DMA Page Register (channel 6)
15 * 08A PS/2-DMA Page Register (channel 7)
16 * 08B PS/2-DMA Page Register (channel 5)
17 * 08C PS/2-DMA RESERVED
18 * 08D PS/2-DMA RESERVED
19 * 08E PS/2-DMA RESERVED
20 * 08F PS/2-DMA Page Register (channel 4)
21 */
22
23typedef struct _DMA_PAGE
24{
38
39/*
40 * DMA Channel Mask Register Structure
41 *
42 * MSB LSB
43 * x x x x x x x x
44 * ------------------- - -----
45 * | | | 00 - Select channel 0 mask bit
46 * | | \---- 01 - Select channel 1 mask bit
47 * | | 10 - Select channel 2 mask bit
48 * | | 11 - Select channel 3 mask bit
49 * | |
50 * | \---------- 0 - Clear mask bit
51 * | 1 - Set mask bit
52 * |
53 * \----------------------- xx - Reserved
54 */
55
56typedef struct _DMA_CHANNEL_MASK
57{
62
63/*
64 * DMA Mask Register Structure
65 *
66 * MSB LSB
67 * x x x x x x x x
68 * \---/ - - ----- -----
69 * | | | | | 00 - Channel 0 select
70 * | | | | \---- 01 - Channel 1 select
71 * | | | | 10 - Channel 2 select
72 * | | | | 11 - Channel 3 select
73 * | | | |
74 * | | | | 00 - Verify transfer
75 * | | | \------------ 01 - Write transfer
76 * | | | 10 - Read transfer
77 * | | |
78 * | | \-------------------- 0 - Autoinitialized
79 * | | 1 - Non-autoinitialized
80 * | |
81 * | \------------------------ 0 - Address increment select
82 * |
83 * | 00 - Demand mode
84 * \------------------------------ 01 - Single mode
85 * 10 - Block mode
86 * 11 - Cascade mode
87 */
88
89typedef union _DMA_MODE
90{
91 struct
92 {
98 };
101
102/*
103 * DMA Extended Mode Register Structure
104 *
105 * MSB LSB
106 * x x x x x x x x
107 * - - ----- ----- -----
108 * | | | | | 00 - Channel 0 select
109 * | | | | \---- 01 - Channel 1 select
110 * | | | | 10 - Channel 2 select
111 * | | | | 11 - Channel 3 select
112 * | | | |
113 * | | | | 00 - 8-bit I/O, by bytes
114 * | | | \------------ 01 - 16-bit I/O, by words, address shifted
115 * | | | 10 - 32-bit I/O, by bytes
116 * | | | 11 - 16-bit I/O, by bytes
117 * | | |
118 * | | \---------------------- 00 - Compatible
119 * | | 01 - Type A
120 * | | 10 - Type B
121 * | | 11 - Burst
122 * | |
123 * | \---------------------------- 0 - Terminal Count is Output
124 * |
125 * \---------------------------------0 - Disable Stop Register
126 * 1 - Enable Stop Register
127 */
128
130{
131 struct
132 {
138 };
141
142/* DMA Extended Mode Register Transfer Sizes */
143#define B_8BITS 0
144#define W_16BITS 1
145#define B_32BITS 2
146#define B_16BITS 3
147
148/* DMA Extended Mode Register Timing */
149#define COMPATIBLE_TIMING 0
150#define TYPE_A_TIMING 1
151#define TYPE_B_TIMING 2
152#define BURST_TIMING 3
153
154/* Channel Stop Registers for each Channel */
155typedef struct _DMA_CHANNEL_STOP
156{
162
163/* Transfer Types */
164#define VERIFY_TRANSFER 0x00
165#define READ_TRANSFER 0x01
166#define WRITE_TRANSFER 0x02
167
168/* Request Modes */
169#define DEMAND_REQUEST_MODE 0x00
170#define SINGLE_REQUEST_MODE 0x01
171#define BLOCK_REQUEST_MODE 0x02
172#define CASCADE_REQUEST_MODE 0x03
173
174#define DMA_SETMASK 4
175#define DMA_CLEARMASK 0
176#define DMA_READ 4
177#define DMA_WRITE 8
178#define DMA_SINGLE_TRANSFER 0x40
179#define DMA_AUTO_INIT 0x10
180
182{
186
188{
194
195typedef struct _DMA1_CONTROL
196{
207
208typedef struct _DMA2_CONTROL
209{
228
229/* This structure defines the I/O Map of the 82537 controller. */
230typedef struct _EISA_CONTROL
231{
232 /* DMA Controller 1 */
234 UCHAR Reserved1[16]; /* 0Fh-1Fh */
235
236 /* Interrupt Controller 1 (PIC) */
239 UCHAR Reserved2[30]; /* 22h-3Fh */
240
241 /* Timer */
244 UCHAR Speaker; /* 42h */
246 UCHAR TimerMisc; /* 44h */
247 UCHAR Reserved3[2]; /* 45-46h */
250 UCHAR Reserved4; /* 49h */
253 UCHAR Reserved5[20]; /* 4Ch-5Fh */
254
255 /* NMI / Keyboard / RTC */
256 UCHAR Keyboard; /* 60h */
257 UCHAR NmiStatus; /* 61h */
258 UCHAR Reserved6[14]; /* 62h-6Fh */
259 UCHAR NmiEnable; /* 70h */
260 UCHAR Reserved7[15]; /* 71h-7Fh */
261
262 /* DMA Page Registers Controller 1 */
264 UCHAR Reserved8[16]; /* 90h-9Fh */
265
266 /* Interrupt Controller 2 (PIC) */
269 UCHAR Reserved9[30]; /* 0A2h-0BFh */
270
271 /* DMA Controller 2 */
273
274 /* System Reserved Ports */
275 UCHAR SystemReserved[816]; /* 0D0h-3FFh */
276
277 /* Extended DMA Registers, Controller 1 */
278 UCHAR DmaHighByteCount1[8]; /* 400h-407h */
279 UCHAR Reserved10[2]; /* 408h-409h */
283 UCHAR Reserved11[84]; /* 40Dh-460h */
285 UCHAR NmiCommand; /* 462h */
286 UCHAR Reserved12; /* 463h */
287 UCHAR BusMaster; /* 464h */
288 UCHAR Reserved13[27]; /* 465h-47Fh */
289
290 /* DMA Page Registers Controller 2 */
292 UCHAR Reserved14[48]; /* 490h-4BFh */
293
294 /* Extended DMA Registers, Controller 2 */
295 UCHAR DmaHighByteCount2[16]; /* 4C0h-4CFh */
296
297 /* Edge/Level Control Registers */
300 UCHAR Reserved15[2]; /* 4D2h-4D3h */
301
302 /* Extended DMA Registers, Controller 2 */
304 UCHAR Reserved16; /* 4D5h */
306 UCHAR Reserved17[9]; /* 4D7h-4DFh */
307
308 /* DMA Stop Registers */
311
313{
318
319typedef struct _ADAPTER_OBJECT {
320 /*
321 * New style DMA object definition. The fact that it is at the beginning
322 * of the ADAPTER_OBJECT structure allows us to easily implement the
323 * fallback implementation of IoGetDmaAdapter.
324 */
326
327 /*
328 * For normal adapter objects pointer to master adapter that takes care
329 * of channel allocation. For master adapter set to NULL.
330 */
332
336
339
360
361typedef struct _GROW_WORK_ITEM {
366
367#define MAP_BASE_SW_SG 1
368
371
377
380 PADAPTER_OBJECT AdapterObject);
unsigned char BOOLEAN
ULONG KSPIN_LOCK
Definition: env_spec_w32.h:72
PADAPTER_OBJECT NTAPI HalpDmaAllocateMasterAdapter(VOID)
Definition: dma.c:398
struct _DMA1_ADDRESS_COUNT DMA1_ADDRESS_COUNT
struct _GROW_WORK_ITEM GROW_WORK_ITEM
union _DMA_EXTENDED_MODE DMA_EXTENDED_MODE
struct _DMA1_ADDRESS_COUNT * PDMA1_ADDRESS_COUNT
struct _DMA2_CONTROL * PDMA2_CONTROL
union _DMA_MODE DMA_MODE
struct _EISA_CONTROL * PEISA_CONTROL
struct _ROS_MAP_REGISTER_ENTRY * PROS_MAP_REGISTER_ENTRY
struct _GROW_WORK_ITEM * PGROW_WORK_ITEM
struct _DMA_PAGE * PDMA_PAGE
struct _DMA1_CONTROL DMA1_CONTROL
struct _ROS_MAP_REGISTER_ENTRY ROS_MAP_REGISTER_ENTRY
struct _DMA2_ADDRESS_COUNT DMA2_ADDRESS_COUNT
struct _DMA2_CONTROL DMA2_CONTROL
struct _DMA_CHANNEL_STOP DMA_CHANNEL_STOP
union _DMA_MODE * PDMA_MODE
struct _DMA1_CONTROL * PDMA1_CONTROL
struct _DMA_CHANNEL_STOP * PDMA_CHANNEL_STOP
PDMA_ADAPTER NTAPI HalpGetDmaAdapter(IN PVOID Context, IN PDEVICE_DESCRIPTION DeviceDescription, OUT PULONG NumberOfMapRegisters)
Definition: dma.c:852
struct _DMA_CHANNEL_MASK * PDMA_CHANNEL_MASK
struct _ADAPTER_OBJECT ADAPTER_OBJECT
struct _DMA_CHANNEL_MASK DMA_CHANNEL_MASK
struct _EISA_CONTROL EISA_CONTROL
struct _DMA_PAGE DMA_PAGE
ULONG NTAPI HalpDmaGetDmaAlignment(PADAPTER_OBJECT AdapterObject)
struct _DMA2_ADDRESS_COUNT * PDMA2_ADDRESS_COUNT
union _DMA_EXTENDED_MODE * PDMA_EXTENDED_MODE
unsigned short USHORT
Definition: pedump.c:61
BOOLEAN ScatterGather
Definition: haldma.h:354
struct _ADAPTER_OBJECT * MasterAdapter
Definition: haldma.h:331
ULONG CommittedMapRegisters
Definition: haldma.h:338
DMA_ADAPTER DmaHeader
Definition: haldma.h:325
DMA_MODE AdapterMode
Definition: haldma.h:350
PROS_MAP_REGISTER_ENTRY MapRegisterBase
Definition: haldma.h:335
UCHAR ChannelNumber
Definition: haldma.h:347
BOOLEAN Dma32BitAddresses
Definition: haldma.h:356
BOOLEAN NeedsMapRegisters
Definition: haldma.h:351
USHORT DmaPortAddress
Definition: haldma.h:349
UCHAR AdapterNumber
Definition: haldma.h:348
BOOLEAN MasterDevice
Definition: haldma.h:352
KSPIN_LOCK SpinLock
Definition: haldma.h:344
BOOLEAN Dma64BitAddresses
Definition: haldma.h:357
PRTL_BITMAP MapRegisters
Definition: haldma.h:345
LIST_ENTRY AdapterList
Definition: haldma.h:358
KDEVICE_QUEUE ChannelWaitQueue
Definition: haldma.h:341
PVOID AdapterBaseVa
Definition: haldma.h:334
ULONG NumberOfMapRegisters
Definition: haldma.h:337
ULONG MapRegistersPerChannel
Definition: haldma.h:333
PKDEVICE_QUEUE RegisterWaitQueue
Definition: haldma.h:342
PWAIT_CONTEXT_BLOCK CurrentWcb
Definition: haldma.h:340
LIST_ENTRY AdapterQueue
Definition: haldma.h:343
BOOLEAN Width16Bits
Definition: haldma.h:353
BOOLEAN IgnoreCount
Definition: haldma.h:355
PUCHAR PagePort
Definition: haldma.h:346
UCHAR DmaBaseAddress
Definition: haldma.h:183
UCHAR DmaBaseCount
Definition: haldma.h:184
UCHAR AllMask
Definition: haldma.h:205
UCHAR ClearBytePointer
Definition: haldma.h:202
UCHAR MasterClear
Definition: haldma.h:203
UCHAR DmaRequest
Definition: haldma.h:199
UCHAR ClearMask
Definition: haldma.h:204
UCHAR Mode
Definition: haldma.h:201
UCHAR DmaStatus
Definition: haldma.h:198
DMA1_ADDRESS_COUNT DmaAddressCount[4]
Definition: haldma.h:197
UCHAR SingleMask
Definition: haldma.h:200
UCHAR DmaBaseAddress
Definition: haldma.h:189
UCHAR DmaBaseCount
Definition: haldma.h:191
UCHAR ClearMask
Definition: haldma.h:223
UCHAR Reserved3
Definition: haldma.h:216
UCHAR DmaRequest
Definition: haldma.h:213
UCHAR Reserved8
Definition: haldma.h:226
UCHAR Reserved5
Definition: haldma.h:220
UCHAR ClearBytePointer
Definition: haldma.h:219
UCHAR DmaStatus
Definition: haldma.h:211
UCHAR Reserved6
Definition: haldma.h:222
UCHAR MasterClear
Definition: haldma.h:221
DMA2_ADDRESS_COUNT DmaAddressCount[4]
Definition: haldma.h:210
UCHAR Reserved1
Definition: haldma.h:212
UCHAR Mode
Definition: haldma.h:217
UCHAR Reserved2
Definition: haldma.h:214
UCHAR AllMask
Definition: haldma.h:225
UCHAR SingleMask
Definition: haldma.h:215
UCHAR Reserved7
Definition: haldma.h:224
UCHAR Reserved4
Definition: haldma.h:218
UCHAR SetMask
Definition: haldma.h:59
UCHAR Reserved
Definition: haldma.h:60
UCHAR Channel
Definition: haldma.h:58
UCHAR ChannelMid
Definition: haldma.h:158
UCHAR ChannelHigh
Definition: haldma.h:159
UCHAR ChannelLow
Definition: haldma.h:157
UCHAR Reserved
Definition: haldma.h:160
UCHAR Reserved3
Definition: haldma.h:31
UCHAR Channel0
Definition: haldma.h:30
UCHAR Channel5
Definition: haldma.h:34
UCHAR Channel4
Definition: haldma.h:36
UCHAR Channel1
Definition: haldma.h:28
UCHAR Channel2
Definition: haldma.h:26
UCHAR Channel6
Definition: haldma.h:32
UCHAR Channel7
Definition: haldma.h:33
UCHAR Reserved2[3]
Definition: haldma.h:29
UCHAR Reserved4[3]
Definition: haldma.h:35
UCHAR Reserved1
Definition: haldma.h:25
UCHAR Channel3
Definition: haldma.h:27
UCHAR Keyboard
Definition: haldma.h:256
UCHAR Reserved8[16]
Definition: haldma.h:264
UCHAR Pic1Operation
Definition: haldma.h:237
UCHAR DmaExtendedMode2
Definition: haldma.h:305
UCHAR DmaExtendedMode1
Definition: haldma.h:281
UCHAR Pic2EdgeLevel
Definition: haldma.h:299
UCHAR Reserved9[30]
Definition: haldma.h:269
UCHAR DmaChainMode1
Definition: haldma.h:280
DMA_CHANNEL_STOP DmaChannelStop[8]
Definition: haldma.h:309
UCHAR Reserved1[16]
Definition: haldma.h:234
UCHAR Reserved17[9]
Definition: haldma.h:306
UCHAR SystemReserved[816]
Definition: haldma.h:275
UCHAR Reserved3[2]
Definition: haldma.h:247
UCHAR TimerMisc
Definition: haldma.h:246
UCHAR Reserved13[27]
Definition: haldma.h:288
UCHAR TimerFailSafeCounter
Definition: haldma.h:249
DMA1_CONTROL DmaController2
Definition: haldma.h:272
UCHAR BusMaster
Definition: haldma.h:287
UCHAR Reserved7[15]
Definition: haldma.h:260
UCHAR Pic2Operation
Definition: haldma.h:267
UCHAR Pic1EdgeLevel
Definition: haldma.h:298
UCHAR DmaHighByteCount2[16]
Definition: haldma.h:295
UCHAR Reserved10[2]
Definition: haldma.h:279
UCHAR TimerOperation
Definition: haldma.h:245
UCHAR DmaBufferControl
Definition: haldma.h:282
UCHAR Pic1Interrupt
Definition: haldma.h:238
UCHAR NmiStatus
Definition: haldma.h:257
UCHAR Reserved5[20]
Definition: haldma.h:253
UCHAR TimerCounter2
Definition: haldma.h:251
UCHAR Reserved11[84]
Definition: haldma.h:283
UCHAR TimerCounter
Definition: haldma.h:242
DMA1_CONTROL DmaController1
Definition: haldma.h:233
UCHAR Reserved4
Definition: haldma.h:250
UCHAR NmiEnable
Definition: haldma.h:259
UCHAR Reserved15[2]
Definition: haldma.h:300
UCHAR TimerCounterControl
Definition: haldma.h:248
UCHAR Speaker
Definition: haldma.h:244
UCHAR Reserved6[14]
Definition: haldma.h:258
UCHAR Reserved16
Definition: haldma.h:304
UCHAR NmiCommand
Definition: haldma.h:285
UCHAR TimerOperation2
Definition: haldma.h:252
DMA_PAGE DmaController2Pages
Definition: haldma.h:291
UCHAR DmaChainMode2
Definition: haldma.h:303
UCHAR Reserved12
Definition: haldma.h:286
UCHAR Reserved14[48]
Definition: haldma.h:292
UCHAR Pic2Interrupt
Definition: haldma.h:268
UCHAR TimerMemoryRefresh
Definition: haldma.h:243
UCHAR DmaHighByteCount1[8]
Definition: haldma.h:278
UCHAR Reserved2[30]
Definition: haldma.h:239
UCHAR ExtendedNmiControl
Definition: haldma.h:284
DMA_PAGE DmaController1Pages
Definition: haldma.h:263
WORK_QUEUE_ITEM WorkQueueItem
Definition: haldma.h:362
PADAPTER_OBJECT AdapterObject
Definition: haldma.h:363
ULONG NumberOfMapRegisters
Definition: haldma.h:364
Definition: typedefs.h:120
Definition: haldma.h:313
PHYSICAL_ADDRESS PhysicalAddress
Definition: haldma.h:315
PVOID VirtualAddress
Definition: haldma.h:314
ULONG Counter
Definition: haldma.h:316
uint32_t * PULONG
Definition: typedefs.h:59
#define NTAPI
Definition: typedefs.h:36
#define IN
Definition: typedefs.h:39
unsigned char * PUCHAR
Definition: typedefs.h:53
uint32_t ULONG
Definition: typedefs.h:59
#define OUT
Definition: typedefs.h:40
UCHAR TimingMode
Definition: haldma.h:135
UCHAR TerminalCountIsOutput
Definition: haldma.h:136
UCHAR TransferSize
Definition: haldma.h:134
UCHAR EnableStopRegister
Definition: haldma.h:137
UCHAR ChannelNumber
Definition: haldma.h:133
UCHAR AddressDecrement
Definition: haldma.h:96
UCHAR RequestMode
Definition: haldma.h:97
UCHAR Byte
Definition: haldma.h:99
UCHAR TransferType
Definition: haldma.h:94
UCHAR Channel
Definition: haldma.h:93
UCHAR AutoInitialize
Definition: haldma.h:95
_Must_inspect_result_ _In_ PWDFDEVICE_INIT _In_ PCUNICODE_STRING DeviceDescription
Definition: wdfpdo.h:432
_Out_ PULONG NumberOfMapRegisters
Definition: halfuncs.h:209
unsigned char UCHAR
Definition: xmlstorage.h:181