45 #define TIMEOUT_COUNT 1024 * 200 220 }
while (++
Byte != 0);
241 if (!(Lsr & ExpectedValue))
#define LINE_STATUS_REGISTER
USHORT NTAPI CpGetByte(IN PCPPORT Port, OUT PUCHAR Byte, IN BOOLEAN Wait, IN BOOLEAN Poll)
#define DIVISOR_LATCH_LSB
static BOOLEAN ComPortTest2(IN PUCHAR Address)
VOID NTAPI CpEnableFifo(IN PUCHAR Address, IN BOOLEAN Enable)
#define READ_PORT_UCHAR(p)
#define SERIAL_FCR_DISABLE
#define STATUS_INVALID_PARAMETER
_In_ WDFDPC _In_ BOOLEAN Wait
_In_ ULONGLONG _In_ ULONGLONG _In_ BOOLEAN Enable
VOID NTAPI CpPutByte(IN PCPPORT Port, IN UCHAR Byte)
#define INTERRUPT_ENABLE_REGISTER
#define SERIAL_FCR_ENABLE
NTSTATUS(* NTAPI)(IN PFILE_FULL_EA_INFORMATION EaBuffer, IN ULONG EaLength, OUT PULONG ErrorOffset)
#define RECEIVE_BUFFER_REGISTER
static BOOLEAN ComPortTest1(IN PUCHAR Address)
#define TRANSMIT_HOLDING_REGISTER
UCHAR NTAPI CpReadLsr(IN PCPPORT Port, IN UCHAR ExpectedValue)
#define DIVISOR_LATCH_MSB
NTSTATUS NTAPI CpInitialize(IN PCPPORT Port, IN PUCHAR Address, IN ULONG BaudRate)
VOID NTAPI CpSetBaud(IN PCPPORT Port, IN ULONG BaudRate)
#define MODEM_STATUS_REGISTER
#define SERIAL_NONE_PARITY
#define WRITE_PORT_UCHAR(p, d)
BOOLEAN NTAPI CpDoesPortExist(IN PUCHAR Address)
#define SERIAL_FCR_RCVR_RESET
#define FIFO_CONTROL_REGISTER
#define CPPORT_FLAG_MODEM_CONTROL
#define MODEM_CONTROL_REGISTER
#define SERIAL_FCR_TXMT_RESET
#define LINE_CONTROL_REGISTER