ReactOS  0.4.14-dev-1036-g3c5b10f
ns16550.h
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1 /*
2  * PROJECT: ReactOS ComPort Library
3  * LICENSE: BSD - See COPYING.ARM in the top level directory
4  * FILE: include/reactos/drivers/serial/ns16550.h
5  * PURPOSE: Header for National Semiconductor 16550 UART
6  * PROGRAMMERS: ReactOS Portable Systems Group
7  */
8 
9 /* INCLUDES *******************************************************************/
10 
11 #pragma once
12 
13 /* Note: These definitions are the internal definitions used by Microsoft
14  Serial Driver (see src/serial/serial/serial.h in WDK source code).
15  Linux uses its own, as do most other OS.
16 */
17 
18 /* Baud master clock */
19 // #define BAUD_CLOCK 1843200
20 // #define CLOCKS_PER_BIT 16
21 #define CLOCK_RATE 115200 // UART clock rate == BAUD_CLOCK / CLOCKS_PER_BIT
22 
23 // Define the spacing between registers.
24 #if !defined(SERIAL_REGISTER_STRIDE)
25 #define SERIAL_REGISTER_STRIDE 1
26 #endif
27 
28 /*
29  * Offsets of the various registers, from the base register address.
30  */
31 #define RECEIVE_BUFFER_REGISTER ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
32 #define TRANSMIT_HOLDING_REGISTER ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
33 #define INTERRUPT_ENABLE_REGISTER ((ULONG)((0x01)*SERIAL_REGISTER_STRIDE))
34 #define INTERRUPT_IDENT_REGISTER ((ULONG)((0x02)*SERIAL_REGISTER_STRIDE))
35 #define FIFO_CONTROL_REGISTER ((ULONG)((0x02)*SERIAL_REGISTER_STRIDE))
36 #define LINE_CONTROL_REGISTER ((ULONG)((0x03)*SERIAL_REGISTER_STRIDE))
37 #define MODEM_CONTROL_REGISTER ((ULONG)((0x04)*SERIAL_REGISTER_STRIDE))
38 #define LINE_STATUS_REGISTER ((ULONG)((0x05)*SERIAL_REGISTER_STRIDE))
39 #define MODEM_STATUS_REGISTER ((ULONG)((0x06)*SERIAL_REGISTER_STRIDE))
40 #define SCRATCH_REGISTER ((ULONG)((0x07)*SERIAL_REGISTER_STRIDE))
41 
42 #define DIVISOR_LATCH_LSB ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
43 #define DIVISOR_LATCH_MSB ((ULONG)((0x01)*SERIAL_REGISTER_STRIDE))
44 #define SERIAL_REGISTER_LENGTH ((ULONG)(7*SERIAL_REGISTER_STRIDE))
45 
46 // Length of the interrupt status register.
47 #define SERIAL_STATUS_LENGTH ((ULONG)(1*SERIAL_REGISTER_STRIDE))
48 
49 /*
50  * Start, Data, Parity, Stop number of data bits
51  * transmitted in the Serial Data Unit.
52  */
53 #define SERIAL_DATA_LENGTH_5 0x00
54 #define SERIAL_DATA_LENGTH_6 0x01
55 #define SERIAL_DATA_LENGTH_7 0x02
56 #define SERIAL_DATA_LENGTH_8 0x03
57 
58 /*
59  * Masks defining the interrupts that can be enabled or disabled.
60  */
61 #define SERIAL_IER_RDA 0x01 // New incoming data available.
62 #define SERIAL_IER_THR 0x02 // Space available for another octet in the transmitter.
63 #define SERIAL_IER_RLS 0x04 // Error occurred with incoming data.
64 #define SERIAL_IER_MS 0x08 // Change occurred in the modem control line.
65 
66 /*
67  * Interrupt Identification Register masks.
68  */
69 #define SERIAL_IIR_RLS 0x06
70 #define SERIAL_IIR_RDA 0x04
71 #define SERIAL_IIR_CTI 0x0c
72 #define SERIAL_IIR_THR 0x02
73 #define SERIAL_IIR_MS 0x00
74 #define SERIAL_IIR_FIFOS_ENABLED 0xc0
75 #define SERIAL_IIR_NO_INTERRUPT_PENDING 0x01
76 #define SERIAL_IIR_MUST_BE_ZERO 0x30
77 
78 /*
79  * Fifo Control Register accessing masks.
80  */
81 #define SERIAL_FCR_DISABLE ((UCHAR)0x00)
82 #define SERIAL_FCR_ENABLE ((UCHAR)0x01)
83 #define SERIAL_FCR_RCVR_RESET ((UCHAR)0x02)
84 #define SERIAL_FCR_TXMT_RESET ((UCHAR)0x04)
85 
86 #define SERIAL_1_BYTE_HIGH_WATER ((UCHAR)0x00)
87 #define SERIAL_4_BYTE_HIGH_WATER ((UCHAR)0x40)
88 #define SERIAL_8_BYTE_HIGH_WATER ((UCHAR)0x80)
89 #define SERIAL_14_BYTE_HIGH_WATER ((UCHAR)0xc0)
90 
91 /*
92  * Line Control Register accessing masks.
93  */
94 #define SERIAL_LCR_DLAB 0x80 // Divisor Latch Access Bit
95 #define SERIAL_LCR_BREAK 0x40 // Send a break
96 
97 /*
98  * Line Control Register setting bits.
99  */
100 #define SERIAL_5_DATA ((UCHAR)0x00)
101 #define SERIAL_6_DATA ((UCHAR)0x01)
102 #define SERIAL_7_DATA ((UCHAR)0x02)
103 #define SERIAL_8_DATA ((UCHAR)0x03)
104 #define SERIAL_DATA_MASK ((UCHAR)0x03)
105 
106 #define SERIAL_1_STOP ((UCHAR)0x00)
107 #define SERIAL_1_5_STOP ((UCHAR)0x04) // Only valid for 5 data bits
108 #define SERIAL_2_STOP ((UCHAR)0x04) // Not valid for 5 data bits
109 #define SERIAL_STOP_MASK ((UCHAR)0x04)
110 
111 #define SERIAL_NONE_PARITY ((UCHAR)0x00)
112 #define SERIAL_ODD_PARITY ((UCHAR)0x08)
113 #define SERIAL_EVEN_PARITY ((UCHAR)0x18)
114 #define SERIAL_MARK_PARITY ((UCHAR)0x28)
115 #define SERIAL_SPACE_PARITY ((UCHAR)0x38)
116 #define SERIAL_PARITY_MASK ((UCHAR)0x38)
117 
118 /*
119  * Modem Control Register accessing masks.
120  */
121 #define SERIAL_MCR_DTR 0x01 // Controls the Data Terminal Ready line
122 #define SERIAL_MCR_RTS 0x02 // Controls the Ready To Send line
123 #define SERIAL_MCR_OUT1 0x04 // General purpose output
124 #define SERIAL_MCR_OUT2 0x08 // General purpose output
125 #define SERIAL_MCR_LOOP 0x10 // Controls the loopback testing mode
126 #define SERIAL_MCR_TL16C550CAFE 0x20 // Enables Auto Flow Control on a TI TL16C550C
127 
128 /*
129  * Line Status Register accessing masks.
130  */
131 #define SERIAL_LSR_DR 0x01 // Data Ready indicator
132 #define SERIAL_LSR_OE 0x02 // Overrun indicator
133 #define SERIAL_LSR_PE 0x04 // Parity Error indicator
134 #define SERIAL_LSR_FE 0x08 // Framing Error indicator
135 #define SERIAL_LSR_BI 0x10 // Break Interrupt indicator
136 #define SERIAL_LSR_THRE 0x20 // Transmit Holding Register Empty indicator
137 #define SERIAL_LSR_TEMT 0x40 // Transmitter Empty indicator
138 #define SERIAL_LSR_FIFOERR 0x80 // Fifo Error indicator
139 
140 /*
141  * Modem Status Register accessing masks.
142  */
143 #define SERIAL_MSR_DCTS 0x01 // Delta Clear To Send
144 #define SERIAL_MSR_DDSR 0x02 // Delta Data Set Ready
145 #define SERIAL_MSR_TERI 0x04 // Trailing Edge Ring Indicator
146 #define SERIAL_MSR_DDCD 0x08 // Delta Data Carrier Detect
147 #define SERIAL_MSR_CTS 0x10 // Clear To Send
148 #define SERIAL_MSR_DSR 0x20 // Data Set Ready
149 #define SERIAL_MSR_RI 0x40 // Ring Indicator
150 #define SERIAL_MSR_DCD 0x80 // Data Carrier Detect
151 
152 /* EOF */