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◆ CLOCK_RATE
◆ DIVISOR_LATCH_LSB
◆ DIVISOR_LATCH_MSB
◆ FIFO_CONTROL_REGISTER
◆ INTERRUPT_ENABLE_REGISTER
◆ INTERRUPT_IDENT_REGISTER
◆ LINE_CONTROL_REGISTER
◆ LINE_STATUS_REGISTER
◆ MODEM_CONTROL_REGISTER
◆ MODEM_STATUS_REGISTER
◆ RECEIVE_BUFFER_REGISTER
◆ SCRATCH_REGISTER
◆ SERIAL_14_BYTE_HIGH_WATER
◆ SERIAL_1_5_STOP
◆ SERIAL_1_BYTE_HIGH_WATER
◆ SERIAL_1_STOP
◆ SERIAL_2_STOP
◆ SERIAL_4_BYTE_HIGH_WATER
◆ SERIAL_5_DATA
◆ SERIAL_6_DATA
◆ SERIAL_7_DATA
◆ SERIAL_8_BYTE_HIGH_WATER
◆ SERIAL_8_DATA
◆ SERIAL_DATA_LENGTH_5
#define SERIAL_DATA_LENGTH_5 0x00 |
◆ SERIAL_DATA_LENGTH_6
#define SERIAL_DATA_LENGTH_6 0x01 |
◆ SERIAL_DATA_LENGTH_7
#define SERIAL_DATA_LENGTH_7 0x02 |
◆ SERIAL_DATA_LENGTH_8
#define SERIAL_DATA_LENGTH_8 0x03 |
◆ SERIAL_DATA_MASK
◆ SERIAL_EVEN_PARITY
◆ SERIAL_FCR_DISABLE
◆ SERIAL_FCR_ENABLE
◆ SERIAL_FCR_RCVR_RESET
◆ SERIAL_FCR_TXMT_RESET
◆ SERIAL_IER_MS
◆ SERIAL_IER_RDA
◆ SERIAL_IER_RLS
◆ SERIAL_IER_THR
◆ SERIAL_IIR_CTI
◆ SERIAL_IIR_FIFOS_ENABLED
#define SERIAL_IIR_FIFOS_ENABLED 0xc0 |
◆ SERIAL_IIR_MS
◆ SERIAL_IIR_MUST_BE_ZERO
#define SERIAL_IIR_MUST_BE_ZERO 0x30 |
◆ SERIAL_IIR_NO_INTERRUPT_PENDING
#define SERIAL_IIR_NO_INTERRUPT_PENDING 0x01 |
◆ SERIAL_IIR_RDA
◆ SERIAL_IIR_RLS
◆ SERIAL_IIR_THR
◆ SERIAL_LCR_BREAK
◆ SERIAL_LCR_DLAB
◆ SERIAL_LSR_BI
◆ SERIAL_LSR_DR
◆ SERIAL_LSR_FE
◆ SERIAL_LSR_FIFOERR
#define SERIAL_LSR_FIFOERR 0x80 |
◆ SERIAL_LSR_OE
◆ SERIAL_LSR_PE
◆ SERIAL_LSR_TEMT
◆ SERIAL_LSR_THRE
◆ SERIAL_MARK_PARITY
◆ SERIAL_MCR_DTR
◆ SERIAL_MCR_LOOP
◆ SERIAL_MCR_OUT1
◆ SERIAL_MCR_OUT2
◆ SERIAL_MCR_RTS
◆ SERIAL_MCR_TL16C550CAFE
#define SERIAL_MCR_TL16C550CAFE 0x20 |
◆ SERIAL_MSR_CTS
◆ SERIAL_MSR_DCD
◆ SERIAL_MSR_DCTS
◆ SERIAL_MSR_DDCD
◆ SERIAL_MSR_DDSR
◆ SERIAL_MSR_DSR
◆ SERIAL_MSR_RI
◆ SERIAL_MSR_TERI
◆ SERIAL_NONE_PARITY
◆ SERIAL_ODD_PARITY
◆ SERIAL_PARITY_MASK
◆ SERIAL_REGISTER_LENGTH
◆ SERIAL_REGISTER_STRIDE
#define SERIAL_REGISTER_STRIDE 1 |
◆ SERIAL_SPACE_PARITY
◆ SERIAL_STATUS_LENGTH
◆ SERIAL_STOP_MASK
◆ TRANSMIT_HOLDING_REGISTER