10#define PIC1_CONTROL_PORT 0x00
11#define PIC1_DATA_PORT 0x02
12#define PIC2_CONTROL_PORT 0x08
13#define PIC2_DATA_PORT 0x0A
15#define PIC_TIMER_IRQ 0
16#define PIC_CASCADE_IRQ 7
190#define EISA_ELCR_MASTER 0x98D2
191#define EISA_ELCR_SLAVE 0x98D4
_I8259_ICW4_BUFFERED_MODE
_I8259_ICW1_OPERATING_MODE
_I8259_ICW1_INTERRUPT_MODE
union _I8259_OCW2 I8259_OCW2
union _I8259_OCW3 * PI8259_OCW3
union _I8259_ISR * PI8259_ISR
union _EISA_ELCR * PEISA_ELCR
union _I8259_ICW2 I8259_ICW2
enum _I8259_ICW4_EOI_MODE I8259_ICW4_EOI_MODE
union _I8259_ICW3 I8259_ICW3
union _I8259_OCW2 * PI8259_OCW2
enum _I8259_READ_REQUEST I8259_READ_REQUEST
enum _I8259_EOI_MODE I8259_EOI_MODE
union _I8259_ICW1 I8259_ICW1
union _EISA_ELCR EISA_ELCR
union _I8259_ICW2 * PI8259_ICW2
enum _I8259_ICW4_SYSTEM_MODE I8259_ICW4_SYSTEM_MODE
union _PIC_MASK * PPIC_MASK
union _I8259_ISR I8259_ISR
union _I8259_ICW3 * PI8259_ICW3
enum _I8259_ICW1_INTERRUPT_MODE I8259_ICW1_INTERRUPT_MODE
enum _I8259_ICW1_OPERATING_MODE I8259_ICW1_OPERATING_MODE
union _I8259_ICW1 * PI8259_ICW1
union _I8259_ICW4 * PI8259_ICW4
union _I8259_ICW4 I8259_ICW4
enum _I8259_ICW1_INTERVAL I8259_ICW1_INTERVAL
union _I8259_OCW3 I8259_OCW3
enum _I8259_ICW4_BUFFERED_MODE I8259_ICW4_BUFFERED_MODE
struct _EISA_ELCR::@1520::@1523 Slave
struct _EISA_ELCR::@1520::@1522 Master
UCHAR InterruptVectorAddress
UCHAR SpecialFullyNestedMode