ReactOS  0.4.15-dev-1386-g5cb9f87
cmireg.hpp
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1 /*
2 Copyright (c) 2006-2008 dogbert <dogber1@gmail.com>
3 All rights reserved.
4 
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions
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8 1. Redistributions of source code must retain the above copyright
9  notice, this list of conditions and the following disclaimer.
10 2. Redistributions in binary form must reproduce the above copyright
11  notice, this list of conditions and the following disclaimer in the
12  documentation and/or other materials provided with the distribution.
13 3. The name of the author may not be used to endorse or promote products
14  derived from this software without specific prior written permission.
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16 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 */
27 
28 #ifndef _CMIREG_HPP_
29 #define _CMIREG_HPP_
30 
31 // registers (from CMI8738_6ch_series_spec_v18f_registers.pdf)
32 
33 #define REG_FUNCTRL0 0x00 // Function Control Register 0 (32bit)
34 #define ADC_CH0 0x00000001 // enable ADC on channel 0 for recording
35 #define ADC_CH1 0x00000002 // enable ADC on channel 1 for recording
36 #define PAUSE_CH0 0x00000004 // pause channel 0
37 #define PAUSE_CH1 0x00000008 // pause channel 1
38 #define EN_CH0 0x00010000 // enable channel 0
39 #define EN_CH1 0x00020000 // enable channel 1
40 #define RST_CH0 0x00040000 // reset channel 0
41 #define RST_CH1 0x00080000 // reset channel 1
42 
43 #define REG_FUNCTRL1 0x04 // Function Control Register 1 (32bit)
44 #define EN_ZVPORT 0x00000001 // enable ZVPort
45 #define EN_GAMEPORT 0x00000002 // enable legacy gameport
46 #define EN_UART 0x00000004 // enable UART (MIDI interface)
47 #define BREQ 0x00000010 // enable bus master request
48 #define INTRM 0x00000020 // enable master control block interrupt
49 #define SPDO2DAC 0x00000040 // send S/PDIF out through DAC
50 #define LOOP_SPDF 0x00000080 // loop S/PDIF in to S/PDIF out
51 #define SPDF_0 0x00000100 // enable S/PDIF out at channel 0
52 #define SPDF_1 0x00000200 // enable S/PDIF in/out at channel 1
53 #define SFC_CH0_MASK 0x00001C00 // mask for the sample rate bits of channel 0
54 #define SFC_44K_CH0 0x00000C00 // 44.1kHz channel 0
55 #define SFC_48K_CH0 0x00001C00 // 48kHz channel 0
56 #define SFC_CH1_MASK 0x0000E000 // mask for the sample rate bits of channel 1
57 #define SFC_44K_CH1 0x00006000 // 44.1kHz channel 1
58 #define SFC_48K_CH1 0x0000E000 // 48kHz channel 1
59 
60 #define REG_CHFORMAT 0x08 // Channel Format Register (32bit)
61 #define FORMAT_CH0 0x00000003 // enable 16bit stereo format for channel 0
62 #define FORMAT_CH1 0x0000000C // enable 16bit stereo format for channel 1
63 #define SPDLOCKED 0x00000010 //
64 #define POLVALID 0x00000020 // invert S/PDIF in valid bit
65 #define DBLSPDS 0x00000040 // double S/PDIF sampling rate (44.1 => 88.2, 48 => 96)
66 #define INV_SPDIFI2 0x00000080 // invert S/PDIF in signal (whatever that means, version >37)
67 #define SPD88_CH0 0x00000100 // double sample rate from 44.1 to 88.2 kHz on channel 0
68 #define SPD88_CH1 0x00000200 // double sample rate from 44.1 to 88.2 kHz on channel 1
69 #define SPD96_CH0 0x00000400 // double sample rate from 48 to 96 kHz on channel 0
70 #define SPD96_CH1 0x00000800 // double sample rate from 48 to 96 kHz on channel 1
71 #define SEL_SPDIFI1 0x00080000 // select secondary S/PDIF in (only for versions <=37)
72 #define EN_SPDO_AC3_3 0x00020000 // undocumented: enable AC3 mode on S/PDIF out (requires hardware support)
73 #define EN_SPDO_AC3_1 0x00100000 // undocumented: enable AC3 mode on S/PDIF out
74 #define SPD24SEL 0x00200000 // enable 24bit S/PDIF out
75 #define VERSION_37 0x01000000 // undocumented: hardware revision 37
76 #define EN_4CH_CH1 0x20000000 // enable 4 channel mode on channel 1
77 #define EN_5CH_CH1 0x80000000 // enable 5 channel mode on channel 1
78 
79 #define REG_INTHLDCLR 0x0C // Interrupt Hold/Clear Register (32bit)
80 #define VERSION_MASK 0xFF000000 // mask for the version number, bits [31:24], highest byte
81 #define VERSION_68 0x20000000 // undocumented: hardware revision 68 (8768)
82 #define VERSION_55 0x08000000 // undocumented: hardware revision 55
83 #define VERSION_39 0x04000000 // undocumented: hardware revision 39
84 #define VERSION_39_6 0x01000000 // undocumented: 6 channel version of revision 39
85 #define INT_CLEAR 0x00000001 // clear interrupt
86 #define INT_HOLD 0x00000002 // hold interrupt
87 #define EN_CH0_INT 0x00010000 // enable interrupt on channel 0
88 #define EN_CH1_INT 0x00020000 // enable interrupt on channel 1
89 
90 #define REG_INT_STAT 0x10 // Interrupt Register (32bit)
91 #define INT_CH0 0x00000001 // interrupt on channel 0
92 #define INT_CH1 0x00000002 // interrupt on channel 1
93 #define BUSY_CH0 0x00000004 // channel 0 busy
94 #define BUSY_CH1 0x00000008 // channel 1 busy
95 #define INT_UART 0x00010000 // interrupt on UART interface
96 #define INT_PENDING 0x80000000 // interrupt pending
97 
98 #define REG_LEGACY 0x14 // Legacy Control Register (32bit)
99 #define CENTER2LINE 0x00002000 // route center channel to line-in jack
100 #define BASS2LINE 0x00004000 // route bass channel to line-in jack
101 #define EN_6CH_CH1 0x00008000 // enable 6 channel mode on channel 1
102 #define DAC2SPDO 0x00200000 // enable PCM+FM to S/PDIF out
103 #define EN_SPDCOPYRHT 0x00400000 // enable S/PDIF out copyright bit
104 #define EN_SPDIF_OUT 0x00800000 // enable S/PDIF out
105 #define UART_330 0x00000000 // i/o addresses for UART
106 #define UART_320 0x20000000
107 #define UART_310 0x40000000
108 #define UART_300 0x60000000
109 #define DWORD_MAPPING 0x80000000 // enable DWORD-based position in base register
110 
111 #define REG_MISCCTRL 0x18 // Miscellaneous Control Register (32bit)
112 #define EN_CENTER 0x00000080 // enable center channel
113 #define SEL_SPDIFI2 0x00000100 // select secondary S/PDIF in
114 #define EN_SPDIF_48_1 0x00008000 // enable 48kHz sampling rate on S/PDIF out
115 #define EN_SPDO_AC3_2 0x00040000 // enable AC3 mode on S/PDIF out
116 #define LOOP_SPDF_I 0x00100000 // loop internal S/PDIF out to internal S/PDIF in
117 #define SPD32SEL 0x00200000 // enable 32bit S/PDIF out
118 #define XCHG_DAC 0x00400000 // exchange DACs
119 #define EN_DBLDAC 0x00800000 // enable double DAC mode
120 #define EN_SPDIF_48_2 0x01000000 // enable 48kHz sampling rate on S/PDIF out
121 #define EN_SPDO5V 0x02000000 // enable 5V levels on S/PDIF out
122 #define RST_CHIP 0x40000000 // reset bus master / DSP engine
123 #define PWD_CHIP 0x80000000 // enable power down mode (standby mode etc.)
124 #define EN_SPDIF_48 (EN_SPDIF_48_1 | EN_SPDIF_48_2)
125 
126 #define REG_SBDATA 0x22 // SoundBlaster compatible mixer data register (8bit)
127 #define REG_SBINDEX 0x23 // SoundBlaster compatible mixer index register (8bit)
128 
129 #define REG_MIXER1 0x24 // Mixer Register 1 (8bit)
130 #define EN_SPDI2DAC 0x01 // enable S/PDIF in conversion
131 #define EN_3DSOUND 0x02 // enable 3D sound
132 #define EN_WAVEIN_L 0x04 // enable left wave in recording channel
133 #define EN_WAVEIN_R 0x08 // enable right wave in recording channel
134 #define REAR2FRONT 0x10 // exchange rear/front jacks
135 #define REAR2LINE 0x20 // enable rear out on line-in jack
136 #define MUTE_WAVE 0x40 // disable analog conversion of the wave stream
137 #define MUTE_FM 0x80 // mute FM
138 
139 #define REG_MIXER2 0x25 // Mixer Register 2 (8bit)
140 #define DIS_MICGAIN 0x01 // disable microphone gain
141 #define MUTE_AUX_L 0x10 // mute left aux playback channel
142 #define MUTE_AUX_R 0x20 // mute right aux playback channel
143 #define MUTE_RAUX_L 0x40 // mute left aux recording channel
144 #define MUTE_RAUX_R 0x80 // mute right aux recording channel
145 
146 #define REG_MIXER3 0x26 // Mixer Register 3 (8bit)
147 
148 #define REG_MIXER4 0x27 // Mixer Register 4 (8bit)
149 #define INV_SPDIFI1 0x04 // invert S/PDIF in signal (version <=37)
150 #define CENTER2MIC 0x04 // route center to mic-in jack (version >37)
151 
152 #define REG_CH0_FRAME1 0x80 // Channel 0 Frame Register 1 (32bit)
153 #define REG_CH0_FRAME2 0x84 // Channel 0 Frame Register 2 (32bit)
154 #define REG_CH1_FRAME1 0x88 // Channel 1 Frame Register 1 (32bit)
155 #define REG_CH1_FRAME2 0x8C // Channel 1 Frame Register 2 (32bit)
156 
157 #define REG_MISCCTRL2 0x92 // Miscellaneous Control Register 2 (16bit)
158 #define EN_8CH_CH1 0x0020 // enable 8 channel mode on channel 1
159 
160 #define SBREG_OUTPUTCTRL 0x3C // Soundblaster register for output controls (8bit)
161 #define EN_MIC 0x01 // enable microphone output
162 #define EN_CD_L 0x02 // enable left channel of CD input
163 #define EN_CD_R 0x04 // enable right channel of CD input
164 #define EN_LINEIN_L 0x08 // enable left channel of line-in
165 #define EN_LINEIN_R 0x10 // enable right channel of line-in
166 
167 #define SBREG_IN_CTRL_L 0x3D // Soundblaster register for left channel recording controls (8bit)
168 #define SBREG_IN_CTRL_R 0x3E // Soundblaster register for right channel recording controls (8bit)
169 
170 #define SBREG_EXTENSION 0xF0 // Soundblaster Extension Register (8bit)
171 #define EN_MICBOOST 0x01 // enable microphone boost for recording
172 
173 #endif