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cvconst.h
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1 /*
2  * File cvconst.h - MS debug information
3  *
4  * Copyright (C) 2004, Eric Pouech
5  * Copyright (C) 2012, AndrĂ© Hentschel
6  *
7  * This library is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU Lesser General Public
9  * License as published by the Free Software Foundation; either
10  * version 2.1 of the License, or (at your option) any later version.
11  *
12  * This library is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15  * Lesser General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public
18  * License along with this library; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
20  */
21 
22 /* information in this file is highly derived from MSDN DIA information pages */
23 
24 /* symbols & types enumeration */
26 {
59 };
60 
62 {
63  btNoType = 0,
64  btVoid = 1,
65  btChar = 2,
66  btWChar = 3,
67  btInt = 6,
68  btUInt = 7,
69  btFloat = 8,
70  btBCD = 9,
71  btBool = 10,
72  btLong = 13,
73  btULong = 14,
74  btCurrency = 25,
75  btDate = 26,
76  btVariant = 27,
77  btComplex = 28,
78  btBit = 29,
79  btBSTR = 30,
80  btHresult = 31,
81  btChar16 = 32,
82  btChar32 = 33
83 };
84 
85 /* kind of UDT */
86 enum UdtKind
87 {
91 };
92 
93 /* where a SymTagData is */
95 {
107 };
108 
109 /* kind of SymTagData */
111 {
122 };
123 
124 /* values for registers (on different CPUs) */
126 {
127  /* those values are common to all supported CPUs (and CPU independent) */
128  CV_ALLREG_ERR = 30000,
129  CV_ALLREG_TEB = 30001,
138  CV_ALLREG_TID = 30010,
139  CV_ALLREG_ENV = 30011,
141 
142  /* Intel x86 CPU */
153  CV_REG_CX = 10,
154  CV_REG_DX = 11,
155  CV_REG_BX = 12,
156  CV_REG_SP = 13,
157  CV_REG_BP = 14,
158  CV_REG_SI = 15,
159  CV_REG_DI = 16,
168  CV_REG_ES = 25,
169  CV_REG_CS = 26,
170  CV_REG_SS = 27,
171  CV_REG_DS = 28,
172  CV_REG_FS = 29,
173  CV_REG_GS = 30,
174  CV_REG_IP = 31,
178 
179  /* <pcode> */
183  CV_REG_PCDR3 = 43, /* this includes PCDR4 to PCDR7 */
184  CV_REG_CR0 = 80, /* this includes CR1 to CR4 */
185  CV_REG_DR0 = 90, /* this includes DR1 to DR7 */
186  /* </pcode> */
187 
188  CV_REG_GDTR = 110,
189  CV_REG_GDTL = 111,
190  CV_REG_IDTR = 112,
191  CV_REG_IDTL = 113,
192  CV_REG_LDTR = 114,
193  CV_REG_TR = 115,
194 
195  CV_REG_PSEUDO1 = 116, /* this includes Pseudo02 to Pseudo09 */
196  CV_REG_ST0 = 128, /* this includes ST1 to ST7 */
197  CV_REG_CTRL = 136,
198  CV_REG_STAT = 137,
199  CV_REG_TAG = 138,
200  CV_REG_FPIP = 139,
201  CV_REG_FPCS = 140,
202  CV_REG_FPDO = 141,
203  CV_REG_FPDS = 142,
204  CV_REG_ISEM = 143,
207  CV_REG_MM0 = 146, /* this includes MM1 to MM7 */
208  CV_REG_XMM0 = 154, /* this includes XMM1 to XMM7 */
210  CV_REG_XMM0L = 194, /* this includes XMM1L to XMM7L */
211  CV_REG_XMM0H = 202, /* this includes XMM1H to XMM7H */
216  CV_REG_MM00 = 236,
217  CV_REG_MM01 = 237,
218  CV_REG_MM10 = 238,
219  CV_REG_MM11 = 239,
220  CV_REG_MM20 = 240,
221  CV_REG_MM21 = 241,
222  CV_REG_MM30 = 242,
223  CV_REG_MM31 = 243,
224  CV_REG_MM40 = 244,
225  CV_REG_MM41 = 245,
226  CV_REG_MM50 = 246,
227  CV_REG_MM51 = 247,
228  CV_REG_MM60 = 248,
229  CV_REG_MM61 = 249,
230  CV_REG_MM70 = 250,
231  CV_REG_MM71 = 251,
232 
233  CV_REG_YMM0 = 252, /* this includes YMM1 to YMM7 */
234  CV_REG_YMM0H = 260, /* this includes YMM1H to YMM7H */
235  CV_REG_YMM0I0 = 268, /* this includes YMM0I1 to YMM0I3 */
236  CV_REG_YMM1I0 = 272, /* this includes YMM1I1 to YMM1I3 */
237  CV_REG_YMM2I0 = 276, /* this includes YMM2I1 to YMM2I3 */
238  CV_REG_YMM3I0 = 280, /* this includes YMM3I1 to YMM3I3 */
239  CV_REG_YMM4I0 = 284, /* this includes YMM4I1 to YMM4I3 */
240  CV_REG_YMM5I0 = 288, /* this includes YMM5I1 to YMM5I3 */
241  CV_REG_YMM6I0 = 292, /* this includes YMM6I1 to YMM6I3 */
242  CV_REG_YMM7I0 = 296, /* this includes YMM7I1 to YMM7I3 */
243  CV_REG_YMM0F0 = 300, /* this includes YMM0F1 to YMM0F7 */
244  CV_REG_YMM1F0 = 308, /* this includes YMM1F1 to YMM1F7 */
245  CV_REG_YMM2F0 = 316, /* this includes YMM2F1 to YMM2F7 */
246  CV_REG_YMM3F0 = 324, /* this includes YMM3F1 to YMM3F7 */
247  CV_REG_YMM4F0 = 332, /* this includes YMM4F1 to YMM4F7 */
248  CV_REG_YMM5F0 = 340, /* this includes YMM5F1 to YMM5F7 */
249  CV_REG_YMM6F0 = 348, /* this includes YMM6F1 to YMM6F7 */
250  CV_REG_YMM7F0 = 356, /* this includes YMM7F1 to YMM7F7 */
251  CV_REG_YMM0D0 = 364, /* this includes YMM0D1 to YMM0D3 */
252  CV_REG_YMM1D0 = 368, /* this includes YMM1D1 to YMM1D3 */
253  CV_REG_YMM2D0 = 372, /* this includes YMM2D1 to YMM2D3 */
254  CV_REG_YMM3D0 = 376, /* this includes YMM3D1 to YMM3D3 */
255  CV_REG_YMM4D0 = 380, /* this includes YMM4D1 to YMM4D3 */
256  CV_REG_YMM5D0 = 384, /* this includes YMM5D1 to YMM5D3 */
257  CV_REG_YMM6D0 = 388, /* this includes YMM6D1 to YMM6D3 */
258  CV_REG_YMM7D0 = 392, /* this includes YMM7D1 to YMM7D3 */
259 
260  /* Motorola 68K CPU */
261  CV_R68_D0 = 0, /* this includes D1 to D7 too */
262  CV_R68_A0 = 8, /* this includes A1 to A7 too */
264  CV_R68_SR = 17,
273  CV_R68_PC = 26,
277  CV_R68_FP0 = 32, /* this includes FP1 to FP7 */
291  CV_R68_TC = 57,
292  CV_R68_AC = 58,
297  CV_R68_BAD0 = 64, /* this includes BAD1 to BAD7 */
298  CV_R68_BAC0 = 72, /* this includes BAC1 to BAC7 */
299 
300  /* MIPS 4000 CPU */
306  CV_M4_IntA0 = 14, /* this includes IntA1 to IntA3 */
307  CV_M4_IntT0 = 18, /* this includes IntT1 to IntT7 */
308  CV_M4_IntS0 = 26, /* this includes IntS1 to IntS7 */
319  CV_M4_Fir = 50,
320  CV_M4_Psr = 51,
321  CV_M4_FltF0 = 60, /* this includes FltF1 to Flt31 */
323 
324  /* Alpha AXP CPU */
326  CV_ALPHA_FltF0 = 10, /* this includes FltF1 to FltF31 */
328  CV_ALPHA_IntT0 = 43, /* this includes T1 to T7 */
329  CV_ALPHA_IntS0 = 51, /* this includes S1 to S5 */
331  CV_ALPHA_IntA0 = 58, /* this includes A1 to A5 */
347 
348  /* Motorola & IBM PowerPC CPU */
349  CV_PPC_GPR0 = 1, /* this includes GPR1 to GPR31 */
350  CV_PPC_CR = 33,
351  CV_PPC_CR0 = 34, /* this includes CR1 to CR7 */
352  CV_PPC_FPR0 = 42, /* this includes FPR1 to FPR31 */
353 
356  CV_PPC_SR0 = 76, /* this includes SR1 to SR15 */
357  CV_PPC_PC = 99,
358  CV_PPC_MQ = 100,
359  CV_PPC_XER = 101,
360  CV_PPC_RTCU = 104,
361  CV_PPC_RTCL = 105,
362  CV_PPC_LR = 108,
363  CV_PPC_CTR = 109,
367  CV_PPC_DAR = 119,
368  CV_PPC_DEC = 122,
369  CV_PPC_SDR1 = 125,
370  CV_PPC_SRR0 = 126,
371  CV_PPC_SRR1 = 127,
372  CV_PPC_SPRG0 = 372, /* this includes SPRG1 to SPRG3 */
373  CV_PPC_ASR = 280,
374  CV_PPC_EAR = 382,
375  CV_PPC_PVR = 287,
392  CV_PPC_PMR0 = 1044, /* this includes PMR1 to PMR15 */
393  CV_PPC_DMISS = 1076,
394  CV_PPC_DCMP = 1077,
395  CV_PPC_HASH1 = 1078,
396  CV_PPC_HASH2 = 1079,
397  CV_PPC_IMISS = 1080,
398  CV_PPC_ICMP = 1081,
399  CV_PPC_RPA = 1082,
400  CV_PPC_HID0 = 1108, /* this includes HID1 to HID15 */
401 
402  /* Java */
404 
405  /* Hitachi SH3 CPU */
407  CV_SH3_IntR0 = 10, /* this include R1 to R13 */
411  CV_SH3_Pr = 39,
414  CV_SH3_Pc = 50,
415  CV_SH3_Sr = 51,
429  CV_SH_FpR0 = 80, /* this includes FpR1 to FpR15 */
430  CV_SH_XFpR0 = 96, /* this includes XFpR1 to XXFpR15 */
431 
432  /* ARM CPU */
434  CV_ARM_R0 = 10, /* this includes R1 to R12 */
435  CV_ARM_SP = 23,
436  CV_ARM_LR = 24,
437  CV_ARM_PC = 25,
442  CV_ARM_FS0 = 50, /* this includes FS1 to FS31 */
443  CV_ARM_FPEXTRA0 = 90, /* this includes FPEXTRA1 to FPEXTRA7 */
444  CV_ARM_WR0 = 128, /* this includes WR1 to WR15 */
445  CV_ARM_WCID = 144,
446  CV_ARM_WCON = 145,
449  CV_ARM_WC4 = 148,
450  CV_ARM_WC5 = 149,
451  CV_ARM_WC6 = 150,
452  CV_ARM_WC7 = 151,
453  CV_ARM_WCGR0 = 152, /* this includes WCGR1 to WCGR3 */
454  CV_ARM_WC12 = 156,
455  CV_ARM_WC13 = 157,
456  CV_ARM_WC14 = 158,
457  CV_ARM_WC15 = 159,
458  CV_ARM_FS32 = 200, /* this includes FS33 to FS63 */
459  CV_ARM_ND0 = 300, /* this includes ND1 to ND31 */
460  CV_ARM_NQ0 = 400, /* this includes NQ1 to NQ15 */
461 
462  /* ARM64 CPU */
464  CV_ARM64_W0 = 10, /* this includes W0 to W30 */
466  CV_ARM64_PC = 42, /* Wine extension */
467  CV_ARM64_PSTATE = 43, /* Wine extension */
468  CV_ARM64_X0 = 50, /* this includes X0 to X28 */
469  CV_ARM64_IP0 = 66, /* Same as X16 */
470  CV_ARM64_IP1 = 67, /* Same as X17 */
476  CV_ARM64_S0 = 100, /* this includes S0 to S31 */
477  CV_ARM64_D0 = 140, /* this includes D0 to D31 */
478  CV_ARM64_Q0 = 180, /* this includes Q0 to Q31 */
480 
481  /* Intel IA64 CPU */
483  CV_IA64_Br0 = 512, /* this includes Br1 to Br7 */
484  CV_IA64_P0 = 704, /* this includes P1 to P63 */
486  CV_IA64_IntH0 = 832, /* this includes H1 to H15 */
487  CV_IA64_Ip = 1016,
489  CV_IA64_Cfm = 1018,
490  CV_IA64_Psr = 1019,
491  CV_IA64_Nats = 1020,
494  CV_IA64_IntR0 = 1024, /* this includes R1 to R127 */
495  CV_IA64_FltF0 = 2048, /* this includes FltF1 to FltF127 */
496  /* some IA64 registers missing */
497 
498  /* TriCore CPU */
500  CV_TRI_D0 = 10, /* includes D1 to D15 */
501  CV_TRI_A0 = 26, /* includes A1 to A15 */
502  CV_TRI_E0 = 42,
503  CV_TRI_E2 = 43,
504  CV_TRI_E4 = 44,
505  CV_TRI_E6 = 45,
506  CV_TRI_E8 = 46,
520  CV_TRI_PC = 60,
528  CV_TRI_DPRx_0 = 68, /* includes DPRx_1 to DPRx_3 */
529  CV_TRI_CPRx_0 = 68, /* includes CPRx_1 to CPRx_3 */
530  CV_TRI_DPMx_0 = 68, /* includes DPMx_1 to DPMx_3 */
531  CV_TRI_CPMx_0 = 68, /* includes CPMx_1 to CPMx_3 */
543 
544  /* AM33 (and the likes) CPU */
546  CV_AM33_E0 = 10, /* this includes E1 to E7 */
547  CV_AM33_A0 = 20, /* this includes A1 to A3 */
548  CV_AM33_D0 = 30, /* this includes D1 to D3 */
549  CV_AM33_FS0 = 40, /* this includes FS1 to FS31 */
561 
562  /* Mitsubishi M32R CPU */
564  CV_M32R_R0 = 10, /* this includes R1 to R11 */
578 
579  /* AMD/Intel x86_64 CPU */
614 
615  /* <pcode> */
619  CV_AMD64_PCDR3 = CV_REG_PCDR3, /* this includes PCDR4 to PCDR7 */
620  CV_AMD64_CR0 = CV_REG_CR0, /* this includes CR1 to CR4 */
621  CV_AMD64_DR0 = CV_REG_DR0, /* this includes DR1 to DR7 */
622  /* </pcode> */
623 
630 
631  CV_AMD64_PSEUDO1 = CV_REG_PSEUDO1, /* this includes Pseudo02 to Pseudo09 */
632  CV_AMD64_ST0 = CV_REG_ST0, /* this includes ST1 to ST7 */
643  CV_AMD64_MM0 = CV_REG_MM0, /* this includes MM1 to MM7 */
644  CV_AMD64_XMM0 = CV_REG_XMM0, /* this includes XMM1 to XMM7 */
646  CV_AMD64_XMM0L = CV_REG_XMM0L, /* this includes XMM1L to XMM7L */
647  CV_AMD64_XMM0H = CV_REG_XMM0H, /* this includes XMM1H to XMM7H */
668 
669  CV_AMD64_XMM8 = 252, /* this includes XMM9 to XMM15 */
670 
679 
680  CV_AMD64_R8 = 336,
681  CV_AMD64_R9 = 337,
688 };
689 
690 typedef enum
691 {
697 } THUNK_ORDINAL;
698 
699 typedef enum CV_call_e
700 {
724 } CV_call_e;
BasicType
Definition: compat.h:1256
Definition: cvconst.h:68
Definition: cvconst.h:72
Definition: cvconst.h:79
DataKind
Definition: compat.h:1287
THUNK_ORDINAL
Definition: cvconst.h:690
SymTagEnum
Definition: compat.h:1220
UdtKind
Definition: compat.h:1279
Definition: cvconst.h:65
SymTagEnum
Definition: cvconst.h:25
CV_HREG_e
Definition: compat.h:1302
Definition: cvconst.h:78
LocationType
Definition: cvconst.h:94
Definition: cvconst.h:67
CV_call_e
Definition: cvconst.h:699
CV_call_e
Definition: compat.h:1864
Definition: cvconst.h:64
Definition: cvconst.h:71
Definition: cvconst.h:75
Definition: cvconst.h:70