ReactOS 0.4.15-dev-5669-g09dde2c
hda_controller_defs.h File Reference
#include <SupportDefs.h>
Include dependency graph for hda_controller_defs.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct  rirb_t
 
struct  bdl_entry_t
 

Macros

#define HDAC_GLOBAL_CAP   0x00
 
#define GLOBAL_CAP_OUTPUT_STREAMS(cap)   (((cap) >> 12) & 15)
 
#define GLOBAL_CAP_INPUT_STREAMS(cap)   (((cap) >> 8) & 15)
 
#define GLOBAL_CAP_BIDIR_STREAMS(cap)   (((cap) >> 3) & 15)
 
#define GLOBAL_CAP_NUM_SDO(cap)   ((((cap) >> 1) & 3) ? (cap & 6) : 1)
 
#define GLOBAL_CAP_64BIT(cap)   (((cap) & 1) != 0)
 
#define HDAC_VERSION_MINOR   0x02
 
#define HDAC_VERSION_MAJOR   0x03
 
#define HDAC_GLOBAL_CONTROL   0x08
 
#define GLOBAL_CONTROL_UNSOLICITED   (1 << 8)
 
#define GLOBAL_CONTROL_FLUSH   (1 << 1)
 
#define GLOBAL_CONTROL_RESET   (1 << 0)
 
#define HDAC_WAKE_ENABLE   0x0c
 
#define HDAC_WAKE_ENABLE_MASK   0x7fff
 
#define HDAC_STATE_STATUS   0x0e
 
#define HDAC_INTR_CONTROL   0x20
 
#define INTR_CONTROL_GLOBAL_ENABLE   (1U << 31)
 
#define INTR_CONTROL_CONTROLLER_ENABLE   (1 << 30)
 
#define HDAC_INTR_STATUS   0x24
 
#define INTR_STATUS_GLOBAL   (1U << 31)
 
#define INTR_STATUS_CONTROLLER   (1 << 30)
 
#define INTR_STATUS_STREAM_MASK   0x3fffffff
 
#define HDAC_CORB_BASE_LOWER   0x40
 
#define HDAC_CORB_BASE_UPPER   0x44
 
#define HDAC_CORB_WRITE_POS   0x48
 
#define HDAC_CORB_WRITE_POS_MASK   0xff
 
#define HDAC_CORB_READ_POS   0x4a
 
#define CORB_READ_POS_RESET   (1 << 15)
 
#define HDAC_CORB_CONTROL   0x4c
 
#define HDAC_CORB_CONTROL_MASK   0x3
 
#define CORB_CONTROL_RUN   (1 << 1)
 
#define CORB_CONTROL_MEMORY_ERROR_INTR   (1 << 0)
 
#define HDAC_CORB_STATUS   0x4d
 
#define CORB_STATUS_MEMORY_ERROR   (1 << 0)
 
#define HDAC_CORB_SIZE   0x4e
 
#define HDAC_CORB_SIZE_MASK   0x3
 
#define CORB_SIZE_CAP_2_ENTRIES   (1 << 4)
 
#define CORB_SIZE_CAP_16_ENTRIES   (1 << 5)
 
#define CORB_SIZE_CAP_256_ENTRIES   (1 << 6)
 
#define CORB_SIZE_2_ENTRIES   0x00
 
#define CORB_SIZE_16_ENTRIES   0x01
 
#define CORB_SIZE_256_ENTRIES   0x02
 
#define HDAC_RIRB_BASE_LOWER   0x50
 
#define HDAC_RIRB_BASE_UPPER   0x54
 
#define HDAC_RIRB_WRITE_POS   0x58
 
#define RIRB_WRITE_POS_RESET   (1 << 15)
 
#define HDAC_RESPONSE_INTR_COUNT   0x5a
 
#define HDAC_RESPONSE_INTR_COUNT_MASK   0xff
 
#define HDAC_RIRB_CONTROL   0x5c
 
#define HDAC_RIRB_CONTROL_MASK   0x7
 
#define RIRB_CONTROL_OVERRUN_INTR   (1 << 2)
 
#define RIRB_CONTROL_DMA_ENABLE   (1 << 1)
 
#define RIRB_CONTROL_RESPONSE_INTR   (1 << 0)
 
#define HDAC_RIRB_STATUS   0x5d
 
#define RIRB_STATUS_OVERRUN   (1 << 2)
 
#define RIRB_STATUS_RESPONSE   (1 << 0)
 
#define HDAC_RIRB_SIZE   0x5e
 
#define HDAC_RIRB_SIZE_MASK   0x3
 
#define RIRB_SIZE_CAP_2_ENTRIES   (1 << 4)
 
#define RIRB_SIZE_CAP_16_ENTRIES   (1 << 5)
 
#define RIRB_SIZE_CAP_256_ENTRIES   (1 << 6)
 
#define RIRB_SIZE_2_ENTRIES   0x00
 
#define RIRB_SIZE_16_ENTRIES   0x01
 
#define RIRB_SIZE_256_ENTRIES   0x02
 
#define HDAC_DMA_POSITION_BASE_LOWER   0x70
 
#define HDAC_DMA_POSITION_BASE_UPPER   0x74
 
#define DMA_POSITION_ENABLED   1
 
#define HDAC_STREAM_BASE   0x80
 
#define HDAC_STREAM_SIZE   0x20
 
#define HDAC_STREAM_CONTROL0   0x00
 
#define CONTROL0_RESET   (1 << 0)
 
#define CONTROL0_RUN   (1 << 1)
 
#define CONTROL0_BUFFER_COMPLETED_INTR   (1 << 2)
 
#define CONTROL0_FIFO_ERROR_INTR   (1 << 3)
 
#define CONTROL0_DESCRIPTOR_ERROR_INTR   (1 << 4)
 
#define HDAC_STREAM_CONTROL1   0x01
 
#define HDAC_STREAM_CONTROL2   0x02
 
#define CONTROL2_STREAM_MASK   0xf0
 
#define CONTROL2_STREAM_SHIFT   4
 
#define CONTROL2_BIDIR   (1 << 3)
 
#define CONTROL2_TRAFFIC_PRIORITY   (1 << 2)
 
#define CONTROL2_STRIPE_SDO_MASK   0x03
 
#define HDAC_STREAM_STATUS   0x03
 
#define STATUS_BUFFER_COMPLETED   (1 << 2)
 
#define STATUS_FIFO_ERROR   (1 << 3)
 
#define STATUS_DESCRIPTOR_ERROR   (1 << 4)
 
#define STATUS_FIFO_READY   (1 << 5)
 
#define HDAC_STREAM_POSITION   0x04
 
#define HDAC_STREAM_BUFFER_SIZE   0x08
 
#define HDAC_STREAM_LAST_VALID   0x0c
 
#define HDAC_STREAM_FIFO_SIZE   0x10
 
#define HDAC_STREAM_FORMAT   0x12
 
#define FORMAT_8BIT   (0 << 4)
 
#define FORMAT_16BIT   (1 << 4)
 
#define FORMAT_20BIT   (2 << 4)
 
#define FORMAT_24BIT   (3 << 4)
 
#define FORMAT_32BIT   (4 << 4)
 
#define FORMAT_44_1_BASE_RATE   (1 << 14)
 
#define FORMAT_MULTIPLY_RATE_SHIFT   11
 
#define FORMAT_DIVIDE_RATE_SHIFT   8
 
#define HDAC_STREAM_BUFFERS_BASE_LOWER   0x18
 
#define HDAC_STREAM_BUFFERS_BASE_UPPER   0x1c
 
#define PCI_HDA_TCSEL   0x44
 
#define PCI_HDA_TCSEL_MASK   0xf8
 
#define ATI_HDA_MISC_CNTR2   0x42
 
#define ATI_HDA_MISC_CNTR2_MASK   0xf8
 
#define ATI_HDA_ENABLE_SNOOP   0x02
 
#define NVIDIA_HDA_OSTRM_COH   0x4c
 
#define NVIDIA_HDA_ISTRM_COH   0x4d
 
#define NVIDIA_HDA_ENABLE_COHBIT   0x01
 
#define NVIDIA_HDA_TRANSREG   0x4e
 
#define NVIDIA_HDA_TRANSREG_MASK   0xf0
 
#define NVIDIA_HDA_ENABLE_COHBITS   0x0f
 
#define INTEL_SCH_HDA_DEVC   0x78
 
#define INTEL_SCH_HDA_DEVC_SNOOP   0x800
 
#define RESPONSE_FLAGS_CODEC_MASK   0x0000000f
 
#define RESPONSE_FLAGS_UNSOLICITED   (1 << 4)
 

Typedefs

typedef uint32 corb_t
 

Macro Definition Documentation

◆ ATI_HDA_ENABLE_SNOOP

#define ATI_HDA_ENABLE_SNOOP   0x02

Definition at line 147 of file hda_controller_defs.h.

◆ ATI_HDA_MISC_CNTR2

#define ATI_HDA_MISC_CNTR2   0x42

Definition at line 145 of file hda_controller_defs.h.

◆ ATI_HDA_MISC_CNTR2_MASK

#define ATI_HDA_MISC_CNTR2_MASK   0xf8

Definition at line 146 of file hda_controller_defs.h.

◆ CONTROL0_BUFFER_COMPLETED_INTR

#define CONTROL0_BUFFER_COMPLETED_INTR   (1 << 2)

Definition at line 110 of file hda_controller_defs.h.

◆ CONTROL0_DESCRIPTOR_ERROR_INTR

#define CONTROL0_DESCRIPTOR_ERROR_INTR   (1 << 4)

Definition at line 112 of file hda_controller_defs.h.

◆ CONTROL0_FIFO_ERROR_INTR

#define CONTROL0_FIFO_ERROR_INTR   (1 << 3)

Definition at line 111 of file hda_controller_defs.h.

◆ CONTROL0_RESET

#define CONTROL0_RESET   (1 << 0)

Definition at line 108 of file hda_controller_defs.h.

◆ CONTROL0_RUN

#define CONTROL0_RUN   (1 << 1)

Definition at line 109 of file hda_controller_defs.h.

◆ CONTROL2_BIDIR

#define CONTROL2_BIDIR   (1 << 3)

Definition at line 117 of file hda_controller_defs.h.

◆ CONTROL2_STREAM_MASK

#define CONTROL2_STREAM_MASK   0xf0

Definition at line 115 of file hda_controller_defs.h.

◆ CONTROL2_STREAM_SHIFT

#define CONTROL2_STREAM_SHIFT   4

Definition at line 116 of file hda_controller_defs.h.

◆ CONTROL2_STRIPE_SDO_MASK

#define CONTROL2_STRIPE_SDO_MASK   0x03

Definition at line 119 of file hda_controller_defs.h.

◆ CONTROL2_TRAFFIC_PRIORITY

#define CONTROL2_TRAFFIC_PRIORITY   (1 << 2)

Definition at line 118 of file hda_controller_defs.h.

◆ CORB_CONTROL_MEMORY_ERROR_INTR

#define CORB_CONTROL_MEMORY_ERROR_INTR   (1 << 0)

Definition at line 57 of file hda_controller_defs.h.

◆ CORB_CONTROL_RUN

#define CORB_CONTROL_RUN   (1 << 1)

Definition at line 56 of file hda_controller_defs.h.

◆ CORB_READ_POS_RESET

#define CORB_READ_POS_RESET   (1 << 15)

Definition at line 52 of file hda_controller_defs.h.

◆ CORB_SIZE_16_ENTRIES

#define CORB_SIZE_16_ENTRIES   0x01

Definition at line 68 of file hda_controller_defs.h.

◆ CORB_SIZE_256_ENTRIES

#define CORB_SIZE_256_ENTRIES   0x02

Definition at line 69 of file hda_controller_defs.h.

◆ CORB_SIZE_2_ENTRIES

#define CORB_SIZE_2_ENTRIES   0x00

Definition at line 67 of file hda_controller_defs.h.

◆ CORB_SIZE_CAP_16_ENTRIES

#define CORB_SIZE_CAP_16_ENTRIES   (1 << 5)

Definition at line 65 of file hda_controller_defs.h.

◆ CORB_SIZE_CAP_256_ENTRIES

#define CORB_SIZE_CAP_256_ENTRIES   (1 << 6)

Definition at line 66 of file hda_controller_defs.h.

◆ CORB_SIZE_CAP_2_ENTRIES

#define CORB_SIZE_CAP_2_ENTRIES   (1 << 4)

Definition at line 64 of file hda_controller_defs.h.

◆ CORB_STATUS_MEMORY_ERROR

#define CORB_STATUS_MEMORY_ERROR   (1 << 0)

Definition at line 60 of file hda_controller_defs.h.

◆ DMA_POSITION_ENABLED

#define DMA_POSITION_ENABLED   1

Definition at line 101 of file hda_controller_defs.h.

◆ FORMAT_16BIT

#define FORMAT_16BIT   (1 << 4)

Definition at line 131 of file hda_controller_defs.h.

◆ FORMAT_20BIT

#define FORMAT_20BIT   (2 << 4)

Definition at line 132 of file hda_controller_defs.h.

◆ FORMAT_24BIT

#define FORMAT_24BIT   (3 << 4)

Definition at line 133 of file hda_controller_defs.h.

◆ FORMAT_32BIT

#define FORMAT_32BIT   (4 << 4)

Definition at line 134 of file hda_controller_defs.h.

◆ FORMAT_44_1_BASE_RATE

#define FORMAT_44_1_BASE_RATE   (1 << 14)

Definition at line 135 of file hda_controller_defs.h.

◆ FORMAT_8BIT

#define FORMAT_8BIT   (0 << 4)

Definition at line 130 of file hda_controller_defs.h.

◆ FORMAT_DIVIDE_RATE_SHIFT

#define FORMAT_DIVIDE_RATE_SHIFT   8

Definition at line 137 of file hda_controller_defs.h.

◆ FORMAT_MULTIPLY_RATE_SHIFT

#define FORMAT_MULTIPLY_RATE_SHIFT   11

Definition at line 136 of file hda_controller_defs.h.

◆ GLOBAL_CAP_64BIT

#define GLOBAL_CAP_64BIT (   cap)    (((cap) & 1) != 0)

Definition at line 22 of file hda_controller_defs.h.

◆ GLOBAL_CAP_BIDIR_STREAMS

#define GLOBAL_CAP_BIDIR_STREAMS (   cap)    (((cap) >> 3) & 15)

Definition at line 20 of file hda_controller_defs.h.

◆ GLOBAL_CAP_INPUT_STREAMS

#define GLOBAL_CAP_INPUT_STREAMS (   cap)    (((cap) >> 8) & 15)

Definition at line 19 of file hda_controller_defs.h.

◆ GLOBAL_CAP_NUM_SDO

#define GLOBAL_CAP_NUM_SDO (   cap)    ((((cap) >> 1) & 3) ? (cap & 6) : 1)

Definition at line 21 of file hda_controller_defs.h.

◆ GLOBAL_CAP_OUTPUT_STREAMS

#define GLOBAL_CAP_OUTPUT_STREAMS (   cap)    (((cap) >> 12) & 15)

Definition at line 18 of file hda_controller_defs.h.

◆ GLOBAL_CONTROL_FLUSH

#define GLOBAL_CONTROL_FLUSH   (1 << 1)

Definition at line 30 of file hda_controller_defs.h.

◆ GLOBAL_CONTROL_RESET

#define GLOBAL_CONTROL_RESET   (1 << 0)

Definition at line 31 of file hda_controller_defs.h.

◆ GLOBAL_CONTROL_UNSOLICITED

#define GLOBAL_CONTROL_UNSOLICITED   (1 << 8)

Definition at line 28 of file hda_controller_defs.h.

◆ HDAC_CORB_BASE_LOWER

#define HDAC_CORB_BASE_LOWER   0x40

Definition at line 46 of file hda_controller_defs.h.

◆ HDAC_CORB_BASE_UPPER

#define HDAC_CORB_BASE_UPPER   0x44

Definition at line 47 of file hda_controller_defs.h.

◆ HDAC_CORB_CONTROL

#define HDAC_CORB_CONTROL   0x4c

Definition at line 54 of file hda_controller_defs.h.

◆ HDAC_CORB_CONTROL_MASK

#define HDAC_CORB_CONTROL_MASK   0x3

Definition at line 55 of file hda_controller_defs.h.

◆ HDAC_CORB_READ_POS

#define HDAC_CORB_READ_POS   0x4a

Definition at line 51 of file hda_controller_defs.h.

◆ HDAC_CORB_SIZE

#define HDAC_CORB_SIZE   0x4e

Definition at line 62 of file hda_controller_defs.h.

◆ HDAC_CORB_SIZE_MASK

#define HDAC_CORB_SIZE_MASK   0x3

Definition at line 63 of file hda_controller_defs.h.

◆ HDAC_CORB_STATUS

#define HDAC_CORB_STATUS   0x4d

Definition at line 59 of file hda_controller_defs.h.

◆ HDAC_CORB_WRITE_POS

#define HDAC_CORB_WRITE_POS   0x48

Definition at line 48 of file hda_controller_defs.h.

◆ HDAC_CORB_WRITE_POS_MASK

#define HDAC_CORB_WRITE_POS_MASK   0xff

Definition at line 49 of file hda_controller_defs.h.

◆ HDAC_DMA_POSITION_BASE_LOWER

#define HDAC_DMA_POSITION_BASE_LOWER   0x70

Definition at line 99 of file hda_controller_defs.h.

◆ HDAC_DMA_POSITION_BASE_UPPER

#define HDAC_DMA_POSITION_BASE_UPPER   0x74

Definition at line 100 of file hda_controller_defs.h.

◆ HDAC_GLOBAL_CAP

#define HDAC_GLOBAL_CAP   0x00

Definition at line 17 of file hda_controller_defs.h.

◆ HDAC_GLOBAL_CONTROL

#define HDAC_GLOBAL_CONTROL   0x08

Definition at line 27 of file hda_controller_defs.h.

◆ HDAC_INTR_CONTROL

#define HDAC_INTR_CONTROL   0x20

Definition at line 37 of file hda_controller_defs.h.

◆ HDAC_INTR_STATUS

#define HDAC_INTR_STATUS   0x24

Definition at line 41 of file hda_controller_defs.h.

◆ HDAC_RESPONSE_INTR_COUNT

#define HDAC_RESPONSE_INTR_COUNT   0x5a

Definition at line 77 of file hda_controller_defs.h.

◆ HDAC_RESPONSE_INTR_COUNT_MASK

#define HDAC_RESPONSE_INTR_COUNT_MASK   0xff

Definition at line 78 of file hda_controller_defs.h.

◆ HDAC_RIRB_BASE_LOWER

#define HDAC_RIRB_BASE_LOWER   0x50

Definition at line 71 of file hda_controller_defs.h.

◆ HDAC_RIRB_BASE_UPPER

#define HDAC_RIRB_BASE_UPPER   0x54

Definition at line 72 of file hda_controller_defs.h.

◆ HDAC_RIRB_CONTROL

#define HDAC_RIRB_CONTROL   0x5c

Definition at line 80 of file hda_controller_defs.h.

◆ HDAC_RIRB_CONTROL_MASK

#define HDAC_RIRB_CONTROL_MASK   0x7

Definition at line 81 of file hda_controller_defs.h.

◆ HDAC_RIRB_SIZE

#define HDAC_RIRB_SIZE   0x5e

Definition at line 90 of file hda_controller_defs.h.

◆ HDAC_RIRB_SIZE_MASK

#define HDAC_RIRB_SIZE_MASK   0x3

Definition at line 91 of file hda_controller_defs.h.

◆ HDAC_RIRB_STATUS

#define HDAC_RIRB_STATUS   0x5d

Definition at line 86 of file hda_controller_defs.h.

◆ HDAC_RIRB_WRITE_POS

#define HDAC_RIRB_WRITE_POS   0x58

Definition at line 74 of file hda_controller_defs.h.

◆ HDAC_STATE_STATUS

#define HDAC_STATE_STATUS   0x0e

Definition at line 35 of file hda_controller_defs.h.

◆ HDAC_STREAM_BASE

#define HDAC_STREAM_BASE   0x80

Definition at line 104 of file hda_controller_defs.h.

◆ HDAC_STREAM_BUFFER_SIZE

#define HDAC_STREAM_BUFFER_SIZE   0x08

Definition at line 126 of file hda_controller_defs.h.

◆ HDAC_STREAM_BUFFERS_BASE_LOWER

#define HDAC_STREAM_BUFFERS_BASE_LOWER   0x18

Definition at line 138 of file hda_controller_defs.h.

◆ HDAC_STREAM_BUFFERS_BASE_UPPER

#define HDAC_STREAM_BUFFERS_BASE_UPPER   0x1c

Definition at line 139 of file hda_controller_defs.h.

◆ HDAC_STREAM_CONTROL0

#define HDAC_STREAM_CONTROL0   0x00

Definition at line 107 of file hda_controller_defs.h.

◆ HDAC_STREAM_CONTROL1

#define HDAC_STREAM_CONTROL1   0x01

Definition at line 113 of file hda_controller_defs.h.

◆ HDAC_STREAM_CONTROL2

#define HDAC_STREAM_CONTROL2   0x02

Definition at line 114 of file hda_controller_defs.h.

◆ HDAC_STREAM_FIFO_SIZE

#define HDAC_STREAM_FIFO_SIZE   0x10

Definition at line 128 of file hda_controller_defs.h.

◆ HDAC_STREAM_FORMAT

#define HDAC_STREAM_FORMAT   0x12

Definition at line 129 of file hda_controller_defs.h.

◆ HDAC_STREAM_LAST_VALID

#define HDAC_STREAM_LAST_VALID   0x0c

Definition at line 127 of file hda_controller_defs.h.

◆ HDAC_STREAM_POSITION

#define HDAC_STREAM_POSITION   0x04

Definition at line 125 of file hda_controller_defs.h.

◆ HDAC_STREAM_SIZE

#define HDAC_STREAM_SIZE   0x20

Definition at line 105 of file hda_controller_defs.h.

◆ HDAC_STREAM_STATUS

#define HDAC_STREAM_STATUS   0x03

Definition at line 120 of file hda_controller_defs.h.

◆ HDAC_VERSION_MAJOR

#define HDAC_VERSION_MAJOR   0x03

Definition at line 25 of file hda_controller_defs.h.

◆ HDAC_VERSION_MINOR

#define HDAC_VERSION_MINOR   0x02

Definition at line 24 of file hda_controller_defs.h.

◆ HDAC_WAKE_ENABLE

#define HDAC_WAKE_ENABLE   0x0c

Definition at line 33 of file hda_controller_defs.h.

◆ HDAC_WAKE_ENABLE_MASK

#define HDAC_WAKE_ENABLE_MASK   0x7fff

Definition at line 34 of file hda_controller_defs.h.

◆ INTEL_SCH_HDA_DEVC

#define INTEL_SCH_HDA_DEVC   0x78

Definition at line 154 of file hda_controller_defs.h.

◆ INTEL_SCH_HDA_DEVC_SNOOP

#define INTEL_SCH_HDA_DEVC_SNOOP   0x800

Definition at line 155 of file hda_controller_defs.h.

◆ INTR_CONTROL_CONTROLLER_ENABLE

#define INTR_CONTROL_CONTROLLER_ENABLE   (1 << 30)

Definition at line 39 of file hda_controller_defs.h.

◆ INTR_CONTROL_GLOBAL_ENABLE

#define INTR_CONTROL_GLOBAL_ENABLE   (1U << 31)

Definition at line 38 of file hda_controller_defs.h.

◆ INTR_STATUS_CONTROLLER

#define INTR_STATUS_CONTROLLER   (1 << 30)

Definition at line 43 of file hda_controller_defs.h.

◆ INTR_STATUS_GLOBAL

#define INTR_STATUS_GLOBAL   (1U << 31)

Definition at line 42 of file hda_controller_defs.h.

◆ INTR_STATUS_STREAM_MASK

#define INTR_STATUS_STREAM_MASK   0x3fffffff

Definition at line 44 of file hda_controller_defs.h.

◆ NVIDIA_HDA_ENABLE_COHBIT

#define NVIDIA_HDA_ENABLE_COHBIT   0x01

Definition at line 150 of file hda_controller_defs.h.

◆ NVIDIA_HDA_ENABLE_COHBITS

#define NVIDIA_HDA_ENABLE_COHBITS   0x0f

Definition at line 153 of file hda_controller_defs.h.

◆ NVIDIA_HDA_ISTRM_COH

#define NVIDIA_HDA_ISTRM_COH   0x4d

Definition at line 149 of file hda_controller_defs.h.

◆ NVIDIA_HDA_OSTRM_COH

#define NVIDIA_HDA_OSTRM_COH   0x4c

Definition at line 148 of file hda_controller_defs.h.

◆ NVIDIA_HDA_TRANSREG

#define NVIDIA_HDA_TRANSREG   0x4e

Definition at line 151 of file hda_controller_defs.h.

◆ NVIDIA_HDA_TRANSREG_MASK

#define NVIDIA_HDA_TRANSREG_MASK   0xf0

Definition at line 152 of file hda_controller_defs.h.

◆ PCI_HDA_TCSEL

#define PCI_HDA_TCSEL   0x44

Definition at line 142 of file hda_controller_defs.h.

◆ PCI_HDA_TCSEL_MASK

#define PCI_HDA_TCSEL_MASK   0xf8

Definition at line 143 of file hda_controller_defs.h.

◆ RESPONSE_FLAGS_CODEC_MASK

#define RESPONSE_FLAGS_CODEC_MASK   0x0000000f

Definition at line 166 of file hda_controller_defs.h.

◆ RESPONSE_FLAGS_UNSOLICITED

#define RESPONSE_FLAGS_UNSOLICITED   (1 << 4)

Definition at line 167 of file hda_controller_defs.h.

◆ RIRB_CONTROL_DMA_ENABLE

#define RIRB_CONTROL_DMA_ENABLE   (1 << 1)

Definition at line 83 of file hda_controller_defs.h.

◆ RIRB_CONTROL_OVERRUN_INTR

#define RIRB_CONTROL_OVERRUN_INTR   (1 << 2)

Definition at line 82 of file hda_controller_defs.h.

◆ RIRB_CONTROL_RESPONSE_INTR

#define RIRB_CONTROL_RESPONSE_INTR   (1 << 0)

Definition at line 84 of file hda_controller_defs.h.

◆ RIRB_SIZE_16_ENTRIES

#define RIRB_SIZE_16_ENTRIES   0x01

Definition at line 96 of file hda_controller_defs.h.

◆ RIRB_SIZE_256_ENTRIES

#define RIRB_SIZE_256_ENTRIES   0x02

Definition at line 97 of file hda_controller_defs.h.

◆ RIRB_SIZE_2_ENTRIES

#define RIRB_SIZE_2_ENTRIES   0x00

Definition at line 95 of file hda_controller_defs.h.

◆ RIRB_SIZE_CAP_16_ENTRIES

#define RIRB_SIZE_CAP_16_ENTRIES   (1 << 5)

Definition at line 93 of file hda_controller_defs.h.

◆ RIRB_SIZE_CAP_256_ENTRIES

#define RIRB_SIZE_CAP_256_ENTRIES   (1 << 6)

Definition at line 94 of file hda_controller_defs.h.

◆ RIRB_SIZE_CAP_2_ENTRIES

#define RIRB_SIZE_CAP_2_ENTRIES   (1 << 4)

Definition at line 92 of file hda_controller_defs.h.

◆ RIRB_STATUS_OVERRUN

#define RIRB_STATUS_OVERRUN   (1 << 2)

Definition at line 87 of file hda_controller_defs.h.

◆ RIRB_STATUS_RESPONSE

#define RIRB_STATUS_RESPONSE   (1 << 0)

Definition at line 88 of file hda_controller_defs.h.

◆ RIRB_WRITE_POS_RESET

#define RIRB_WRITE_POS_RESET   (1 << 15)

Definition at line 75 of file hda_controller_defs.h.

◆ STATUS_BUFFER_COMPLETED

#define STATUS_BUFFER_COMPLETED   (1 << 2)

Definition at line 121 of file hda_controller_defs.h.

◆ STATUS_DESCRIPTOR_ERROR

#define STATUS_DESCRIPTOR_ERROR   (1 << 4)

Definition at line 123 of file hda_controller_defs.h.

◆ STATUS_FIFO_ERROR

#define STATUS_FIFO_ERROR   (1 << 3)

Definition at line 122 of file hda_controller_defs.h.

◆ STATUS_FIFO_READY

#define STATUS_FIFO_READY   (1 << 5)

Definition at line 124 of file hda_controller_defs.h.

Typedef Documentation

◆ corb_t

typedef uint32 corb_t

Definition at line 159 of file hda_controller_defs.h.