ReactOS 0.4.17-dev-577-ge3e58ac
Typedefs | Enumerations | Functions
armintr.h File Reference

Go to the source code of this file.

Typedefs

typedef enum _tag_ARMINTR_SHIFT_T _ARMINTR_SHIFT_T
 
typedef enum _tag_ARMINTR_CPS_OP _ARMINTR_CPS_OP
 
typedef enum _tag_ARMINTR_CPS_FLAG _ARMINTR_CPS_FLAG
 
typedef enum _tag_ARMINTR_BARRIER_TYPE _ARMINTR_BARRIER_TYPE
 
typedef enum _tag_ARMINTR_BANKED_REG _ARMINTR_BANKED_REG
 

Enumerations

enum  _tag_ARMINTR_SHIFT_T { _ARM_LSR = 0 , _ARM_LSL = 1 , _ARM_ASR = 2 , _ARM_ROR = 3 }
 
enum  _tag_ARMINTR_CPS_OP { _ARM_CPS_ENABLE_INTERRUPTS = 1 , _ARM_CPS_DISABLE_INTERRUPTS = 2 , _ARM_CPS_CHANGE_MODE = 4 }
 
enum  _tag_ARMINTR_CPS_FLAG { _ARM_CPS_INTERRUPT_FLAG_F = 1 , _ARM_CPS_INTERRUPT_FLAG_I = 2 , _ARM_CPS_INTERRUPT_FLAG_A = 4 }
 
enum  _tag_ARMINTR_BARRIER_TYPE {
  _ARM_BARRIER_SY = 0xF , _ARM_BARRIER_ST = 0xE , _ARM_BARRIER_ISH = 0xB , _ARM_BARRIER_ISHST = 0xA ,
  _ARM_BARRIER_NSH = 0x7 , _ARM_BARRIER_NSHST = 0x6 , _ARM_BARRIER_OSH = 0x3 , _ARM_BARRIER_OSHST = 0x2
}
 
enum  _tag_ARMINTR_BANKED_REG {
  _ARM_BANKED_R8_USR = 0x0 , _ARM_BANKED_R9_USR = 0x1 , _ARM_BANKED_R10_USR = 0x2 , _ARM_BANKED_R11_USR = 0x3 ,
  _ARM_BANKED_R12_USR = 0x4 , _ARM_BANKED_R13_USR = 0x5 , _ARM_BANKED_SP_USR = 0x5 , _ARM_BANKED_R14_USR = 0x6 ,
  _ARM_BANKED_LR_USR = 0x6 , _ARM_BANKED_R8_FIQ = 0x8 , _ARM_BANKED_R9_FIQ = 0x9 , _ARM_BANKED_R10_FIQ = 0xA ,
  _ARM_BANKED_R11_FIQ = 0xB , _ARM_BANKED_R12_FIQ = 0xC , _ARM_BANKED_R13_FIQ = 0xD , _ARM_BANKED_SP_FIQ = 0xD ,
  _ARM_BANKED_R14_FIQ = 0xE , _ARM_BANKED_LR_FIQ = 0xE , _ARM_BANKED_R14_IRQ = 0x10 , _ARM_BANKED_LR_IRQ = 0x10 ,
  _ARM_BANKED_R13_IRQ = 0x11 , _ARM_BANKED_SP_IRQ = 0x11 , _ARM_BANKED_R14_SVC = 0x12 , _ARM_BANKED_LR_SVC = 0x12 ,
  _ARM_BANKED_R13_SVC = 0x13 , _ARM_BANKED_SP_SVC = 0x13 , _ARM_BANKED_R14_ABT = 0x14 , _ARM_BANKED_LR_ABT = 0x14 ,
  _ARM_BANKED_R13_ABT = 0x15 , _ARM_BANKED_SP_ABT = 0x15 , _ARM_BANKED_R14_UND = 0x16 , _ARM_BANKED_LR_UND = 0x16 ,
  _ARM_BANKED_R13_UND = 0x17 , _ARM_BANKED_SP_UND = 0x17 , _ARM_BANKED_R14_MON = 0x1C , _ARM_BANKED_LR_MON = 0x1C ,
  _ARM_BANKED_R13_MON = 0x1D , _ARM_BANKED_SP_MON = 0x1D , _ARM_BANKED_ELR_HYP = 0x1E , _ARM_BANKED_R13_HYP = 0x1F ,
  _ARM_BANKED_SP_HYP = 0x1F , _ARM_BANKED_SPSR_FIQ = 0x2E , _ARM_BANKED_SPSR_IRQ = 0x30 , _ARM_BANKED_SPSR_SVC = 0x32 ,
  _ARM_BANKED_SPSR_ABT = 0x34 , _ARM_BANKED_SPSR_UND = 0x36 , _ARM_BANKED_SPSR_MON = 0x3C , _ARM_BANKED_SPSR_HYP = 0x3E
}
 

Functions

void __dmb (unsigned int Type)
 
void __dsb (unsigned int Type)
 
void __isb (unsigned int Type)
 

Typedef Documentation

◆ _ARMINTR_BANKED_REG

typedef enum _tag_ARMINTR_BANKED_REG _ARMINTR_BANKED_REG

◆ _ARMINTR_BARRIER_TYPE

typedef enum _tag_ARMINTR_BARRIER_TYPE _ARMINTR_BARRIER_TYPE

◆ _ARMINTR_CPS_FLAG

typedef enum _tag_ARMINTR_CPS_FLAG _ARMINTR_CPS_FLAG

◆ _ARMINTR_CPS_OP

typedef enum _tag_ARMINTR_CPS_OP _ARMINTR_CPS_OP

◆ _ARMINTR_SHIFT_T

typedef enum _tag_ARMINTR_SHIFT_T _ARMINTR_SHIFT_T

Enumeration Type Documentation

◆ _tag_ARMINTR_BANKED_REG

enum _tag_ARMINTR_BANKED_REG
Enumerator
_ARM_BANKED_R8_USR 
_ARM_BANKED_R9_USR 
_ARM_BANKED_R10_USR 
_ARM_BANKED_R11_USR 
_ARM_BANKED_R12_USR 
_ARM_BANKED_R13_USR 
_ARM_BANKED_SP_USR 
_ARM_BANKED_R14_USR 
_ARM_BANKED_LR_USR 
_ARM_BANKED_R8_FIQ 
_ARM_BANKED_R9_FIQ 
_ARM_BANKED_R10_FIQ 
_ARM_BANKED_R11_FIQ 
_ARM_BANKED_R12_FIQ 
_ARM_BANKED_R13_FIQ 
_ARM_BANKED_SP_FIQ 
_ARM_BANKED_R14_FIQ 
_ARM_BANKED_LR_FIQ 
_ARM_BANKED_R14_IRQ 
_ARM_BANKED_LR_IRQ 
_ARM_BANKED_R13_IRQ 
_ARM_BANKED_SP_IRQ 
_ARM_BANKED_R14_SVC 
_ARM_BANKED_LR_SVC 
_ARM_BANKED_R13_SVC 
_ARM_BANKED_SP_SVC 
_ARM_BANKED_R14_ABT 
_ARM_BANKED_LR_ABT 
_ARM_BANKED_R13_ABT 
_ARM_BANKED_SP_ABT 
_ARM_BANKED_R14_UND 
_ARM_BANKED_LR_UND 
_ARM_BANKED_R13_UND 
_ARM_BANKED_SP_UND 
_ARM_BANKED_R14_MON 
_ARM_BANKED_LR_MON 
_ARM_BANKED_R13_MON 
_ARM_BANKED_SP_MON 
_ARM_BANKED_ELR_HYP 
_ARM_BANKED_R13_HYP 
_ARM_BANKED_SP_HYP 
_ARM_BANKED_SPSR_FIQ 
_ARM_BANKED_SPSR_IRQ 
_ARM_BANKED_SPSR_SVC 
_ARM_BANKED_SPSR_ABT 
_ARM_BANKED_SPSR_UND 
_ARM_BANKED_SPSR_MON 
_ARM_BANKED_SPSR_HYP 

Definition at line 43 of file armintr.h.

44{
45 _ARM_BANKED_R8_USR = 0x0,
46 _ARM_BANKED_R9_USR = 0x1,
47 _ARM_BANKED_R10_USR = 0x2,
48 _ARM_BANKED_R11_USR = 0x3,
49 _ARM_BANKED_R12_USR = 0x4,
50 _ARM_BANKED_R13_USR = 0x5,
51 _ARM_BANKED_SP_USR = 0x5,
52 _ARM_BANKED_R14_USR = 0x6,
53 _ARM_BANKED_LR_USR = 0x6,
54 _ARM_BANKED_R8_FIQ = 0x8,
55 _ARM_BANKED_R9_FIQ = 0x9,
56 _ARM_BANKED_R10_FIQ = 0xA,
57 _ARM_BANKED_R11_FIQ = 0xB,
58 _ARM_BANKED_R12_FIQ = 0xC,
59 _ARM_BANKED_R13_FIQ = 0xD,
60 _ARM_BANKED_SP_FIQ = 0xD,
61 _ARM_BANKED_R14_FIQ = 0xE,
62 _ARM_BANKED_LR_FIQ = 0xE,
63 _ARM_BANKED_R14_IRQ = 0x10,
64 _ARM_BANKED_LR_IRQ = 0x10,
65 _ARM_BANKED_R13_IRQ = 0x11,
66 _ARM_BANKED_SP_IRQ = 0x11,
67 _ARM_BANKED_R14_SVC = 0x12,
68 _ARM_BANKED_LR_SVC = 0x12,
69 _ARM_BANKED_R13_SVC = 0x13,
70 _ARM_BANKED_SP_SVC = 0x13,
71 _ARM_BANKED_R14_ABT = 0x14,
72 _ARM_BANKED_LR_ABT = 0x14,
73 _ARM_BANKED_R13_ABT = 0x15,
74 _ARM_BANKED_SP_ABT = 0x15,
75 _ARM_BANKED_R14_UND = 0x16,
76 _ARM_BANKED_LR_UND = 0x16,
77 _ARM_BANKED_R13_UND = 0x17,
78 _ARM_BANKED_SP_UND = 0x17,
79 _ARM_BANKED_R14_MON = 0x1C,
80 _ARM_BANKED_LR_MON = 0x1C,
81 _ARM_BANKED_R13_MON = 0x1D,
82 _ARM_BANKED_SP_MON = 0x1D,
83 _ARM_BANKED_ELR_HYP = 0x1E,
84 _ARM_BANKED_R13_HYP = 0x1F,
85 _ARM_BANKED_SP_HYP = 0x1F,
86 _ARM_BANKED_SPSR_FIQ = 0x2E,
87 _ARM_BANKED_SPSR_IRQ = 0x30,
88 _ARM_BANKED_SPSR_SVC = 0x32,
89 _ARM_BANKED_SPSR_ABT = 0x34,
90 _ARM_BANKED_SPSR_UND = 0x36,
91 _ARM_BANKED_SPSR_MON = 0x3C,
92 _ARM_BANKED_SPSR_HYP = 0x3E
93} _ARMINTR_BANKED_REG;
_ARM_BANKED_R13_HYP
@ _ARM_BANKED_R13_HYP
Definition: armintr.h:84
_ARM_BANKED_SPSR_HYP
@ _ARM_BANKED_SPSR_HYP
Definition: armintr.h:92
_ARM_BANKED_R14_UND
@ _ARM_BANKED_R14_UND
Definition: armintr.h:75
_ARM_BANKED_R14_ABT
@ _ARM_BANKED_R14_ABT
Definition: armintr.h:71
_ARM_BANKED_SP_ABT
@ _ARM_BANKED_SP_ABT
Definition: armintr.h:74
_ARM_BANKED_SP_IRQ
@ _ARM_BANKED_SP_IRQ
Definition: armintr.h:66
_ARM_BANKED_LR_FIQ
@ _ARM_BANKED_LR_FIQ
Definition: armintr.h:62
_ARM_BANKED_R10_FIQ
@ _ARM_BANKED_R10_FIQ
Definition: armintr.h:56
_ARM_BANKED_SP_FIQ
@ _ARM_BANKED_SP_FIQ
Definition: armintr.h:60
_ARM_BANKED_LR_ABT
@ _ARM_BANKED_LR_ABT
Definition: armintr.h:72
_ARM_BANKED_R14_FIQ
@ _ARM_BANKED_R14_FIQ
Definition: armintr.h:61
_ARM_BANKED_SP_SVC
@ _ARM_BANKED_SP_SVC
Definition: armintr.h:70
_ARM_BANKED_R13_MON
@ _ARM_BANKED_R13_MON
Definition: armintr.h:81
_ARM_BANKED_LR_UND
@ _ARM_BANKED_LR_UND
Definition: armintr.h:76
_ARM_BANKED_SP_MON
@ _ARM_BANKED_SP_MON
Definition: armintr.h:82
_ARM_BANKED_R13_ABT
@ _ARM_BANKED_R13_ABT
Definition: armintr.h:73
_ARM_BANKED_R9_USR
@ _ARM_BANKED_R9_USR
Definition: armintr.h:46
_ARM_BANKED_SPSR_FIQ
@ _ARM_BANKED_SPSR_FIQ
Definition: armintr.h:86
_ARM_BANKED_SPSR_MON
@ _ARM_BANKED_SPSR_MON
Definition: armintr.h:91
_ARM_BANKED_SP_HYP
@ _ARM_BANKED_SP_HYP
Definition: armintr.h:85
_ARM_BANKED_LR_IRQ
@ _ARM_BANKED_LR_IRQ
Definition: armintr.h:64
_ARM_BANKED_ELR_HYP
@ _ARM_BANKED_ELR_HYP
Definition: armintr.h:83
_ARM_BANKED_R14_USR
@ _ARM_BANKED_R14_USR
Definition: armintr.h:52
_ARM_BANKED_R14_SVC
@ _ARM_BANKED_R14_SVC
Definition: armintr.h:67
_ARM_BANKED_R14_IRQ
@ _ARM_BANKED_R14_IRQ
Definition: armintr.h:63
_ARM_BANKED_SP_USR
@ _ARM_BANKED_SP_USR
Definition: armintr.h:51
_ARM_BANKED_R11_FIQ
@ _ARM_BANKED_R11_FIQ
Definition: armintr.h:57
_ARM_BANKED_R8_FIQ
@ _ARM_BANKED_R8_FIQ
Definition: armintr.h:54
_ARM_BANKED_R10_USR
@ _ARM_BANKED_R10_USR
Definition: armintr.h:47
_ARM_BANKED_R13_IRQ
@ _ARM_BANKED_R13_IRQ
Definition: armintr.h:65
_ARM_BANKED_LR_SVC
@ _ARM_BANKED_LR_SVC
Definition: armintr.h:68
_ARM_BANKED_R13_SVC
@ _ARM_BANKED_R13_SVC
Definition: armintr.h:69
_ARM_BANKED_R9_FIQ
@ _ARM_BANKED_R9_FIQ
Definition: armintr.h:55
_ARM_BANKED_R8_USR
@ _ARM_BANKED_R8_USR
Definition: armintr.h:45
_ARM_BANKED_LR_MON
@ _ARM_BANKED_LR_MON
Definition: armintr.h:80
_ARM_BANKED_SPSR_SVC
@ _ARM_BANKED_SPSR_SVC
Definition: armintr.h:88
_ARM_BANKED_LR_USR
@ _ARM_BANKED_LR_USR
Definition: armintr.h:53
_ARM_BANKED_R14_MON
@ _ARM_BANKED_R14_MON
Definition: armintr.h:79
_ARM_BANKED_R12_FIQ
@ _ARM_BANKED_R12_FIQ
Definition: armintr.h:58
_ARM_BANKED_R13_UND
@ _ARM_BANKED_R13_UND
Definition: armintr.h:77
_ARM_BANKED_SP_UND
@ _ARM_BANKED_SP_UND
Definition: armintr.h:78
_ARM_BANKED_SPSR_ABT
@ _ARM_BANKED_SPSR_ABT
Definition: armintr.h:89
_ARM_BANKED_SPSR_IRQ
@ _ARM_BANKED_SPSR_IRQ
Definition: armintr.h:87
_ARM_BANKED_R12_USR
@ _ARM_BANKED_R12_USR
Definition: armintr.h:49
_ARM_BANKED_R13_FIQ
@ _ARM_BANKED_R13_FIQ
Definition: armintr.h:59
_ARM_BANKED_SPSR_UND
@ _ARM_BANKED_SPSR_UND
Definition: armintr.h:90
_ARM_BANKED_R13_USR
@ _ARM_BANKED_R13_USR
Definition: armintr.h:50
_ARM_BANKED_R11_USR
@ _ARM_BANKED_R11_USR
Definition: armintr.h:48
_ARMINTR_BANKED_REG
enum _tag_ARMINTR_BANKED_REG _ARMINTR_BANKED_REG

◆ _tag_ARMINTR_BARRIER_TYPE

enum _tag_ARMINTR_BARRIER_TYPE
Enumerator
_ARM_BARRIER_SY 
_ARM_BARRIER_ST 
_ARM_BARRIER_ISH 
_ARM_BARRIER_ISHST 
_ARM_BARRIER_NSH 
_ARM_BARRIER_NSHST 
_ARM_BARRIER_OSH 
_ARM_BARRIER_OSHST 

Definition at line 31 of file armintr.h.

32{
33 _ARM_BARRIER_SY = 0xF,
34 _ARM_BARRIER_ST = 0xE,
35 _ARM_BARRIER_ISH = 0xB,
36 _ARM_BARRIER_ISHST = 0xA,
37 _ARM_BARRIER_NSH = 0x7,
38 _ARM_BARRIER_NSHST = 0x6,
39 _ARM_BARRIER_OSH = 0x3,
40 _ARM_BARRIER_OSHST = 0x2
41} _ARMINTR_BARRIER_TYPE;
_ARM_BARRIER_NSHST
@ _ARM_BARRIER_NSHST
Definition: armintr.h:38
_ARM_BARRIER_NSH
@ _ARM_BARRIER_NSH
Definition: armintr.h:37
_ARM_BARRIER_ST
@ _ARM_BARRIER_ST
Definition: armintr.h:34
_ARM_BARRIER_ISH
@ _ARM_BARRIER_ISH
Definition: armintr.h:35
_ARM_BARRIER_ISHST
@ _ARM_BARRIER_ISHST
Definition: armintr.h:36
_ARM_BARRIER_SY
@ _ARM_BARRIER_SY
Definition: armintr.h:33
_ARM_BARRIER_OSH
@ _ARM_BARRIER_OSH
Definition: armintr.h:39
_ARM_BARRIER_OSHST
@ _ARM_BARRIER_OSHST
Definition: armintr.h:40
_ARMINTR_BARRIER_TYPE
enum _tag_ARMINTR_BARRIER_TYPE _ARMINTR_BARRIER_TYPE

◆ _tag_ARMINTR_CPS_FLAG

enum _tag_ARMINTR_CPS_FLAG
Enumerator
_ARM_CPS_INTERRUPT_FLAG_F 
_ARM_CPS_INTERRUPT_FLAG_I 
_ARM_CPS_INTERRUPT_FLAG_A 

Definition at line 24 of file armintr.h.

25{
26 _ARM_CPS_INTERRUPT_FLAG_F = 1,
27 _ARM_CPS_INTERRUPT_FLAG_I = 2,
28 _ARM_CPS_INTERRUPT_FLAG_A = 4
29} _ARMINTR_CPS_FLAG;
_ARM_CPS_INTERRUPT_FLAG_I
@ _ARM_CPS_INTERRUPT_FLAG_I
Definition: armintr.h:27
_ARM_CPS_INTERRUPT_FLAG_F
@ _ARM_CPS_INTERRUPT_FLAG_F
Definition: armintr.h:26
_ARM_CPS_INTERRUPT_FLAG_A
@ _ARM_CPS_INTERRUPT_FLAG_A
Definition: armintr.h:28
_ARMINTR_CPS_FLAG
enum _tag_ARMINTR_CPS_FLAG _ARMINTR_CPS_FLAG

◆ _tag_ARMINTR_CPS_OP

enum _tag_ARMINTR_CPS_OP
Enumerator
_ARM_CPS_ENABLE_INTERRUPTS 
_ARM_CPS_DISABLE_INTERRUPTS 
_ARM_CPS_CHANGE_MODE 

Definition at line 17 of file armintr.h.

18{
19 _ARM_CPS_ENABLE_INTERRUPTS = 1,
20 _ARM_CPS_DISABLE_INTERRUPTS = 2,
21 _ARM_CPS_CHANGE_MODE = 4
22} _ARMINTR_CPS_OP;
_ARMINTR_CPS_OP
enum _tag_ARMINTR_CPS_OP _ARMINTR_CPS_OP
_ARM_CPS_CHANGE_MODE
@ _ARM_CPS_CHANGE_MODE
Definition: armintr.h:21
_ARM_CPS_DISABLE_INTERRUPTS
@ _ARM_CPS_DISABLE_INTERRUPTS
Definition: armintr.h:20
_ARM_CPS_ENABLE_INTERRUPTS
@ _ARM_CPS_ENABLE_INTERRUPTS
Definition: armintr.h:19

◆ _tag_ARMINTR_SHIFT_T

enum _tag_ARMINTR_SHIFT_T
Enumerator
_ARM_LSR 
_ARM_LSL 
_ARM_ASR 
_ARM_ROR 

Definition at line 9 of file armintr.h.

10{
11 _ARM_LSR = 0,
12 _ARM_LSL = 1,
13 _ARM_ASR = 2,
14 _ARM_ROR = 3
15} _ARMINTR_SHIFT_T;
_ARM_ASR
@ _ARM_ASR
Definition: armintr.h:13
_ARM_LSL
@ _ARM_LSL
Definition: armintr.h:12
_ARM_ROR
@ _ARM_ROR
Definition: armintr.h:14
_ARM_LSR
@ _ARM_LSR
Definition: armintr.h:11
_ARMINTR_SHIFT_T
enum _tag_ARMINTR_SHIFT_T _ARMINTR_SHIFT_T

Function Documentation

◆ __dmb()

void __dmb ( unsigned int  Type)

Definition at line 694 of file intrin_arm64.h.

695{
696 /* MS _ARM64_BARRIER_* constants: OSHLD=1 OSHST=2 OSH=3 NSHLD=5 NSHST=6
697 NSH=7 ISHLD=9 ISHST=10 ISH=11 LD=13 ST=14 SY=15. The dmb option must
698 be an assembler literal, so we dispatch on the runtime value. */
699 switch (type)
700 {
701 case 1: __asm__ __volatile__("dmb oshld" ::: "memory"); break;
702 case 2: __asm__ __volatile__("dmb oshst" ::: "memory"); break;
703 case 3: __asm__ __volatile__("dmb osh" ::: "memory"); break;
704 case 5: __asm__ __volatile__("dmb nshld" ::: "memory"); break;
705 case 6: __asm__ __volatile__("dmb nshst" ::: "memory"); break;
706 case 7: __asm__ __volatile__("dmb nsh" ::: "memory"); break;
707 case 9: __asm__ __volatile__("dmb ishld" ::: "memory"); break;
708 case 10: __asm__ __volatile__("dmb ishst" ::: "memory"); break;
709 case 11: __asm__ __volatile__("dmb ish" ::: "memory"); break;
710 case 13: __asm__ __volatile__("dmb ld" ::: "memory"); break;
711 case 14: __asm__ __volatile__("dmb st" ::: "memory"); break;
712 default: __asm__ __volatile__("dmb sy" ::: "memory"); break;
713 }
714}
type
GLuint GLuint GLsizei GLenum type
Definition: gl.h:1545
__asm__
__asm__(".p2align 4, 0x90\n" ".seh_proc __seh2_global_filter_func\n" "__seh2_global_filter_func:\n" "\tsub %rbp, %rax\n" "\tpush %rbp\n" "\t.seh_pushreg %rbp\n" "\tpush %rbx\n" "\t.seh_pushreg %rbx\n" "\tpush %rdi\n" "\t.seh_pushreg %rdi\n" "\tpush %rsi\n" "\t.seh_pushreg %rsi\n" "\tpush %r12\n" "\t.seh_pushreg %r12\n" "\tpush %r13\n" "\t.seh_pushreg %r13\n" "\tpush %r14\n" "\t.seh_pushreg %r14\n" "\tpush %r15\n" "\t.seh_pushreg %r15\n" "\tsub $40, %rsp\n" "\t.seh_stackalloc 40\n" "\t.seh_endprologue\n" "\tsub %rax, %rdx\n" "\tmov %rdx, %rbp\n" "\tjmp *%r8\n" "__seh2_global_filter_func_exit:\n" "\t.p2align 4\n" "\tadd $40, %rsp\n" "\tpop %r15\n" "\tpop %r14\n" "\tpop %r13\n" "\tpop %r12\n" "\tpop %rsi\n" "\tpop %rdi\n" "\tpop %rbx\n" "\tpop %rbp\n" "\tret\n" "\t.seh_endproc")

◆ __dsb()

void __dsb ( unsigned int  Type)

Definition at line 718 of file intrin_arm64.h.

719{
720 switch (type)
721 {
722 case 1: __asm__ __volatile__("dsb oshld" ::: "memory"); break;
723 case 2: __asm__ __volatile__("dsb oshst" ::: "memory"); break;
724 case 3: __asm__ __volatile__("dsb osh" ::: "memory"); break;
725 case 5: __asm__ __volatile__("dsb nshld" ::: "memory"); break;
726 case 6: __asm__ __volatile__("dsb nshst" ::: "memory"); break;
727 case 7: __asm__ __volatile__("dsb nsh" ::: "memory"); break;
728 case 9: __asm__ __volatile__("dsb ishld" ::: "memory"); break;
729 case 10: __asm__ __volatile__("dsb ishst" ::: "memory"); break;
730 case 11: __asm__ __volatile__("dsb ish" ::: "memory"); break;
731 case 13: __asm__ __volatile__("dsb ld" ::: "memory"); break;
732 case 14: __asm__ __volatile__("dsb st" ::: "memory"); break;
733 default: __asm__ __volatile__("dsb sy" ::: "memory"); break;
734 }
735}

◆ __isb()

void __isb ( unsigned int  Type)

Definition at line 739 of file intrin_arm64.h.

740{
741 /* ISB on ARM64 only supports the 'sy' option; accept the type arg
742 for API compatibility with MS docs and ignore it. */
743 (void)type;
744 __asm__ __volatile__("isb" ::: "memory");
745}