ReactOS  0.4.15-dev-509-g96a357b
pci.h File Reference
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Macros

#define PCI_PCIID   0x0 /* pci id - query 32 bits */
 
#define PCI_VENID   0x0 /* vendor ID */
 
#define PCI_DEVID   0x2 /* device ID */
 
#define PCI_COMMAND   0x4 /* command register */
 
#define PCI_STATUS   0x6 /* status register */
 
#define PCI_REVID   0x8 /* revision ID */
 
#define PCI_PIR   0x9 /* programming interface register */
 
#define PCI_SCR   0xa /* sub-class register */
 
#define PCI_BCR   0xb /* base-class register */
 
#define PCI_LTR   0xd /* latency timer register */
 
#define PCI_HTR   0xe /* header type register */
 
#define PCI_IOBAR   0x10 /* i/o base address register */
 
#define PCI_MMBAR   0x14 /* i/o memory-mapped base address register */
 
#define PCI_ERBAR   0x30 /* expansion rom base address register */
 
#define PCI_ILR   0x3c /* interrupt line register */
 
#define PCI_IPR   0x3d /* interrupt pin register */
 
#define PCI_MINGNT   0x3e /* min_gnt register */
 
#define PCI_MAXLAT   0x3f /* max_lat register */
 
#define PCI_IOEN   0x1 /* i/o space access enable */
 
#define PCI_MEMEN   0x2 /* memory space access enable */
 
#define PCI_BMEN   0x4 /* bus master enable */
 
#define PCI_SCYCEN   0x8 /* special cycle enable */
 
#define PCI_MWIEN   0X10 /* memory write and invalidate cycle enable */
 
#define PCI_VGASNOOP   0x20 /* vga palette snoop */
 
#define PCI_PERREN   0x40 /* parity error response enable */
 
#define PCI_ADSTEP   0x80 /* address/data stepping */
 
#define PCI_SERREN   0x100 /* signalled error enable */
 
#define PCI_FBTBEN   0X200 /* fast back-to-back enable */
 
#define PCI_FBTBC   0x80 /* fast back-to-back capable */
 
#define PCI_DATAPERR   0x100 /* data parity error detected */
 
#define PCI_DEVSEL1   0x200 /* device select timing lsb */
 
#define PCI_DEVSEL2   0x400 /* device select timing msb */
 
#define PCI_STABORT   0x800 /* send target abort */
 
#define PCI_RTABORT   0x1000 /* received target abort */
 
#define PCI_SERR   0x2000 /* signalled error */
 
#define PCI_PERR   0x4000 /* parity error */
 

Macro Definition Documentation

◆ PCI_ADSTEP

#define PCI_ADSTEP   0x80 /* address/data stepping */

Definition at line 56 of file pci.h.

◆ PCI_BCR

#define PCI_BCR   0xb /* base-class register */

Definition at line 37 of file pci.h.

◆ PCI_BMEN

#define PCI_BMEN   0x4 /* bus master enable */

Definition at line 51 of file pci.h.

◆ PCI_COMMAND

#define PCI_COMMAND   0x4 /* command register */

Definition at line 32 of file pci.h.

◆ PCI_DATAPERR

#define PCI_DATAPERR   0x100 /* data parity error detected */

Definition at line 62 of file pci.h.

◆ PCI_DEVID

#define PCI_DEVID   0x2 /* device ID */

Definition at line 31 of file pci.h.

◆ PCI_DEVSEL1

#define PCI_DEVSEL1   0x200 /* device select timing lsb */

Definition at line 63 of file pci.h.

◆ PCI_DEVSEL2

#define PCI_DEVSEL2   0x400 /* device select timing msb */

Definition at line 64 of file pci.h.

◆ PCI_ERBAR

#define PCI_ERBAR   0x30 /* expansion rom base address register */

Definition at line 42 of file pci.h.

◆ PCI_FBTBC

#define PCI_FBTBC   0x80 /* fast back-to-back capable */

Definition at line 61 of file pci.h.

◆ PCI_FBTBEN

#define PCI_FBTBEN   0X200 /* fast back-to-back enable */

Definition at line 58 of file pci.h.

◆ PCI_HTR

#define PCI_HTR   0xe /* header type register */

Definition at line 39 of file pci.h.

◆ PCI_ILR

#define PCI_ILR   0x3c /* interrupt line register */

Definition at line 43 of file pci.h.

◆ PCI_IOBAR

#define PCI_IOBAR   0x10 /* i/o base address register */

Definition at line 40 of file pci.h.

◆ PCI_IOEN

#define PCI_IOEN   0x1 /* i/o space access enable */

Definition at line 49 of file pci.h.

◆ PCI_IPR

#define PCI_IPR   0x3d /* interrupt pin register */

Definition at line 44 of file pci.h.

◆ PCI_LTR

#define PCI_LTR   0xd /* latency timer register */

Definition at line 38 of file pci.h.

◆ PCI_MAXLAT

#define PCI_MAXLAT   0x3f /* max_lat register */

Definition at line 46 of file pci.h.

◆ PCI_MEMEN

#define PCI_MEMEN   0x2 /* memory space access enable */

Definition at line 50 of file pci.h.

◆ PCI_MINGNT

#define PCI_MINGNT   0x3e /* min_gnt register */

Definition at line 45 of file pci.h.

◆ PCI_MMBAR

#define PCI_MMBAR   0x14 /* i/o memory-mapped base address register */

Definition at line 41 of file pci.h.

◆ PCI_MWIEN

#define PCI_MWIEN   0X10 /* memory write and invalidate cycle enable */

Definition at line 53 of file pci.h.

◆ PCI_PCIID

#define PCI_PCIID   0x0 /* pci id - query 32 bits */

Definition at line 29 of file pci.h.

◆ PCI_PERR

#define PCI_PERR   0x4000 /* parity error */

Definition at line 68 of file pci.h.

◆ PCI_PERREN

#define PCI_PERREN   0x40 /* parity error response enable */

Definition at line 55 of file pci.h.

◆ PCI_PIR

#define PCI_PIR   0x9 /* programming interface register */

Definition at line 35 of file pci.h.

◆ PCI_REVID

#define PCI_REVID   0x8 /* revision ID */

Definition at line 34 of file pci.h.

◆ PCI_RTABORT

#define PCI_RTABORT   0x1000 /* received target abort */

Definition at line 66 of file pci.h.

◆ PCI_SCR

#define PCI_SCR   0xa /* sub-class register */

Definition at line 36 of file pci.h.

◆ PCI_SCYCEN

#define PCI_SCYCEN   0x8 /* special cycle enable */

Definition at line 52 of file pci.h.

◆ PCI_SERR

#define PCI_SERR   0x2000 /* signalled error */

Definition at line 67 of file pci.h.

◆ PCI_SERREN

#define PCI_SERREN   0x100 /* signalled error enable */

Definition at line 57 of file pci.h.

◆ PCI_STABORT

#define PCI_STABORT   0x800 /* send target abort */

Definition at line 65 of file pci.h.

◆ PCI_STATUS

#define PCI_STATUS   0x6 /* status register */

Definition at line 33 of file pci.h.

◆ PCI_VENID

#define PCI_VENID   0x0 /* vendor ID */

Definition at line 30 of file pci.h.

◆ PCI_VGASNOOP

#define PCI_VGASNOOP   0x20 /* vga palette snoop */

Definition at line 54 of file pci.h.