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| #define | PCI_PCIID 0x0 /* pci id - query 32 bits */ |
| |
| #define | PCI_VENID 0x0 /* vendor ID */ |
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| #define | PCI_DEVID 0x2 /* device ID */ |
| |
| #define | PCI_COMMAND 0x4 /* command register */ |
| |
| #define | PCI_STATUS 0x6 /* status register */ |
| |
| #define | PCI_REVID 0x8 /* revision ID */ |
| |
| #define | PCI_PIR 0x9 /* programming interface register */ |
| |
| #define | PCI_SCR 0xa /* sub-class register */ |
| |
| #define | PCI_BCR 0xb /* base-class register */ |
| |
| #define | PCI_LTR 0xd /* latency timer register */ |
| |
| #define | PCI_HTR 0xe /* header type register */ |
| |
| #define | PCI_IOBAR 0x10 /* i/o base address register */ |
| |
| #define | PCI_MMBAR 0x14 /* i/o memory-mapped base address register */ |
| |
| #define | PCI_ERBAR 0x30 /* expansion rom base address register */ |
| |
| #define | PCI_ILR 0x3c /* interrupt line register */ |
| |
| #define | PCI_IPR 0x3d /* interrupt pin register */ |
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| #define | PCI_MINGNT 0x3e /* min_gnt register */ |
| |
| #define | PCI_MAXLAT 0x3f /* max_lat register */ |
| |
| #define | PCI_IOEN 0x1 /* i/o space access enable */ |
| |
| #define | PCI_MEMEN 0x2 /* memory space access enable */ |
| |
| #define | PCI_BMEN 0x4 /* bus master enable */ |
| |
| #define | PCI_SCYCEN 0x8 /* special cycle enable */ |
| |
| #define | PCI_MWIEN 0X10 /* memory write and invalidate cycle enable */ |
| |
| #define | PCI_VGASNOOP 0x20 /* vga palette snoop */ |
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| #define | PCI_PERREN 0x40 /* parity error response enable */ |
| |
| #define | PCI_ADSTEP 0x80 /* address/data stepping */ |
| |
| #define | PCI_SERREN 0x100 /* signalled error enable */ |
| |
| #define | PCI_FBTBEN 0X200 /* fast back-to-back enable */ |
| |
| #define | PCI_FBTBC 0x80 /* fast back-to-back capable */ |
| |
| #define | PCI_DATAPERR 0x100 /* data parity error detected */ |
| |
| #define | PCI_DEVSEL1 0x200 /* device select timing lsb */ |
| |
| #define | PCI_DEVSEL2 0x400 /* device select timing msb */ |
| |
| #define | PCI_STABORT 0x800 /* send target abort */ |
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| #define | PCI_RTABORT 0x1000 /* received target abort */ |
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| #define | PCI_SERR 0x2000 /* signalled error */ |
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| #define | PCI_PERR 0x4000 /* parity error */ |
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1.9.6