ReactOS 0.4.15-dev-8138-g1e75ea8
pci.h
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1/*
2 * ReactOS AMD PCNet Driver
3 *
4 * Copyright (C) 2003 Vizzini <vizzini@plasmic.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * PURPOSE:
21 * PCI configuration constants
22 * REVISIONS:
23 * 01-Sept-2003 vizzini - Created
24 */
25
26#pragma once
27
28/* PCI Config Space Offset Definitions */
29#define PCI_PCIID 0x0 /* pci id - query 32 bits */
30#define PCI_VENID 0x0 /* vendor ID */
31#define PCI_DEVID 0x2 /* device ID */
32#define PCI_COMMAND 0x4 /* command register */
33#define PCI_STATUS 0x6 /* status register */
34#define PCI_REVID 0x8 /* revision ID */
35#define PCI_PIR 0x9 /* programming interface register */
36#define PCI_SCR 0xa /* sub-class register */
37#define PCI_BCR 0xb /* base-class register */
38#define PCI_LTR 0xd /* latency timer register */
39#define PCI_HTR 0xe /* header type register */
40#define PCI_IOBAR 0x10 /* i/o base address register */
41#define PCI_MMBAR 0x14 /* i/o memory-mapped base address register */
42#define PCI_ERBAR 0x30 /* expansion rom base address register */
43#define PCI_ILR 0x3c /* interrupt line register */
44#define PCI_IPR 0x3d /* interrupt pin register */
45#define PCI_MINGNT 0x3e /* min_gnt register */
46#define PCI_MAXLAT 0x3f /* max_lat register */
47
48/* PCI Command Register Bits */
49#define PCI_IOEN 0x1 /* i/o space access enable */
50#define PCI_MEMEN 0x2 /* memory space access enable */
51#define PCI_BMEN 0x4 /* bus master enable */
52#define PCI_SCYCEN 0x8 /* special cycle enable */
53#define PCI_MWIEN 0X10 /* memory write and invalidate cycle enable */
54#define PCI_VGASNOOP 0x20 /* vga palette snoop */
55#define PCI_PERREN 0x40 /* parity error response enable */
56#define PCI_ADSTEP 0x80 /* address/data stepping */
57#define PCI_SERREN 0x100 /* signalled error enable */
58#define PCI_FBTBEN 0X200 /* fast back-to-back enable */
59
60/* PCI Status Register Bits */
61#define PCI_FBTBC 0x80 /* fast back-to-back capable */
62#define PCI_DATAPERR 0x100 /* data parity error detected */
63#define PCI_DEVSEL1 0x200 /* device select timing lsb */
64#define PCI_DEVSEL2 0x400 /* device select timing msb */
65#define PCI_STABORT 0x800 /* send target abort */
66#define PCI_RTABORT 0x1000 /* received target abort */
67#define PCI_SERR 0x2000 /* signalled error */
68#define PCI_PERR 0x4000 /* parity error */