ReactOS  0.4.14-dev-606-g14ebc0b
vga.h
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1 /*
2  * PROJECT: ReactOS VGA Miniport Driver
3  * LICENSE: Microsoft NT4 DDK Sample Code License
4  * FILE: win32ss/drivers/miniport/vga_new/vga.h
5  * PURPOSE: Main Header File
6  * PROGRAMMERS: Copyright (c) 1992 Microsoft Corporation
7  * ReactOS Portable Systems Group
8  */
9 
10 #ifndef _VGA_NEW_PCH_
11 #define _VGA_NEW_PCH_
12 
13 #include <ntdef.h>
14 #include <dderror.h>
15 #include <miniport.h>
16 #include <video.h>
17 
18 #include "cmdcnst.h"
19 
20 //
21 // Base address of VGA memory range. Also used as base address of VGA
22 // memory when loading a font, which is done with the VGA mapped at A0000.
23 //
24 
25 #define MEM_VGA 0xA0000
26 #define MEM_VGA_SIZE 0x20000
27 
28 //
29 // For memory mapped IO
30 //
31 
32 #define MEMORY_MAPPED_IO_OFFSET (0xB8000 - 0xA0000)
33 
34 //
35 // Port definitions for filling the ACCESS_RANGES structure in the miniport
36 // information, defines the range of I/O ports the VGA spans.
37 // There is a break in the IO ports - a few ports are used for the parallel
38 // port. Those cannot be defined in the ACCESS_RANGE, but are still mapped
39 // so all VGA ports are in one address range.
40 //
41 
42 #define VGA_BASE_IO_PORT 0x000003B0
43 #define VGA_START_BREAK_PORT 0x000003BB
44 #define VGA_END_BREAK_PORT 0x000003C0
45 #define VGA_MAX_IO_PORT 0x000003DF
46 
47 //
48 // VGA register definitions
49 //
50 // eVb: 3.1 [VGA] - Use offsets from the VGA Port Address instead of absolute
51 #define CRTC_ADDRESS_PORT_MONO 0x0004 // CRT Controller Address and
52 #define CRTC_DATA_PORT_MONO 0x0005 // Data registers in mono mode
53 #define FEAT_CTRL_WRITE_PORT_MONO 0x000A // Feature Control write port
54  // in mono mode
55 #define INPUT_STATUS_1_MONO 0x000A // Input Status 1 register read
56  // port in mono mode
57 #define ATT_INITIALIZE_PORT_MONO INPUT_STATUS_1_MONO
58  // Register to read to reset
59  // Attribute Controller index/data
60 
61 #define ATT_ADDRESS_PORT 0x0010 // Attribute Controller Address and
62 #define ATT_DATA_WRITE_PORT 0x0010 // Data registers share one port
63  // for writes, but only Address is
64  // readable at 0x3C0
65 #define ATT_DATA_READ_PORT 0x0011 // Attribute Controller Data reg is
66  // readable here
67 #define MISC_OUTPUT_REG_WRITE_PORT 0x0012 // Miscellaneous Output reg write
68  // port
69 #define INPUT_STATUS_0_PORT 0x0012 // Input Status 0 register read
70  // port
71 #define VIDEO_SUBSYSTEM_ENABLE_PORT 0x0013 // Bit 0 enables/disables the
72  // entire VGA subsystem
73 #define SEQ_ADDRESS_PORT 0x0014 // Sequence Controller Address and
74 #define SEQ_DATA_PORT 0x0015 // Data registers
75 #define DAC_PIXEL_MASK_PORT 0x0016 // DAC pixel mask reg
76 #define DAC_ADDRESS_READ_PORT 0x0017 // DAC register read index reg,
77  // write-only
78 #define DAC_STATE_PORT 0x0017 // DAC state (read/write),
79  // read-only
80 #define DAC_ADDRESS_WRITE_PORT 0x0018 // DAC register write index reg
81 #define DAC_DATA_REG_PORT 0x0019 // DAC data transfer reg
82 #define FEAT_CTRL_READ_PORT 0x001A // Feature Control read port
83 #define MISC_OUTPUT_REG_READ_PORT 0x001C // Miscellaneous Output reg read
84  // port
85 #define GRAPH_ADDRESS_PORT 0x001E // Graphics Controller Address
86 #define GRAPH_DATA_PORT 0x001F // and Data registers
87 
88 #define CRTC_ADDRESS_PORT_COLOR 0x0024 // CRT Controller Address and
89 #define CRTC_DATA_PORT_COLOR 0x0025 // Data registers in color mode
90 #define FEAT_CTRL_WRITE_PORT_COLOR 0x002A // Feature Control write port
91 #define INPUT_STATUS_1_COLOR 0x002A // Input Status 1 register read
92  // port in color mode
93 // eVb: 3.2 [END]
94 #define ATT_INITIALIZE_PORT_COLOR INPUT_STATUS_1_COLOR
95  // Register to read to reset
96  // Attribute Controller index/data
97  // toggle in color mode
98 
99 //
100 // Offsets in HardwareStateHeader->PortValue[] of save areas for non-indexed
101 // VGA registers.
102 //
103 
104 #define CRTC_ADDRESS_MONO_OFFSET 0x04
105 #define FEAT_CTRL_WRITE_MONO_OFFSET 0x0A
106 #define ATT_ADDRESS_OFFSET 0x10
107 #define MISC_OUTPUT_REG_WRITE_OFFSET 0x12
108 #define VIDEO_SUBSYSTEM_ENABLE_OFFSET 0x13
109 #define SEQ_ADDRESS_OFFSET 0x14
110 #define DAC_PIXEL_MASK_OFFSET 0x16
111 #define DAC_STATE_OFFSET 0x17
112 #define DAC_ADDRESS_WRITE_OFFSET 0x18
113 #define GRAPH_ADDRESS_OFFSET 0x1E
114 #define CRTC_ADDRESS_COLOR_OFFSET 0x24
115 #define FEAT_CTRL_WRITE_COLOR_OFFSET 0x2A
116 
117 //
118 // VGA indexed register indexes.
119 //
120 
121 // CL-GD542x specific registers:
122 //
123 #define IND_CL_EXTS_ENB 0x06 // index in Sequencer to enable exts
124 #define IND_NORD_SCRATCH_PAD 0x09 // index in Seq of Nordic scratch pad
125 #define IND_CL_SCRATCH_PAD 0x0A // index in Seq of 542x scratch pad
126 #define IND_ALP_SCRATCH_PAD 0x15 // index in Seq of Alpine scratch pad
127 #define IND_CL_REV_REG 0x25 // index in CRTC of ID Register
128 #define IND_CL_ID_REG 0x27 // index in CRTC of ID Register
129 //
130 #define IND_CURSOR_START 0x0A // index in CRTC of the Cursor Start
131 #define IND_CURSOR_END 0x0B // and End registers
132 #define IND_CURSOR_HIGH_LOC 0x0E // index in CRTC of the Cursor Location
133 #define IND_CURSOR_LOW_LOC 0x0F // High and Low Registers
134 #define IND_VSYNC_END 0x11 // index in CRTC of the Vertical Sync
135  // End register, which has the bit
136  // that protects/unprotects CRTC
137  // index registers 0-7
138 #define IND_CR2C 0x2C // Nordic LCD Interface Register
139 #define IND_CR2D 0x2D // Nordic LCD Display Control
140 #define IND_SET_RESET_ENABLE 0x01 // index of Set/Reset Enable reg in GC
141 #define IND_DATA_ROTATE 0x03 // index of Data Rotate reg in GC
142 #define IND_READ_MAP 0x04 // index of Read Map reg in Graph Ctlr
143 #define IND_GRAPH_MODE 0x05 // index of Mode reg in Graph Ctlr
144 #define IND_GRAPH_MISC 0x06 // index of Misc reg in Graph Ctlr
145 #define IND_BIT_MASK 0x08 // index of Bit Mask reg in Graph Ctlr
146 #define IND_SYNC_RESET 0x00 // index of Sync Reset reg in Seq
147 #define IND_MAP_MASK 0x02 // index of Map Mask in Sequencer
148 #define IND_MEMORY_MODE 0x04 // index of Memory Mode reg in Seq
149 #define IND_CRTC_PROTECT 0x11 // index of reg containing regs 0-7 in
150  // CRTC
151 #define IND_CRTC_COMPAT 0x34 // index of CRTC Compatibility reg
152  // in CRTC
153 #define IND_PERF_TUNING 0x16 // index of performance tuning in Seq
154 #define START_SYNC_RESET_VALUE 0x01 // value for Sync Reset reg to start
155  // synchronous reset
156 #define END_SYNC_RESET_VALUE 0x03 // value for Sync Reset reg to end
157  // synchronous reset
158 
159 //
160 // Value to write to Extensions Control register values extensions.
161 //
162 
163 #define CL64xx_EXTENSION_ENABLE_INDEX 0x0A // GR0A to be exact!
164 #define CL64xx_EXTENSION_ENABLE_VALUE 0xEC
165 #define CL64xx_EXTENSION_DISABLE_VALUE 0xCE
166 #define CL64xx_TRISTATE_CONTROL_REG 0xA1
167 
168 #define CL6340_ENABLE_READBACK_REGISTER 0xE0
169 #define CL6340_ENABLE_READBACK_ALLSEL_VALUE 0xF0
170 #define CL6340_ENABLE_READBACK_OFF_VALUE 0x00
171 #define CL6340_IDENTIFICATION_REGISTER 0xE9
172 //
173 // Values for Attribute Controller Index register to turn video off
174 // and on, by setting bit 5 to 0 (off) or 1 (on).
175 //
176 
177 #define VIDEO_DISABLE 0
178 #define VIDEO_ENABLE 0x20
179 
180 #define INDEX_ENABLE_AUTO_START 0x31
181 
182 // Masks to keep only the significant bits of the Graphics Controller and
183 // Sequencer Address registers. Masking is necessary because some VGAs, such
184 // as S3-based ones, don't return unused bits set to 0, and some SVGAs use
185 // these bits if extensions are enabled.
186 //
187 
188 #define GRAPH_ADDR_MASK 0x0F
189 #define SEQ_ADDR_MASK 0x07
190 
191 //
192 // Mask used to toggle Chain4 bit in the Sequencer's Memory Mode register.
193 //
194 
195 #define CHAIN4_MASK 0x08
196 
197 //
198 // Value written to the Read Map register when identifying the existence of
199 // a VGA in VgaInitialize. This value must be different from the final test
200 // value written to the Bit Mask in that routine.
201 //
202 
203 #define READ_MAP_TEST_SETTING 0x03
204 
205 //
206 // Default text mode setting for various registers, used to restore their
207 // states if VGA detection fails after they've been modified.
208 //
209 
210 #define MEMORY_MODE_TEXT_DEFAULT 0x02
211 #define BIT_MASK_DEFAULT 0xFF
212 #define READ_MAP_DEFAULT 0x00
213 
214 
215 //
216 // Palette-related info.
217 //
218 
219 //
220 // Highest valid DAC color register index.
221 //
222 
223 #define VIDEO_MAX_COLOR_REGISTER 0xFF
224 
225 //
226 // Highest valid palette register index
227 //
228 
229 #define VIDEO_MAX_PALETTE_REGISTER 0x0F
230 
231 //
232 // Driver Specific Attribute Flags
233 //
234 
235 #define CAPS_NO_HOST_XFER 0x00000002 // Do not use host xfers to
236  // the blt engine.
237 #define CAPS_SW_POINTER 0x00000004 // Use software pointer.
238 #define CAPS_TRUE_COLOR 0x00000008 // Set upper color registers.
239 #define CAPS_MM_IO 0x00000010 // Use memory mapped IO.
240 #define CAPS_BLT_SUPPORT 0x00000020 // BLTs are supported
241 #define CAPS_IS_542x 0x00000040 // This is a 542x
242 #define CAPS_IS_5436 0x00000080 // This is a 5436
243 #define CAPS_CURSOR_VERT_EXP 0x00000100 // Flag set if 8x6 panel,
244  // but 6x4 resolution
245 
246 //
247 // Structure used to describe each video mode in ModesVGA[].
248 //
249 
250 typedef struct {
251  USHORT fbType; // color or monochrome, text or graphics, via
252  // VIDEO_MODE_COLOR and VIDEO_MODE_GRAPHICS
253  USHORT numPlanes; // # of video memory planes
254  USHORT bitsPerPlane; // # of bits of color in each plane
255  SHORT col; // # of text columns across screen with default font
256  SHORT row; // # of text rows down screen with default font
257  USHORT hres; // # of pixels across screen
258  USHORT vres; // # of scan lines down screen
259 // eVb: 3.2 [VGA] - Store frequency next to resolution data
260  ULONG Frequency; // Vertical Frequency
261 // eVb: 3.2 [END]
262  USHORT wbytes; // # of bytes from start of one scan line to start of next
263  ULONG sbytes; // total size of addressable display memory in bytes
264 // eVb: 3.3 [VBE] - Add VBE mode and bank flag
267 // eVb: 3.3 [VBE]
268  PUSHORT CmdStream; // pointer to array of register-setting commands to
269  // set up mode
270 // eVb: 3.4 [VBE] - Add fields to track linear addresses/sizes and flags
278 // eVb: 3.4 [END]
280 
281 //
282 // Mode into which to put the VGA before starting a VDM, so it's a plain
283 // vanilla VGA. (This is the mode's index in ModesVGA[], currently standard
284 // 80x25 text mode.)
285 //
286 
287 #define DEFAULT_MODE 0
288 
289 
290 //
291 // Info used by the Validator functions and save/restore code.
292 // Structure used to trap register accesses that must be done atomically.
293 //
294 
295 #define VGA_MAX_VALIDATOR_DATA 100
296 
297 #define VGA_VALIDATOR_UCHAR_ACCESS 1
298 #define VGA_VALIDATOR_USHORT_ACCESS 2
299 #define VGA_VALIDATOR_ULONG_ACCESS 3
300 
301 typedef struct _VGA_VALIDATOR_DATA {
306 
307 //
308 // Number of bytes to save in each plane.
309 //
310 
311 #define VGA_PLANE_SIZE 0x10000
312 
313 //
314 // Number of each type of indexed register in a standard VGA, used by
315 // validator and state save/restore functions.
316 //
317 // Note: VDMs currently only support basic VGAs only.
318 //
319 
320 #define VGA_NUM_SEQUENCER_PORTS 5
321 #define VGA_NUM_CRTC_PORTS 25
322 #define VGA_NUM_GRAPH_CONT_PORTS 9
323 #define VGA_NUM_ATTRIB_CONT_PORTS 21
324 #define VGA_NUM_DAC_ENTRIES 256
325 
326 #define EXT_NUM_GRAPH_CONT_PORTS 0
327 #define EXT_NUM_SEQUENCER_PORTS 0
328 #define EXT_NUM_CRTC_PORTS 0
329 #define EXT_NUM_ATTRIB_CONT_PORTS 0
330 #define EXT_NUM_DAC_ENTRIES 0
331 
332 //
333 // These constants determine the offsets within the
334 // VIDEO_HARDWARE_STATE_HEADER structure that are used to save and
335 // restore the VGA's state.
336 //
337 
338 #define VGA_HARDWARE_STATE_SIZE sizeof(VIDEO_HARDWARE_STATE_HEADER)
339 
340 #define VGA_BASIC_SEQUENCER_OFFSET (VGA_HARDWARE_STATE_SIZE + 0)
341 #define VGA_BASIC_CRTC_OFFSET (VGA_BASIC_SEQUENCER_OFFSET + \
342  VGA_NUM_SEQUENCER_PORTS)
343 #define VGA_BASIC_GRAPH_CONT_OFFSET (VGA_BASIC_CRTC_OFFSET + \
344  VGA_NUM_CRTC_PORTS)
345 #define VGA_BASIC_ATTRIB_CONT_OFFSET (VGA_BASIC_GRAPH_CONT_OFFSET + \
346  VGA_NUM_GRAPH_CONT_PORTS)
347 #define VGA_BASIC_DAC_OFFSET (VGA_BASIC_ATTRIB_CONT_OFFSET + \
348  VGA_NUM_ATTRIB_CONT_PORTS)
349 #define VGA_BASIC_LATCHES_OFFSET (VGA_BASIC_DAC_OFFSET + \
350  (3 * VGA_NUM_DAC_ENTRIES))
351 
352 #define VGA_EXT_SEQUENCER_OFFSET (VGA_BASIC_LATCHES_OFFSET + 4)
353 #define VGA_EXT_CRTC_OFFSET (VGA_EXT_SEQUENCER_OFFSET + \
354  EXT_NUM_SEQUENCER_PORTS)
355 #define VGA_EXT_GRAPH_CONT_OFFSET (VGA_EXT_CRTC_OFFSET + \
356  EXT_NUM_CRTC_PORTS)
357 #define VGA_EXT_ATTRIB_CONT_OFFSET (VGA_EXT_GRAPH_CONT_OFFSET +\
358  EXT_NUM_GRAPH_CONT_PORTS)
359 #define VGA_EXT_DAC_OFFSET (VGA_EXT_ATTRIB_CONT_OFFSET + \
360  EXT_NUM_ATTRIB_CONT_PORTS)
361 
362 #define VGA_VALIDATOR_OFFSET (VGA_EXT_DAC_OFFSET + 4 * EXT_NUM_DAC_ENTRIES)
363 
364 #define VGA_VALIDATOR_AREA_SIZE sizeof (ULONG) + (VGA_MAX_VALIDATOR_DATA * \
365  sizeof (VGA_VALIDATOR_DATA)) + \
366  sizeof (ULONG) + \
367  sizeof (ULONG) + \
368  sizeof (PVIDEO_ACCESS_RANGE)
369 
370 #define VGA_MISC_DATA_AREA_OFFSET VGA_VALIDATOR_OFFSET + VGA_VALIDATOR_AREA_SIZE
371 
372 #define VGA_MISC_DATA_AREA_SIZE 0
373 
374 #define VGA_PLANE_0_OFFSET VGA_MISC_DATA_AREA_OFFSET + VGA_MISC_DATA_AREA_SIZE
375 
376 #define VGA_PLANE_1_OFFSET VGA_PLANE_0_OFFSET + VGA_PLANE_SIZE
377 #define VGA_PLANE_2_OFFSET VGA_PLANE_1_OFFSET + VGA_PLANE_SIZE
378 #define VGA_PLANE_3_OFFSET VGA_PLANE_2_OFFSET + VGA_PLANE_SIZE
379 
380 //
381 // Space needed to store all state data.
382 //
383 
384 #define VGA_TOTAL_STATE_SIZE VGA_PLANE_3_OFFSET + VGA_PLANE_SIZE
385 
386 
387 //
388 // Device extension for the driver object. This data is only used
389 // locally, so this structure can be added to as needed.
390 //
391 
392 typedef struct _HW_DEVICE_EXTENSION {
393 
394  PHYSICAL_ADDRESS PhysicalVideoMemoryBase; // physical memory address and
395  PHYSICAL_ADDRESS PhysicalFrameOffset; // physical memory address and
396  ULONG PhysicalVideoMemoryLength; // length of display memory
397  ULONG PhysicalFrameLength; // length of display memory for
398  // the current mode.
399 
400  PUCHAR IOAddress; // base I/O address of VGA ports
401  PUCHAR VideoMemoryAddress; // base virtual memory address of VGA memory
402  ULONG ModeIndex; // index of current mode in ModesVGA[]
403  PVIDEOMODE CurrentMode; // pointer to VIDEOMODE structure for
404  // current mode
405 
406  VIDEO_CURSOR_POSITION CursorPosition; // current cursor position
407 
408  UCHAR CursorEnable; // whether cursor is enabled or not
409  UCHAR CursorTopScanLine; // Cursor Start register setting (top scan)
410  UCHAR CursorBottomScanLine; // Cursor End register setting (bottom scan)
411 // eVb: 3.5 [VBE] - Add fields for VBE support and XP+ INT10 interface
414 // eVb: 3.5 [END]
416 
417 
418 //
419 // Function prototypes.
420 //
421 
422 //
423 // Entry points for the VGA validator. Used in VgaEmulatorAccessEntries[].
424 //
425 
426 
427 //
428 // Vga init scripts for font loading
429 //
430 
431 extern USHORT EnableA000Data[];
432 extern USHORT DisableA000Color[];
433 
434 //
435 // Mode Information
436 //
437 
438 extern ULONG NumVideoModes;
439 extern VIDEOMODE ModesVGA[];
440 extern PVIDEOMODE VgaModeList;
441 
442 // eVb: 3.5 [VGA] - Add ATI/Mach64 Access Range
443 #define NUM_VGA_ACCESS_RANGES 5
444 // eVb: 3.5 [END]
446 
447 /* VESA Bios Magic number */
448 #define VESA_MAGIC ('V' + ('E' << 8) + ('S' << 16) + ('A' << 24))
449 
450 #include "vbe.h"
451 
452 #endif /* _VGA_NEW_PCH_ */
ULONG PhysSize
Definition: vga.h:274
ULONG LogicalWidth
Definition: vga.h:275
PUCHAR IOAddress
Definition: vga.h:400
USHORT vres
Definition: vga.h:258
ULONG NumVideoModes
Definition: vgadata.c:433
PUSHORT CmdStream
Definition: vga.h:268
ULONG PhysicalFrameLength
Definition: vga.h:397
ULONG Frequency
Definition: vga.h:260
USHORT numPlanes
Definition: vga.h:253
UCHAR AccessType
Definition: vga.h:303
unsigned char * PUCHAR
Definition: retypes.h:3
ULONG FrameBufferSize
Definition: vga.h:273
ULONG NonVgaMode
Definition: vga.h:276
ULONG FrameBufferBase
Definition: vga.h:272
ULONG PhysicalVideoMemoryLength
Definition: vga.h:396
USHORT hres
Definition: vga.h:257
PHYSICAL_ADDRESS PhysicalVideoMemoryBase
Definition: vga.h:394
ULONG sbytes
Definition: vga.h:263
PVIDEOMODE VgaModeList
Definition: vgadata.c:434
USHORT bitsPerPlane
Definition: vga.h:254
Definition: vga.h:250
struct _VGA_VALIDATOR_DATA VGA_VALIDATOR_DATA
PVIDEOMODE CurrentMode
Definition: vga.h:403
VIDEOMODE ModesVGA[]
Definition: vgadata.c:281
USHORT fbType
Definition: vga.h:251
VIDEO_PORT_INT10_INTERFACE Int10Interface
Definition: vga.h:412
short SHORT
Definition: pedump.c:59
struct _HW_DEVICE_EXTENSION * PHW_DEVICE_EXTENSION
ULONG Mode
Definition: vga.h:266
unsigned char BOOLEAN
ULONG PhysBase
Definition: vga.h:271
UCHAR CursorBottomScanLine
Definition: vga.h:410
ULONG ModeIndex
Definition: vga.h:402
USHORT wbytes
Definition: vga.h:262
UCHAR CursorTopScanLine
Definition: vga.h:409
SHORT row
Definition: vga.h:256
USHORT EnableA000Data[]
Definition: vgadata.c:447
ULONG Granularity
Definition: vga.h:277
VIDEO_CURSOR_POSITION CursorPosition
Definition: vga.h:406
struct _HW_DEVICE_EXTENSION HW_DEVICE_EXTENSION
unsigned char UCHAR
Definition: xmlstorage.h:181
BOOLEAN VesaBiosOk
Definition: vga.h:413
USHORT DisableA000Color[]
Definition: vgadata.c:473
struct _VGA_VALIDATOR_DATA * PVGA_VALIDATOR_DATA
VIDEO_ACCESS_RANGE VgaAccessRange[]
Definition: vgadata.c:16
SHORT col
Definition: vga.h:255
PUCHAR VideoMemoryAddress
Definition: vga.h:401
unsigned short USHORT
Definition: pedump.c:61
PHYSICAL_ADDRESS PhysicalFrameOffset
Definition: vga.h:395
unsigned int ULONG
Definition: retypes.h:1
ULONG NoBankSwitch
Definition: vga.h:265
struct VIDEOMODE * PVIDEOMODE
unsigned short * PUSHORT
Definition: retypes.h:2
UCHAR CursorEnable
Definition: vga.h:408