25 #define MEM_VGA 0xA0000 26 #define MEM_VGA_SIZE 0x20000 32 #define MEMORY_MAPPED_IO_OFFSET (0xB8000 - 0xA0000) 42 #define VGA_BASE_IO_PORT 0x000003B0 43 #define VGA_START_BREAK_PORT 0x000003BB 44 #define VGA_END_BREAK_PORT 0x000003C0 45 #define VGA_MAX_IO_PORT 0x000003DF 51 #define CRTC_ADDRESS_PORT_MONO 0x0004 // CRT Controller Address and 52 #define CRTC_DATA_PORT_MONO 0x0005 // Data registers in mono mode 53 #define FEAT_CTRL_WRITE_PORT_MONO 0x000A // Feature Control write port 55 #define INPUT_STATUS_1_MONO 0x000A // Input Status 1 register read 57 #define ATT_INITIALIZE_PORT_MONO INPUT_STATUS_1_MONO 61 #define ATT_ADDRESS_PORT 0x0010 // Attribute Controller Address and 62 #define ATT_DATA_WRITE_PORT 0x0010 // Data registers share one port 65 #define ATT_DATA_READ_PORT 0x0011 // Attribute Controller Data reg is 67 #define MISC_OUTPUT_REG_WRITE_PORT 0x0012 // Miscellaneous Output reg write 69 #define INPUT_STATUS_0_PORT 0x0012 // Input Status 0 register read 71 #define VIDEO_SUBSYSTEM_ENABLE_PORT 0x0013 // Bit 0 enables/disables the 73 #define SEQ_ADDRESS_PORT 0x0014 // Sequence Controller Address and 74 #define SEQ_DATA_PORT 0x0015 // Data registers 75 #define DAC_PIXEL_MASK_PORT 0x0016 // DAC pixel mask reg 76 #define DAC_ADDRESS_READ_PORT 0x0017 // DAC register read index reg, 78 #define DAC_STATE_PORT 0x0017 // DAC state (read/write), 80 #define DAC_ADDRESS_WRITE_PORT 0x0018 // DAC register write index reg 81 #define DAC_DATA_REG_PORT 0x0019 // DAC data transfer reg 82 #define FEAT_CTRL_READ_PORT 0x001A // Feature Control read port 83 #define MISC_OUTPUT_REG_READ_PORT 0x001C // Miscellaneous Output reg read 85 #define GRAPH_ADDRESS_PORT 0x001E // Graphics Controller Address 86 #define GRAPH_DATA_PORT 0x001F // and Data registers 88 #define CRTC_ADDRESS_PORT_COLOR 0x0024 // CRT Controller Address and 89 #define CRTC_DATA_PORT_COLOR 0x0025 // Data registers in color mode 90 #define FEAT_CTRL_WRITE_PORT_COLOR 0x002A // Feature Control write port 91 #define INPUT_STATUS_1_COLOR 0x002A // Input Status 1 register read 94 #define ATT_INITIALIZE_PORT_COLOR INPUT_STATUS_1_COLOR 104 #define CRTC_ADDRESS_MONO_OFFSET 0x04 105 #define FEAT_CTRL_WRITE_MONO_OFFSET 0x0A 106 #define ATT_ADDRESS_OFFSET 0x10 107 #define MISC_OUTPUT_REG_WRITE_OFFSET 0x12 108 #define VIDEO_SUBSYSTEM_ENABLE_OFFSET 0x13 109 #define SEQ_ADDRESS_OFFSET 0x14 110 #define DAC_PIXEL_MASK_OFFSET 0x16 111 #define DAC_STATE_OFFSET 0x17 112 #define DAC_ADDRESS_WRITE_OFFSET 0x18 113 #define GRAPH_ADDRESS_OFFSET 0x1E 114 #define CRTC_ADDRESS_COLOR_OFFSET 0x24 115 #define FEAT_CTRL_WRITE_COLOR_OFFSET 0x2A 123 #define IND_CL_EXTS_ENB 0x06 // index in Sequencer to enable exts 124 #define IND_NORD_SCRATCH_PAD 0x09 // index in Seq of Nordic scratch pad 125 #define IND_CL_SCRATCH_PAD 0x0A // index in Seq of 542x scratch pad 126 #define IND_ALP_SCRATCH_PAD 0x15 // index in Seq of Alpine scratch pad 127 #define IND_CL_REV_REG 0x25 // index in CRTC of ID Register 128 #define IND_CL_ID_REG 0x27 // index in CRTC of ID Register 130 #define IND_CURSOR_START 0x0A // index in CRTC of the Cursor Start 131 #define IND_CURSOR_END 0x0B // and End registers 132 #define IND_CURSOR_HIGH_LOC 0x0E // index in CRTC of the Cursor Location 133 #define IND_CURSOR_LOW_LOC 0x0F // High and Low Registers 134 #define IND_VSYNC_END 0x11 // index in CRTC of the Vertical Sync 138 #define IND_CR2C 0x2C // Nordic LCD Interface Register 139 #define IND_CR2D 0x2D // Nordic LCD Display Control 140 #define IND_SET_RESET_ENABLE 0x01 // index of Set/Reset Enable reg in GC 141 #define IND_DATA_ROTATE 0x03 // index of Data Rotate reg in GC 142 #define IND_READ_MAP 0x04 // index of Read Map reg in Graph Ctlr 143 #define IND_GRAPH_MODE 0x05 // index of Mode reg in Graph Ctlr 144 #define IND_GRAPH_MISC 0x06 // index of Misc reg in Graph Ctlr 145 #define IND_BIT_MASK 0x08 // index of Bit Mask reg in Graph Ctlr 146 #define IND_SYNC_RESET 0x00 // index of Sync Reset reg in Seq 147 #define IND_MAP_MASK 0x02 // index of Map Mask in Sequencer 148 #define IND_MEMORY_MODE 0x04 // index of Memory Mode reg in Seq 149 #define IND_CRTC_PROTECT 0x11 // index of reg containing regs 0-7 in 151 #define IND_CRTC_COMPAT 0x34 // index of CRTC Compatibility reg 153 #define IND_PERF_TUNING 0x16 // index of performance tuning in Seq 154 #define START_SYNC_RESET_VALUE 0x01 // value for Sync Reset reg to start 156 #define END_SYNC_RESET_VALUE 0x03 // value for Sync Reset reg to end 163 #define CL64xx_EXTENSION_ENABLE_INDEX 0x0A // GR0A to be exact! 164 #define CL64xx_EXTENSION_ENABLE_VALUE 0xEC 165 #define CL64xx_EXTENSION_DISABLE_VALUE 0xCE 166 #define CL64xx_TRISTATE_CONTROL_REG 0xA1 168 #define CL6340_ENABLE_READBACK_REGISTER 0xE0 169 #define CL6340_ENABLE_READBACK_ALLSEL_VALUE 0xF0 170 #define CL6340_ENABLE_READBACK_OFF_VALUE 0x00 171 #define CL6340_IDENTIFICATION_REGISTER 0xE9 177 #define VIDEO_DISABLE 0 178 #define VIDEO_ENABLE 0x20 180 #define INDEX_ENABLE_AUTO_START 0x31 188 #define GRAPH_ADDR_MASK 0x0F 189 #define SEQ_ADDR_MASK 0x07 195 #define CHAIN4_MASK 0x08 203 #define READ_MAP_TEST_SETTING 0x03 210 #define MEMORY_MODE_TEXT_DEFAULT 0x02 211 #define BIT_MASK_DEFAULT 0xFF 212 #define READ_MAP_DEFAULT 0x00 223 #define VIDEO_MAX_COLOR_REGISTER 0xFF 229 #define VIDEO_MAX_PALETTE_REGISTER 0x0F 235 #define CAPS_NO_HOST_XFER 0x00000002 // Do not use host xfers to 237 #define CAPS_SW_POINTER 0x00000004 // Use software pointer. 238 #define CAPS_TRUE_COLOR 0x00000008 // Set upper color registers. 239 #define CAPS_MM_IO 0x00000010 // Use memory mapped IO. 240 #define CAPS_BLT_SUPPORT 0x00000020 // BLTs are supported 241 #define CAPS_IS_542x 0x00000040 // This is a 542x 242 #define CAPS_IS_5436 0x00000080 // This is a 5436 243 #define CAPS_CURSOR_VERT_EXP 0x00000100 // Flag set if 8x6 panel, 287 #define DEFAULT_MODE 0 295 #define VGA_MAX_VALIDATOR_DATA 100 297 #define VGA_VALIDATOR_UCHAR_ACCESS 1 298 #define VGA_VALIDATOR_USHORT_ACCESS 2 299 #define VGA_VALIDATOR_ULONG_ACCESS 3 311 #define VGA_PLANE_SIZE 0x10000 320 #define VGA_NUM_SEQUENCER_PORTS 5 321 #define VGA_NUM_CRTC_PORTS 25 322 #define VGA_NUM_GRAPH_CONT_PORTS 9 323 #define VGA_NUM_ATTRIB_CONT_PORTS 21 324 #define VGA_NUM_DAC_ENTRIES 256 326 #define EXT_NUM_GRAPH_CONT_PORTS 0 327 #define EXT_NUM_SEQUENCER_PORTS 0 328 #define EXT_NUM_CRTC_PORTS 0 329 #define EXT_NUM_ATTRIB_CONT_PORTS 0 330 #define EXT_NUM_DAC_ENTRIES 0 338 #define VGA_HARDWARE_STATE_SIZE sizeof(VIDEO_HARDWARE_STATE_HEADER) 340 #define VGA_BASIC_SEQUENCER_OFFSET (VGA_HARDWARE_STATE_SIZE + 0) 341 #define VGA_BASIC_CRTC_OFFSET (VGA_BASIC_SEQUENCER_OFFSET + \ 342 VGA_NUM_SEQUENCER_PORTS) 343 #define VGA_BASIC_GRAPH_CONT_OFFSET (VGA_BASIC_CRTC_OFFSET + \ 345 #define VGA_BASIC_ATTRIB_CONT_OFFSET (VGA_BASIC_GRAPH_CONT_OFFSET + \ 346 VGA_NUM_GRAPH_CONT_PORTS) 347 #define VGA_BASIC_DAC_OFFSET (VGA_BASIC_ATTRIB_CONT_OFFSET + \ 348 VGA_NUM_ATTRIB_CONT_PORTS) 349 #define VGA_BASIC_LATCHES_OFFSET (VGA_BASIC_DAC_OFFSET + \ 350 (3 * VGA_NUM_DAC_ENTRIES)) 352 #define VGA_EXT_SEQUENCER_OFFSET (VGA_BASIC_LATCHES_OFFSET + 4) 353 #define VGA_EXT_CRTC_OFFSET (VGA_EXT_SEQUENCER_OFFSET + \ 354 EXT_NUM_SEQUENCER_PORTS) 355 #define VGA_EXT_GRAPH_CONT_OFFSET (VGA_EXT_CRTC_OFFSET + \ 357 #define VGA_EXT_ATTRIB_CONT_OFFSET (VGA_EXT_GRAPH_CONT_OFFSET +\ 358 EXT_NUM_GRAPH_CONT_PORTS) 359 #define VGA_EXT_DAC_OFFSET (VGA_EXT_ATTRIB_CONT_OFFSET + \ 360 EXT_NUM_ATTRIB_CONT_PORTS) 362 #define VGA_VALIDATOR_OFFSET (VGA_EXT_DAC_OFFSET + 4 * EXT_NUM_DAC_ENTRIES) 364 #define VGA_VALIDATOR_AREA_SIZE sizeof (ULONG) + (VGA_MAX_VALIDATOR_DATA * \ 365 sizeof (VGA_VALIDATOR_DATA)) + \ 368 sizeof (PVIDEO_ACCESS_RANGE) 370 #define VGA_MISC_DATA_AREA_OFFSET VGA_VALIDATOR_OFFSET + VGA_VALIDATOR_AREA_SIZE 372 #define VGA_MISC_DATA_AREA_SIZE 0 374 #define VGA_PLANE_0_OFFSET VGA_MISC_DATA_AREA_OFFSET + VGA_MISC_DATA_AREA_SIZE 376 #define VGA_PLANE_1_OFFSET VGA_PLANE_0_OFFSET + VGA_PLANE_SIZE 377 #define VGA_PLANE_2_OFFSET VGA_PLANE_1_OFFSET + VGA_PLANE_SIZE 378 #define VGA_PLANE_3_OFFSET VGA_PLANE_2_OFFSET + VGA_PLANE_SIZE 384 #define VGA_TOTAL_STATE_SIZE VGA_PLANE_3_OFFSET + VGA_PLANE_SIZE 443 #define NUM_VGA_ACCESS_RANGES 5 448 #define VESA_MAGIC ('V' + ('E' << 8) + ('S' << 16) + ('A' << 24))
ULONG PhysicalFrameLength
ULONG PhysicalVideoMemoryLength
PHYSICAL_ADDRESS PhysicalVideoMemoryBase
struct _VGA_VALIDATOR_DATA VGA_VALIDATOR_DATA
VIDEO_PORT_INT10_INTERFACE Int10Interface
struct _HW_DEVICE_EXTENSION * PHW_DEVICE_EXTENSION
UCHAR CursorBottomScanLine
VIDEO_CURSOR_POSITION CursorPosition
struct _HW_DEVICE_EXTENSION HW_DEVICE_EXTENSION
USHORT DisableA000Color[]
struct _VGA_VALIDATOR_DATA * PVGA_VALIDATOR_DATA
VIDEO_ACCESS_RANGE VgaAccessRange[]
PUCHAR VideoMemoryAddress
PHYSICAL_ADDRESS PhysicalFrameOffset
struct _VIDEOMODE VIDEOMODE
struct VIDEOMODE * PVIDEOMODE