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ReactOS Development > Doxygenid_sata.h
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00001 /*++ 00002 00003 Copyright (c) 2008-2011 Alexandr A. Telyatnikov (Alter) 00004 00005 Module Name: 00006 id_probe.cpp 00007 00008 Abstract: 00009 This module handles SATA-related staff 00010 00011 Author: 00012 Alexander A. Telyatnikov (Alter) 00013 00014 Environment: 00015 kernel mode only 00016 00017 Notes: 00018 00019 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 00020 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 00021 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 00022 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 00023 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 00024 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 00025 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 00026 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00027 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 00028 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00029 00030 Revision History: 00031 00032 --*/ 00033 00034 #ifndef __UNIATA_SATA__H__ 00035 #define __UNIATA_SATA__H__ 00036 00037 UCHAR 00038 NTAPI 00039 UniataSataConnect( 00040 IN PVOID HwDeviceExtension, 00041 IN ULONG lChannel, // logical channel 00042 IN ULONG pm_port = 0 /* for port multipliers */ 00043 ); 00044 00045 #define UNIATA_SATA_RESET_ENABLE TRUE 00046 #define UNIATA_SATA_FAST_ENABLE FALSE 00047 00048 UCHAR 00049 NTAPI 00050 UniataSataPhyEnable( 00051 IN PVOID HwDeviceExtension, 00052 IN ULONG lChannel, // logical channel 00053 IN ULONG pm_port = 0, /* for port multipliers */ 00054 IN BOOLEAN doReset = UNIATA_SATA_FAST_ENABLE 00055 ); 00056 00057 #define UNIATA_SATA_DO_CONNECT TRUE 00058 #define UNIATA_SATA_IGNORE_CONNECT FALSE 00059 00060 BOOLEAN 00061 NTAPI 00062 UniataSataClearErr( 00063 IN PVOID HwDeviceExtension, 00064 IN ULONG lChannel, // logical channel 00065 IN BOOLEAN do_connect, 00066 IN ULONG pm_port = 0 /* for port multipliers */ 00067 ); 00068 00069 #define UNIATA_SATA_EVENT_ATTACH 0x01 00070 #define UNIATA_SATA_EVENT_DETACH 0x02 00071 00072 BOOLEAN 00073 NTAPI 00074 UniataSataEvent( 00075 IN PVOID HwDeviceExtension, 00076 IN ULONG lChannel, // logical channel 00077 IN ULONG Action, 00078 IN ULONG pm_port = 0 /* for port multipliers */ 00079 ); 00080 /* 00081 #define UniataIsSATARangeAvailable(deviceExtension, lChannel) \ 00082 ((deviceExtension->BaseIoAddressSATA_0.Addr || \ 00083 deviceExtension->BaseIoAHCI_0.Addr) && \ 00084 (deviceExtension->chan[lChannel].RegTranslation[IDX_SATA_SStatus].Addr)) 00085 */ 00086 __inline 00087 BOOLEAN 00088 UniataIsSATARangeAvailable( 00089 IN PHW_DEVICE_EXTENSION deviceExtension, 00090 IN ULONG lChannel 00091 ) 00092 { 00093 // seems, check for deviceExtension->BaseIoAddressSATA_0.Addr and 00094 // deviceExtension->BaseIoAHCI_0.Addr is not necessary now 00095 if(deviceExtension->chan[lChannel].RegTranslation[IDX_SATA_SStatus].Addr || 00096 deviceExtension->chan[lChannel].RegTranslation[IDX_SATA_SStatus].Proc) { 00097 return TRUE; 00098 } 00099 return FALSE; 00100 } // end UniataIsSATARangeAvailable() 00101 00102 00103 ULONG 00104 NTAPI 00105 UniataSataReadPort4( 00106 IN PHW_CHANNEL chan, 00107 IN ULONG io_port_ndx, 00108 IN ULONG pm_port=0 /* for port multipliers */ 00109 ); 00110 00111 VOID 00112 NTAPI 00113 UniataSataWritePort4( 00114 IN PHW_CHANNEL chan, 00115 IN ULONG io_port_ndx, 00116 IN ULONG data, 00117 IN ULONG pm_port=0 /* for port multipliers */ 00118 ); 00119 00120 BOOLEAN 00121 NTAPI 00122 UniataAhciInit( 00123 IN PVOID HwDeviceExtension 00124 ); 00125 00126 BOOLEAN 00127 NTAPI 00128 UniataAhciDetect( 00129 IN PVOID HwDeviceExtension, 00130 IN PPCI_COMMON_CONFIG pciData, // optional 00131 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo 00132 ); 00133 00134 UCHAR 00135 NTAPI 00136 UniataAhciStatus( 00137 IN PVOID HwDeviceExtension, 00138 IN ULONG lChannel, 00139 IN ULONG DeviceNumber 00140 ); 00141 00142 ULONG 00143 NTAPI 00144 UniataAhciSetupFIS_H2D( 00145 IN PHW_DEVICE_EXTENSION deviceExtension, 00146 IN ULONG DeviceNumber, 00147 IN ULONG lChannel, 00148 OUT PUCHAR fis, 00149 IN UCHAR command, 00150 IN ULONGLONG lba, 00151 IN USHORT count, 00152 IN USHORT feature, 00153 IN ULONG flags 00154 ); 00155 00156 UCHAR 00157 NTAPI 00158 UniataAhciSendCommand( 00159 IN PVOID HwDeviceExtension, 00160 IN ULONG lChannel, 00161 IN ULONG DeviceNumber, 00162 IN ULONG flags, 00163 IN ULONG timeout 00164 ); 00165 00166 ULONG 00167 NTAPI 00168 UniataAhciSoftReset( 00169 IN PVOID HwDeviceExtension, 00170 IN ULONG lChannel, 00171 IN ULONG DeviceNumber 00172 ); 00173 00174 ULONG 00175 NTAPI 00176 UniataAhciWaitReady( 00177 IN PHW_CHANNEL chan, 00178 IN ULONG timeout 00179 ); 00180 00181 ULONG 00182 NTAPI 00183 UniataAhciHardReset( 00184 IN PVOID HwDeviceExtension, 00185 IN ULONG lChannel, 00186 OUT PULONG signature 00187 ); 00188 00189 VOID 00190 NTAPI 00191 UniataAhciReset( 00192 IN PVOID HwDeviceExtension, 00193 IN ULONG lChannel 00194 ); 00195 00196 VOID 00197 NTAPI 00198 UniataAhciStartFR( 00199 IN PHW_CHANNEL chan 00200 ); 00201 00202 VOID 00203 NTAPI 00204 UniataAhciStopFR( 00205 IN PHW_CHANNEL chan 00206 ); 00207 00208 VOID 00209 NTAPI 00210 UniataAhciStart( 00211 IN PHW_CHANNEL chan 00212 ); 00213 00214 VOID 00215 NTAPI 00216 UniataAhciCLO( 00217 IN PHW_CHANNEL chan 00218 ); 00219 00220 VOID 00221 NTAPI 00222 UniataAhciStop( 00223 IN PHW_CHANNEL chan 00224 ); 00225 00226 00227 __inline 00228 ULONG 00229 UniataAhciReadChannelPort4( 00230 IN PHW_CHANNEL chan, 00231 IN ULONG io_port_ndx 00232 ) 00233 { 00234 ULONG v = AtapiReadPortEx4(NULL, (ULONGIO_PTR)&((chan)->BaseIoAHCI_Port), io_port_ndx); 00235 KdPrint3((PRINT_PREFIX "ReadChannelPort4 ch%d[%x] = %x\n", chan->lChannel, io_port_ndx, v)); 00236 return v; 00237 } // end UniataAhciReadChannelPort4() 00238 00239 __inline 00240 VOID 00241 UniataAhciWriteChannelPort4( 00242 IN PHW_CHANNEL chan, 00243 IN ULONG io_port_ndx, 00244 IN ULONG data 00245 ) 00246 { 00247 KdPrint3((PRINT_PREFIX "WriteChannelPort4 %x => ch%d[%x]\n", data, chan->lChannel, io_port_ndx)); 00248 AtapiWritePortEx4(NULL, (ULONGIO_PTR)&((chan)->BaseIoAHCI_Port), io_port_ndx, data); 00249 } // end UniataAhciWriteChannelPort4() 00250 00251 00252 #define UniataAhciReadHostPort4(deviceExtension, io_port_ndx) \ 00253 AtapiReadPortEx4(NULL, (ULONGIO_PTR)&((deviceExtension)->BaseIoAHCI_0), io_port_ndx) 00254 00255 #define UniataAhciWriteHostPort4(deviceExtension, io_port_ndx, data) \ 00256 AtapiWritePortEx4(NULL, (ULONGIO_PTR)&((deviceExtension)->BaseIoAHCI_0), io_port_ndx, data) 00257 00258 UCHAR 00259 NTAPI 00260 UniataAhciBeginTransaction( 00261 IN PVOID HwDeviceExtension, 00262 IN ULONG lChannel, 00263 IN ULONG DeviceNumber, 00264 IN PSCSI_REQUEST_BLOCK Srb 00265 ); 00266 00267 UCHAR 00268 NTAPI 00269 UniataAhciEndTransaction( 00270 IN PVOID HwDeviceExtension, 00271 IN ULONG lChannel, 00272 IN ULONG DeviceNumber, 00273 IN PSCSI_REQUEST_BLOCK Srb 00274 ); 00275 00276 VOID 00277 NTAPI 00278 UniataAhciResume( 00279 IN PHW_CHANNEL chan 00280 ); 00281 00282 __inline 00283 ULONG 00284 UniataAhciUlongFromRFIS( 00285 PUCHAR RCV_FIS 00286 ) 00287 { 00288 return ( (((ULONG)(RCV_FIS[6])) << 24) | 00289 (((ULONG)(RCV_FIS[5])) << 16) | 00290 (((ULONG)(RCV_FIS[4])) << 8) | 00291 ((ULONG)(RCV_FIS[12])) ); 00292 } 00293 00294 BOOLEAN 00295 NTAPI 00296 UniataAhciReadPM( 00297 IN PHW_CHANNEL chan, 00298 IN ULONG DeviceNumber, 00299 IN ULONG Reg, 00300 OUT PULONG result 00301 ); 00302 00303 UCHAR 00304 NTAPI 00305 UniataAhciWritePM( 00306 IN PHW_CHANNEL chan, 00307 IN ULONG DeviceNumber, 00308 IN ULONG Reg, 00309 IN ULONG value 00310 ); 00311 00312 VOID 00313 UniataAhciSetupCmdPtr( 00314 IN OUT PATA_REQ AtaReq 00315 ); 00316 00317 #endif //__UNIATA_SATA__H__ Generated on Sun May 27 2012 04:28:26 for ReactOS by
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