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00001 /*++ 00002 00003 Copyright (c) 2002-2011 Alexandr A. Telyatnikov (Alter) 00004 00005 Module Name: 00006 atapi.h 00007 00008 Abstract: 00009 This file contains IDE, ATA, ATAPI and SCSI Miniport definitions 00010 and function prototypes. 00011 00012 Author: 00013 Alexander A. Telyatnikov (Alter) 00014 00015 Environment: 00016 kernel mode only 00017 00018 Notes: 00019 00020 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 00021 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 00022 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 00023 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 00024 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 00025 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 00026 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 00027 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00028 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 00029 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00030 00031 Revision History: 00032 00033 Some definitions were taken from standard ATAPI.SYS sources from NT4 DDK by 00034 Mike Glass (MGlass) 00035 00036 Some definitions were taken from FreeBSD 4.3-4.6 ATA driver by 00037 Søren Schmidt, Copyright (c) 1998,1999,2000,2001 00038 00039 Code was changed/updated by 00040 Alter, Copyright (c) 2002-2004 00041 00042 00043 --*/ 00044 #ifndef __GLOBAL_H__ 00045 #define __GLOBAL_H__ 00046 00047 #ifdef __cplusplus 00048 extern "C" { 00049 #endif //__cplusplus 00050 00051 #ifndef USER_MODE 00052 #include "config.h" 00053 #endif //USER_MODE 00054 00055 #include "scsi.h" 00056 #include "stdio.h" 00057 #include "string.h" 00058 00059 #ifdef _DEBUG 00060 00061 00062 #ifndef _DBGNT_ 00063 00064 #ifdef KdPrint 00065 #undef KdPrint 00066 #endif 00067 00068 #ifdef USE_DBGPRINT_LOGGER 00069 #include "inc/PostDbgMesg.h" 00070 #define DbgPrint DbgDump_Printf 00071 #define Connect_DbgPrint() {DbgDump_SetAutoReconnect(TRUE); DbgDump_Reconnect();} 00072 #else // USE_DBGPRINT_LOGGER 00073 #define Connect_DbgPrint() {;} 00074 #endif // USE_DBGPRINT_LOGGER 00075 00076 #ifdef SCSI_PORT_DBG_PRINT 00077 00078 SCSIPORT_API 00079 VOID 00080 __cdecl 00081 ScsiDebugPrint( 00082 ULONG DebugPrintLevel, 00083 PCCHAR DebugMessage, 00084 ... 00085 ); 00086 00087 #define PRINT_PREFIX 0, 00088 00089 #define KdPrint3(_x_) ScsiDebugPrint _x_ {;} 00090 #define KdPrint2(_x_) {ScsiDebugPrint("%x: ", PsGetCurrentThread()) ; ScsiDebugPrint _x_ ; } 00091 #define KdPrint(_x_) ScsiDebugPrint _x_ {;} 00092 00093 #else // SCSI_PORT_DBG_PRINT 00094 00095 #ifndef USE_DBGPRINT_LOGGER 00096 /* 00097 ULONG 00098 _cdecl 00099 DbgPrint( 00100 PCH Format, 00101 ... 00102 ); 00103 */ 00104 #endif // USE_DBGPRINT_LOGGER 00105 00106 #define PRINT_PREFIX 00107 00108 // Note, that using DbgPrint on raised IRQL will crash w2k 00109 // tis will not happen immediately, so we shall see some logs 00110 //#define LOG_ON_RAISED_IRQL_W2K TRUE 00111 //#define LOG_ON_RAISED_IRQL_W2K FALSE 00112 00113 #define KdPrint3(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }} 00114 #define KdPrint2(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }} 00115 #define KdPrint(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }} 00116 /* 00117 #define PRINT_PREFIX_PTR ((PCHAR)&__tmp__kdprint__buff__) 00118 #define PRINT_UPREFIX_PTR ((PWCHAR)&__tmp__kdprint__ubuff__) 00119 #define PRINT_PREFIX PRINT_PREFIX_PTR, 00120 #define KdPrint2(_x_) \ 00121 { \ 00122 WCHAR __tmp__kdprint__ubuff__[256]; \ 00123 CHAR __tmp__kdprint__buff__[256]; \ 00124 UNICODE_STRING __tmp__usrt__buff__; \ 00125 sprintf _x_; \ 00126 swprintf (PRINT_UPREFIX_PTR, L"%hs", PRINT_PREFIX_PTR); \ 00127 __tmp__usrt__buff__.Buffer = PRINT_UPREFIX_PTR; \ 00128 __tmp__usrt__buff__.Length = \ 00129 __tmp__usrt__buff__.MaximumLength = strlen(PRINT_PREFIX_PTR); \ 00130 NtDisplayString(&__tmp__usrt__buff__); \ 00131 }; 00132 #define KdPrint(_x_) DbgPrint _x_ 00133 */ 00134 #endif // SCSI_PORT_DBG_PRINT 00135 00136 //#define AtapiStallExecution(dt) { KdPrint2((" AtapiStallExecution(%d)\n", dt)); ScsiPortStallExecution(dt); } 00137 #define AtapiStallExecution(dt) { ScsiPortStallExecution(dt); } 00138 00139 #endif // _DBGNT_ 00140 00141 #else // _DEBUG 00142 00143 #ifdef KdPrint 00144 #undef KdPrint 00145 #endif 00146 00147 #define PRINT_PREFIX "UniATA: " 00148 00149 //#define KdPrint3(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }} 00150 #define KdPrint3(_x_) {;} 00151 #define KdPrint2(_x_) {;} 00152 #define KdPrint(_x_) {;} 00153 #define Connect_DbgPrint() {;} 00154 00155 #define AtapiStallExecution(dt) ScsiPortStallExecution(dt) 00156 00157 #endif // _DEBUG 00158 00159 // IDE register definition 00160 00161 #pragma pack(push, 1) 00162 00163 typedef union _IDE_REGISTERS_1 { 00164 struct _o { 00165 UCHAR Data; 00166 UCHAR Feature; 00167 UCHAR BlockCount; 00168 UCHAR BlockNumber; 00169 UCHAR CylinderLow; 00170 UCHAR CylinderHigh; 00171 UCHAR DriveSelect; 00172 UCHAR Command; 00173 } o; 00174 00175 struct _i { 00176 UCHAR Data; 00177 UCHAR Error; 00178 UCHAR BlockCount; 00179 UCHAR BlockNumber; 00180 UCHAR CylinderLow; 00181 UCHAR CylinderHigh; 00182 UCHAR DriveSelect; 00183 UCHAR Status; 00184 } i; 00185 00186 } IDE_REGISTERS_1, *PIDE_REGISTERS_1; 00187 00188 #define IDX_IO1 0 00189 #define IDX_IO1_SZ sizeof(IDE_REGISTERS_1) 00190 00191 #define IDX_IO1 0 00192 #define IDX_IO1_SZ sizeof(IDE_REGISTERS_1) 00193 #define IDX_IO1_i_Data (FIELD_OFFSET(IDE_REGISTERS_1, i.Data )+IDX_IO1) 00194 #define IDX_IO1_i_Error (FIELD_OFFSET(IDE_REGISTERS_1, i.Error )+IDX_IO1) 00195 #define IDX_IO1_i_BlockCount (FIELD_OFFSET(IDE_REGISTERS_1, i.BlockCount )+IDX_IO1) 00196 #define IDX_IO1_i_BlockNumber (FIELD_OFFSET(IDE_REGISTERS_1, i.BlockNumber )+IDX_IO1) 00197 #define IDX_IO1_i_CylinderLow (FIELD_OFFSET(IDE_REGISTERS_1, i.CylinderLow )+IDX_IO1) 00198 #define IDX_IO1_i_CylinderHigh (FIELD_OFFSET(IDE_REGISTERS_1, i.CylinderHigh)+IDX_IO1) 00199 #define IDX_IO1_i_DriveSelect (FIELD_OFFSET(IDE_REGISTERS_1, i.DriveSelect )+IDX_IO1) 00200 #define IDX_IO1_i_Status (FIELD_OFFSET(IDE_REGISTERS_1, i.Status )+IDX_IO1) 00201 00202 #define IDX_IO1_o IDX_IO1_SZ 00203 #define IDX_IO1_o_SZ sizeof(IDE_REGISTERS_1) 00204 00205 #define IDX_IO1_o_Data (FIELD_OFFSET(IDE_REGISTERS_1, o.Data )+IDX_IO1_o) 00206 #define IDX_IO1_o_Feature (FIELD_OFFSET(IDE_REGISTERS_1, o.Feature )+IDX_IO1_o) 00207 #define IDX_IO1_o_BlockCount (FIELD_OFFSET(IDE_REGISTERS_1, o.BlockCount )+IDX_IO1_o) 00208 #define IDX_IO1_o_BlockNumber (FIELD_OFFSET(IDE_REGISTERS_1, o.BlockNumber )+IDX_IO1_o) 00209 #define IDX_IO1_o_CylinderLow (FIELD_OFFSET(IDE_REGISTERS_1, o.CylinderLow )+IDX_IO1_o) 00210 #define IDX_IO1_o_CylinderHigh (FIELD_OFFSET(IDE_REGISTERS_1, o.CylinderHigh)+IDX_IO1_o) 00211 #define IDX_IO1_o_DriveSelect (FIELD_OFFSET(IDE_REGISTERS_1, o.DriveSelect )+IDX_IO1_o) 00212 #define IDX_IO1_o_Command (FIELD_OFFSET(IDE_REGISTERS_1, o.Command )+IDX_IO1_o) 00213 00214 typedef struct _IDE_REGISTERS_2 { 00215 UCHAR AltStatus; 00216 UCHAR DriveAddress; 00217 } IDE_REGISTERS_2, *PIDE_REGISTERS_2; 00218 00219 #define IDX_IO2 (IDX_IO1_o+IDX_IO1_o_SZ) 00220 #define IDX_IO2_SZ sizeof(IDE_REGISTERS_2) 00221 00222 #define IDX_IO2_AltStatus (FIELD_OFFSET(IDE_REGISTERS_2, AltStatus )+IDX_IO2) 00223 #define IDX_IO2_DriveAddress (FIELD_OFFSET(IDE_REGISTERS_2, DriveAddress)+IDX_IO2) 00224 00225 #define IDX_IO2_o (IDX_IO2+IDX_IO2_SZ) 00226 #define IDX_IO2_o_SZ sizeof(IDE_REGISTERS_2) 00227 00228 #define IDX_IO2_o_Control (FIELD_OFFSET(IDE_REGISTERS_2, AltStatus )+IDX_IO2_o) 00229 // 00230 // Device Extension Device Flags 00231 // 00232 00233 #define DFLAGS_DEVICE_PRESENT 0x0001 // Indicates that some device is present. 00234 #define DFLAGS_ATAPI_DEVICE 0x0002 // Indicates whether ATAPI commands can be used. 00235 #define DFLAGS_TAPE_DEVICE 0x0004 // Indicates whether this is a tape device. 00236 #define DFLAGS_INT_DRQ 0x0008 // Indicates whether device interrupts as DRQ is set after 00237 // receiving ATAPI Packet Command 00238 #define DFLAGS_REMOVABLE_DRIVE 0x0010 // Indicates that the drive has the 'removable' bit set in 00239 // identify data (offset 128) 00240 #define DFLAGS_MEDIA_STATUS_ENABLED 0x0020 // Media status notification enabled 00241 #define DFLAGS_ATAPI_CHANGER 0x0040 // Indicates atapi 2.5 changer present. 00242 #define DFLAGS_SANYO_ATAPI_CHANGER 0x0080 // Indicates multi-platter device, not conforming to the 2.5 spec. 00243 #define DFLAGS_CHANGER_INITED 0x0100 // Indicates that the init path for changers has already been done. 00244 #define DFLAGS_LBA_ENABLED 0x0200 // Indicates that we should use LBA addressing rather than CHS 00245 #define DFLAGS_DWORDIO_ENABLED 0x0400 // Indicates that we should use 32-bit IO 00246 #define DFLAGS_WCACHE_ENABLED 0x0800 // Indicates that we use write cache 00247 #define DFLAGS_RCACHE_ENABLED 0x1000 // Indicates that we use read cache 00248 #define DFLAGS_ORIG_GEOMETRY 0x2000 // 00249 #define DFLAGS_REINIT_DMA 0x4000 // 00250 #define DFLAGS_HIDDEN 0x8000 // Hidden device, available only with special IOCTLs 00251 // via communication virtual device 00252 //#define DFLAGS_ 0x10000 // 00253 // 00254 // Used to disable 'advanced' features. 00255 // 00256 00257 #define MAX_ERRORS 4 00258 00259 // 00260 // ATAPI command definitions 00261 // 00262 00263 #define ATAPI_MODE_SENSE 0x5A 00264 #define ATAPI_MODE_SELECT 0x55 00265 #define ATAPI_FORMAT_UNIT 0x24 00266 00267 // ATAPI Command Descriptor Block 00268 00269 typedef struct _MODE_SENSE_10 { 00270 UCHAR OperationCode; 00271 UCHAR Reserved1; 00272 UCHAR PageCode : 6; 00273 UCHAR Pc : 2; 00274 UCHAR Reserved2[4]; 00275 UCHAR ParameterListLengthMsb; 00276 UCHAR ParameterListLengthLsb; 00277 UCHAR Reserved3[3]; 00278 } MODE_SENSE_10, *PMODE_SENSE_10; 00279 00280 typedef struct _MODE_SELECT_10 { 00281 UCHAR OperationCode; 00282 UCHAR Reserved1 : 4; 00283 UCHAR PFBit : 1; 00284 UCHAR Reserved2 : 3; 00285 UCHAR Reserved3[5]; 00286 UCHAR ParameterListLengthMsb; 00287 UCHAR ParameterListLengthLsb; 00288 UCHAR Reserved4[3]; 00289 } MODE_SELECT_10, *PMODE_SELECT_10; 00290 00291 typedef struct _MODE_PARAMETER_HEADER_10 { 00292 UCHAR ModeDataLengthMsb; 00293 UCHAR ModeDataLengthLsb; 00294 UCHAR MediumType; 00295 UCHAR Reserved[5]; 00296 }MODE_PARAMETER_HEADER_10, *PMODE_PARAMETER_HEADER_10; 00297 00298 // 00299 // IDE command definitions 00300 // 00301 00302 #define IDE_COMMAND_ATAPI_RESET 0x08 00303 #define IDE_COMMAND_RECALIBRATE 0x10 00304 #define IDE_COMMAND_READ 0x20 00305 #define IDE_COMMAND_READ_NO_RETR 0x21 00306 #define IDE_COMMAND_READ48 0x24 00307 #define IDE_COMMAND_READ_DMA48 0x25 00308 #define IDE_COMMAND_READ_DMA_Q48 0x26 00309 #define IDE_COMMAND_READ_NATIVE_SIZE48 0x27 00310 #define IDE_COMMAND_READ_MUL48 0x29 00311 #define IDE_COMMAND_READ_STREAM_DMA48 0x2A 00312 #define IDE_COMMAND_READ_STREAM48 0x2B 00313 #define IDE_COMMAND_READ_LOG48 0x2f 00314 #define IDE_COMMAND_WRITE 0x30 00315 #define IDE_COMMAND_WRITE_NO_RETR 0x31 00316 #define IDE_COMMAND_WRITE48 0x34 00317 #define IDE_COMMAND_WRITE_DMA48 0x35 00318 #define IDE_COMMAND_WRITE_DMA_Q48 0x36 00319 #define IDE_COMMAND_SET_NATIVE_SIZE48 0x37 00320 #define IDE_COMMAND_WRITE_MUL48 0x39 00321 #define IDE_COMMAND_WRITE_STREAM_DMA48 0x3a 00322 #define IDE_COMMAND_WRITE_STREAM48 0x3b 00323 #define IDE_COMMAND_WRITE_FUA_DMA48 0x3d 00324 #define IDE_COMMAND_WRITE_FUA_DMA_Q48 0x3e 00325 #define IDE_COMMAND_WRITE_LOG48 0x3f 00326 #define IDE_COMMAND_VERIFY 0x40 00327 #define IDE_COMMAND_VERIFY48 0x42 00328 #define IDE_COMMAND_READ_LOG_DMA48 0x47 00329 #define IDE_COMMAND_WRITE_LOG_DMA48 0x57 00330 #define IDE_COMMAND_TRUSTED_RCV 0x5c 00331 #define IDE_COMMAND_TRUSTED_RCV_DMA 0x5d 00332 #define IDE_COMMAND_TRUSTED_SEND 0x5e 00333 #define IDE_COMMAND_TRUSTED_SEND_DMA 0x5f 00334 #define IDE_COMMAND_SEEK 0x70 00335 #define IDE_COMMAND_SET_DRIVE_PARAMETERS 0x91 00336 #define IDE_COMMAND_ATAPI_PACKET 0xA0 00337 #define IDE_COMMAND_ATAPI_IDENTIFY 0xA1 00338 #define IDE_COMMAND_READ_MULTIPLE 0xC4 00339 #define IDE_COMMAND_WRITE_MULTIPLE 0xC5 00340 #define IDE_COMMAND_SET_MULTIPLE 0xC6 00341 #define IDE_COMMAND_READ_DMA_Q 0xC7 00342 #define IDE_COMMAND_READ_DMA 0xC8 00343 #define IDE_COMMAND_WRITE_DMA 0xCA 00344 #define IDE_COMMAND_WRITE_DMA_Q 0xCC 00345 #define IDE_COMMAND_WRITE_MUL_FUA48 0xCE 00346 #define IDE_COMMAND_GET_MEDIA_STATUS 0xDA 00347 #define IDE_COMMAND_DOOR_LOCK 0xDE 00348 #define IDE_COMMAND_DOOR_UNLOCK 0xDF 00349 #define IDE_COMMAND_STANDBY_IMMED 0xE0 // flush and spin down 00350 #define IDE_COMMAND_STANDBY 0xE2 // flush and spin down and enable autopowerdown timer 00351 #define IDE_COMMAND_READ_PM 0xE4 // SATA PM 00352 #define IDE_COMMAND_SLEEP 0xE6 // flush, spin down and deactivate interface 00353 #define IDE_COMMAND_FLUSH_CACHE 0xE7 00354 #define IDE_COMMAND_WRITE_PM 0xE8 // SATA PM 00355 #define IDE_COMMAND_IDENTIFY 0xEC 00356 #define IDE_COMMAND_MEDIA_EJECT 0xED 00357 #define IDE_COMMAND_FLUSH_CACHE48 0xEA 00358 #define IDE_COMMAND_ENABLE_MEDIA_STATUS 0xEF 00359 #define IDE_COMMAND_SET_FEATURES 0xEF /* features command, 00360 IDE_COMMAND_ENABLE_MEDIA_STATUS */ 00361 #define IDE_COMMAND_READ_NATIVE_SIZE 0xF8 00362 #define IDE_COMMAND_SET_NATIVE_SIZE 0xF9 00363 00364 #define SCSIOP_ATA_PASSTHROUGH 0xCC // 00365 00366 // 00367 // IDE status definitions 00368 // 00369 00370 #define IDE_STATUS_SUCCESS 0x00 00371 #define IDE_STATUS_ERROR 0x01 00372 #define IDE_STATUS_INDEX 0x02 00373 #define IDE_STATUS_CORRECTED_ERROR 0x04 00374 #define IDE_STATUS_DRQ 0x08 00375 #define IDE_STATUS_DSC 0x10 00376 //#define IDE_STATUS_DWF 0x10 /* drive write fault */ 00377 #define IDE_STATUS_DMA 0x20 /* DMA ready */ 00378 #define IDE_STATUS_DWF 0x20 /* drive write fault */ 00379 #define IDE_STATUS_DRDY 0x40 00380 #define IDE_STATUS_IDLE 0x50 00381 #define IDE_STATUS_BUSY 0x80 00382 00383 00384 // 00385 // IDE drive select/head definitions 00386 // 00387 00388 #define IDE_DRIVE_SELECT 0xA0 00389 #define IDE_DRIVE_1 0x00 00390 #define IDE_DRIVE_2 0x10 00391 #define IDE_DRIVE_SELECT_1 (IDE_DRIVE_SELECT | IDE_DRIVE_1) 00392 #define IDE_DRIVE_SELECT_2 (IDE_DRIVE_SELECT | IDE_DRIVE_2) 00393 00394 #define IDE_USE_LBA 0x40 00395 00396 // 00397 // IDE drive control definitions 00398 // 00399 00400 #define IDE_DC_DISABLE_INTERRUPTS 0x02 00401 #define IDE_DC_RESET_CONTROLLER 0x04 00402 #define IDE_DC_A_4BIT 0x80 00403 #define IDE_DC_USE_HOB 0x80 // use high-order byte(s) 00404 #define IDE_DC_REENABLE_CONTROLLER 0x00 00405 00406 // IDE error definitions 00407 // 00408 00409 #define IDE_ERROR_ICRC 0x80 00410 #define IDE_ERROR_BAD_BLOCK 0x80 00411 #define IDE_ERROR_DATA_ERROR 0x40 00412 #define IDE_ERROR_MEDIA_CHANGE 0x20 00413 #define IDE_ERROR_ID_NOT_FOUND 0x10 00414 #define IDE_ERROR_MEDIA_CHANGE_REQ 0x08 00415 #define IDE_ERROR_COMMAND_ABORTED 0x04 00416 #define IDE_ERROR_END_OF_MEDIA 0x02 00417 #define IDE_ERROR_NO_MEDIA 0x02 00418 #define IDE_ERROR_ILLEGAL_LENGTH 0x01 00419 00420 // 00421 // ATAPI register definition 00422 // 00423 00424 typedef union _ATAPI_REGISTERS_1 { 00425 struct _o { 00426 UCHAR Data; 00427 UCHAR Feature; 00428 UCHAR Unused0; 00429 UCHAR Unused1; 00430 UCHAR ByteCountLow; 00431 UCHAR ByteCountHigh; 00432 UCHAR DriveSelect; 00433 UCHAR Command; 00434 } o; 00435 00436 struct _i { 00437 UCHAR Data; 00438 UCHAR Error; 00439 UCHAR InterruptReason; 00440 UCHAR Unused1; 00441 UCHAR ByteCountLow; 00442 UCHAR ByteCountHigh; 00443 UCHAR DriveSelect; 00444 UCHAR Status; 00445 } i; 00446 00447 //IDE_REGISTERS_1 ide; 00448 00449 } ATAPI_REGISTERS_1, *PATAPI_REGISTERS_1; 00450 00451 #define IDX_ATAPI_IO1 IDX_IO1 00452 #define IDX_ATAPI_IO1_SZ sizeof(ATAPI_REGISTERS_1) 00453 00454 #define IDX_ATAPI_IO1_i_Data (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Data )+IDX_ATAPI_IO1) 00455 #define IDX_ATAPI_IO1_i_Error (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Error )+IDX_ATAPI_IO1) 00456 #define IDX_ATAPI_IO1_i_InterruptReason (FIELD_OFFSET(ATAPI_REGISTERS_1, i.InterruptReason)+IDX_ATAPI_IO1) 00457 #define IDX_ATAPI_IO1_i_Unused1 (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Unused1 )+IDX_ATAPI_IO1) 00458 #define IDX_ATAPI_IO1_i_ByteCountLow (FIELD_OFFSET(ATAPI_REGISTERS_1, i.ByteCountLow )+IDX_ATAPI_IO1) 00459 #define IDX_ATAPI_IO1_i_ByteCountHigh (FIELD_OFFSET(ATAPI_REGISTERS_1, i.ByteCountHigh )+IDX_ATAPI_IO1) 00460 #define IDX_ATAPI_IO1_i_DriveSelect (FIELD_OFFSET(ATAPI_REGISTERS_1, i.DriveSelect )+IDX_ATAPI_IO1) 00461 #define IDX_ATAPI_IO1_i_Status (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Status )+IDX_ATAPI_IO1) 00462 00463 #define IDX_ATAPI_IO1_o_Data (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Data )+IDX_ATAPI_IO1) 00464 #define IDX_ATAPI_IO1_o_Feature (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Feature )+IDX_ATAPI_IO1) 00465 #define IDX_ATAPI_IO1_o_Unused0 (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Unused0 )+IDX_ATAPI_IO1) 00466 #define IDX_ATAPI_IO1_o_Unused1 (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Unused1 )+IDX_ATAPI_IO1) 00467 #define IDX_ATAPI_IO1_o_ByteCountLow (FIELD_OFFSET(ATAPI_REGISTERS_1, o.ByteCountLow )+IDX_ATAPI_IO1) 00468 #define IDX_ATAPI_IO1_o_ByteCountHigh (FIELD_OFFSET(ATAPI_REGISTERS_1, o.ByteCountHigh)+IDX_ATAPI_IO1) 00469 #define IDX_ATAPI_IO1_o_DriveSelect (FIELD_OFFSET(ATAPI_REGISTERS_1, o.DriveSelect )+IDX_ATAPI_IO1) 00470 #define IDX_ATAPI_IO1_o_Command (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Command )+IDX_ATAPI_IO1) 00471 00472 /* 00473 typedef union _ATAPI_REGISTERS_2 { 00474 struct { 00475 UCHAR AltStatus; 00476 UCHAR DriveAddress; 00477 }; 00478 00479 //IDE_REGISTERS_2 ide; 00480 00481 } ATAPI_REGISTERS_2, *PATAPI_REGISTERS_2; 00482 00483 #define IDX_ATAPI_IO2 IDX_ATAPI_IO2_SZ 00484 #define IDX_ATAPI_IO2_SZ sizeof(ATAPI_REGISTERS_2) 00485 */ 00486 00487 // 00488 // ATAPI interrupt reasons 00489 // 00490 00491 #define ATAPI_IR_COD 0x01 00492 #define ATAPI_IR_IO 0x02 00493 00494 // 00495 // ATA Features 00496 // 00497 00498 #define ATA_F_DMA 0x01 /* enable DMA */ 00499 #define ATA_F_OVL 0x02 /* enable overlap */ 00500 00501 #define ATA_C_F_SETXFER 0x03 /* set transfer mode */ 00502 00503 #define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */ 00504 #define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */ 00505 00506 #define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */ 00507 #define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */ 00508 00509 #define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */ 00510 #define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */ 00511 00512 #define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */ 00513 #define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */ 00514 00515 #define ATA_C_F_ENAB_MEDIASTAT 0x95 /* enable media status */ 00516 #define ATA_C_F_DIS_MEDIASTAT 0x31 /* disable media status */ 00517 00518 // 00519 // ATAPI interrupt reasons 00520 // 00521 00522 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 00523 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 00524 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 00525 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 00526 00527 // IDENTIFY data 00528 // 00529 00530 typedef struct _IDENTIFY_DATA { 00531 UCHAR AtapiCmdSize:2; // 00 00 00532 #define ATAPI_PSIZE_12 0 /* 12 bytes */ 00533 #define ATAPI_PSIZE_16 1 /* 16 bytes */ 00534 UCHAR :3; 00535 UCHAR DrqType:2; // 00 00 00536 #define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */ 00537 #define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */ 00538 #define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */ 00539 UCHAR Removable:1; 00540 00541 UCHAR DeviceType:5; 00542 #define ATAPI_TYPE_DIRECT 0 /* disk/floppy */ 00543 #define ATAPI_TYPE_TAPE 1 /* streaming tape */ 00544 #define ATAPI_TYPE_CDROM 5 /* CD-ROM device */ 00545 #define ATAPI_TYPE_OPTICAL 7 /* optical disk */ 00546 UCHAR :1; 00547 UCHAR CmdProtocol:2; // 00 00 00548 #define ATAPI_PROTO_ATAPI 2 00549 // USHORT GeneralConfiguration; // 00 00 00550 00551 USHORT NumberOfCylinders; // 02 1 00552 USHORT Reserved1; // 04 2 00553 USHORT NumberOfHeads; // 06 3 00554 USHORT UnformattedBytesPerTrack; // 08 4 // Now obsolete 00555 USHORT UnformattedBytesPerSector; // 0A 5 // Now obsolete 00556 USHORT SectorsPerTrack; // 0C 6 00557 00558 USHORT VendorUnique1[3]; // 0E 7-9 00559 UCHAR SerialNumber[20]; // 14 10-19 00560 00561 USHORT BufferType; // 28 20 00562 #define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */ 00563 #define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */ 00564 #define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */ 00565 00566 USHORT BufferSectorSize; // 2A 21 00567 USHORT NumberOfEccBytes; // 2C 22 00568 USHORT FirmwareRevision[4]; // 2E 23-26 00569 USHORT ModelNumber[20]; // 36 27-46 00570 UCHAR MaximumBlockTransfer; // 5E 47 00571 UCHAR VendorUnique2; // 5F 00572 00573 USHORT DoubleWordIo; // 60 48 00574 00575 USHORT Reserved62_0:8; // 62 49 00576 USHORT SupportDma:1; 00577 USHORT SupportLba:1; 00578 USHORT DisableIordy:1; 00579 USHORT SupportIordy:1; 00580 USHORT SoftReset:1; 00581 USHORT StandbyOverlap:1; 00582 USHORT SupportQTag:1; /* supports queuing overlap */ 00583 USHORT SupportIDma:1; /* interleaved DMA supported */ 00584 /* USHORT Capabilities; // 62 49 00585 #define IDENTIFY_CAPABILITIES_SUPPORT_DMA 0x0100 00586 #define IDENTIFY_CAPABILITIES_SUPPORT_LBA 0x0200 00587 #define IDENTIFY_CAPABILITIES_DISABLE_IORDY 0x0400 00588 #define IDENTIFY_CAPABILITIES_SUPPORT_IORDY 0x0800 00589 #define IDENTIFY_CAPABILITIES_SOFT_RESET 0x1000 00590 #define IDENTIFY_CAPABILITIES_STDBY_OVLP 0x2000 00591 #define IDENTIFY_CAPABILITIES_SUPPORT_QTAG 0x4000 00592 #define IDENTIFY_CAPABILITIES_SUPPORT_IDMA 0x8000*/ 00593 00594 USHORT DeviceStandbyMin:1; // 64 50 00595 USHORT Reserved50_1:13; 00596 USHORT DeviceCapability1:1; 00597 USHORT DeviceCapability0:1; 00598 // USHORT Reserved2; 00599 00600 UCHAR Vendor51; // 66 51 00601 UCHAR PioCycleTimingMode; // 67 00602 00603 UCHAR Vendor52; // 68 52 00604 UCHAR DmaCycleTimingMode; // 69 00605 00606 USHORT TranslationFieldsValid:1; // 6A 53 /* 54-58 */ 00607 USHORT PioTimingsValid:1; /* 64-70 */ 00608 USHORT UdmaModesValid:1; /* 88 */ 00609 USHORT Reserved3:13; 00610 00611 USHORT NumberOfCurrentCylinders; // 6C 54 \- 00612 USHORT NumberOfCurrentHeads; // 6E 55 \- 00613 USHORT CurrentSectorsPerTrack; // 70 56 /- obsolete USHORT[5] 00614 ULONG CurrentSectorCapacity; // 72 57-58 /- 00615 00616 USHORT CurrentMultiSector:8; // 59 00617 USHORT CurrentMultiSectorValid:1; 00618 USHORT Reserved59_9:7; 00619 00620 ULONG UserAddressableSectors; // 60-61 00621 00622 USHORT SingleWordDMASupport : 8; // 62 \- obsolete 00623 USHORT SingleWordDMAActive : 8; // /- 00624 00625 USHORT MultiWordDMASupport : 8; // 63 00626 USHORT MultiWordDMAActive : 8; 00627 00628 USHORT AdvancedPIOModes : 8; // 64 00629 USHORT Reserved4 : 8; 00630 00631 #define AdvancedPIOModes_3 1 00632 #define AdvancedPIOModes_4 2 00633 #define AdvancedPIOModes_5 4 // non-standard 00634 00635 USHORT MinimumMWXferCycleTime; // 65 00636 USHORT RecommendedMWXferCycleTime; // 66 00637 USHORT MinimumPIOCycleTime; // 67 00638 USHORT MinimumPIOCycleTimeIORDY; // 68 00639 00640 USHORT Reserved69_70[2]; // 69-70 00641 USHORT ReleaseTimeOverlapped; // 71 00642 USHORT ReleaseTimeServiceCommand; // 72 00643 USHORT Reserved73_74[2]; // 73-74 00644 00645 USHORT QueueLength : 5; // 75 00646 USHORT Reserved75_6 : 11; 00647 00648 USHORT SataCapabilities; // 76 00649 #define ATA_SATA_GEN1 0x0002 00650 #define ATA_SATA_GEN2 0x0004 00651 #define ATA_SATA_GEN3 0x0008 00652 #define ATA_SUPPORT_NCQ 0x0100 00653 #define ATA_SUPPORT_IFPWRMNGTRCV 0x0200 00654 00655 USHORT Reserved77; // 77 00656 00657 USHORT SataSupport; // 78 00658 #define ATA_SUPPORT_NONZERO 0x0002 00659 #define ATA_SUPPORT_AUTOACTIVATE 0x0004 00660 #define ATA_SUPPORT_IFPWRMNGT 0x0008 00661 #define ATA_SUPPORT_INORDERDATA 0x0010 00662 00663 USHORT SataEnable; // 79 00664 USHORT MajorRevision; // 80 00665 USHORT MinorRevision; // 81 00666 00667 struct { 00668 USHORT Smart:1; // 82/85 00669 USHORT Security:1; 00670 USHORT Removable:1; 00671 USHORT PowerMngt:1; 00672 USHORT Packet:1; 00673 USHORT WriteCache:1; 00674 USHORT LookAhead:1; 00675 USHORT ReleaseDRQ:1; 00676 USHORT ServiceDRQ:1; 00677 USHORT Reset:1; 00678 USHORT Protected:1; 00679 USHORT Reserved_82_11:1; 00680 USHORT WriteBuffer:1; 00681 USHORT ReadBuffer:1; 00682 USHORT Nop:1; 00683 USHORT Reserved_82_15:1; 00684 00685 USHORT Microcode:1; // 83/86 00686 USHORT Queued:1; // 00687 USHORT CFA:1; // 00688 USHORT APM:1; // 00689 USHORT Notify:1; // 00690 USHORT Standby:1; // 00691 USHORT Spinup:1; // 00692 USHORT Reserver_83_7:1; 00693 USHORT MaxSecurity:1; // 00694 USHORT AutoAcoustic:1; // 00695 USHORT Address48:1; // 00696 USHORT ConfigOverlay:1; // 00697 USHORT FlushCache:1; // 00698 USHORT FlushCache48:1; // 00699 USHORT SupportOne:1; // 00700 USHORT SupportZero:1; // 00701 00702 USHORT SmartErrorLog:1; // 84/87 00703 USHORT SmartSelfTest:1; 00704 USHORT MediaSerialNo:1; 00705 USHORT MediaCardPass:1; 00706 USHORT Streaming:1; 00707 USHORT Logging:1; 00708 USHORT Reserver_84_6:8; 00709 USHORT ExtendedOne:1; // 00710 USHORT ExtendedZero:1; // 00711 } FeaturesSupport, FeaturesEnabled; 00712 00713 USHORT UltraDMASupport : 8; // 88 00714 USHORT UltraDMAActive : 8; 00715 00716 USHORT EraseTime; // 89 00717 USHORT EnhancedEraseTime; // 90 00718 USHORT CurentAPMLevel; // 91 00719 00720 USHORT MasterPasswdRevision; // 92 00721 00722 USHORT HwResMaster : 8; // 93 00723 USHORT HwResSlave : 5; 00724 USHORT HwResCableId : 1; 00725 USHORT HwResValid : 2; 00726 00727 USHORT CurrentAcoustic : 8; // 94 00728 USHORT VendorAcoustic : 8; 00729 00730 USHORT StreamMinReqSize; // 95 00731 USHORT StreamTransferTime; // 96 00732 USHORT StreamAccessLatency; // 97 00733 ULONG StreamGranularity; // 98-99 00734 00735 ULONGLONG UserAddressableSectors48; // 100-103 00736 00737 USHORT Reserved104[2]; // 104-105 00738 union { 00739 USHORT PhysLogSectorSize; // 106 00740 struct { 00741 USHORT PLSS_Size:4; 00742 USHORT PLSS_Reserved:8; 00743 USHORT PLSS_LargeL:1; // =1 if 117-118 are valid 00744 USHORT PLSS_LargeP:1; 00745 USHORT PLSS_Signature:2; // = 0x01 = 01b 00746 }; 00747 }; 00748 USHORT Reserved107[10]; // 107-116 00749 00750 ULONG LargeSectorSize; // 117-118 00751 00752 USHORT Reserved117[8]; // 119-126 00753 00754 USHORT RemovableStatus; // 127 00755 USHORT SecurityStatus; // 128 00756 00757 USHORT FeaturesSupport4; // 129 00758 USHORT Reserved130[30]; // 130-159 00759 USHORT CfAdvPowerMode; // 160 00760 USHORT Reserved161[14]; // 161-175 00761 USHORT MediaSerial[30]; // 176-205 00762 USHORT Reserved206[49]; // 205-254 00763 USHORT Integrity; // 255 00764 } IDENTIFY_DATA, *PIDENTIFY_DATA; 00765 00766 // 00767 // Identify data without the Reserved4. 00768 // 00769 00770 #define IDENTIFY_DATA2 IDENTIFY_DATA 00771 #define PIDENTIFY_DATA2 PIDENTIFY_DATA 00772 00773 /*typedef struct _IDENTIFY_DATA2 { 00774 UCHAR AtapiCmdSize:2; // 00 00 00775 UCHAR :3; 00776 UCHAR DrqType:2; // 00 00 00777 UCHAR Removable:1; 00778 00779 UCHAR DeviceType:5; 00780 UCHAR :1; 00781 UCHAR CmdProtocol:2; // 00 00 00782 // USHORT GeneralConfiguration; // 00 00783 00784 USHORT NumberOfCylinders; // 02 00785 USHORT Reserved1; // 04 00786 USHORT NumberOfHeads; // 06 00787 USHORT UnformattedBytesPerTrack; // 08 00788 USHORT UnformattedBytesPerSector; // 0A 00789 USHORT SectorsPerTrack; // 0C 00790 USHORT VendorUnique1[3]; // 0E 00791 UCHAR SerialNumber[20]; // 14 00792 USHORT BufferType; // 28 00793 USHORT BufferSectorSize; // 2A 00794 USHORT NumberOfEccBytes; // 2C 00795 USHORT FirmwareRevision[4]; // 2E 00796 USHORT ModelNumber[20]; // 36 00797 UCHAR MaximumBlockTransfer; // 5E 00798 UCHAR VendorUnique2; // 5F 00799 USHORT DoubleWordIo; // 60 00800 USHORT Capabilities; // 62 00801 USHORT Reserved2; // 64 00802 UCHAR VendorUnique3; // 66 00803 UCHAR PioCycleTimingMode; // 67 00804 UCHAR VendorUnique4; // 68 00805 UCHAR DmaCycleTimingMode; // 69 00806 USHORT TranslationFieldsValid:1; // 6A 00807 USHORT Reserved3:15; 00808 USHORT NumberOfCurrentCylinders; // 6C 00809 USHORT NumberOfCurrentHeads; // 6E 00810 USHORT CurrentSectorsPerTrack; // 70 00811 ULONG CurrentSectorCapacity; // 72 00812 } IDENTIFY_DATA2, *PIDENTIFY_DATA2;*/ 00813 00814 #define IDENTIFY_DATA_SIZE sizeof(IDENTIFY_DATA) 00815 00816 // IDENTIFY DMA timing cycle modes. 00817 #define IDENTIFY_DMA_CYCLES_MODE_0 0x00 00818 #define IDENTIFY_DMA_CYCLES_MODE_1 0x01 00819 #define IDENTIFY_DMA_CYCLES_MODE_2 0x02 00820 /* 00821 #define PCI_DEV_HW_SPEC(idhi, idlo) \ 00822 { #idlo, 4, #idhi, 4} 00823 00824 typedef struct _BROKEN_CONTROLLER_INFORMATION { 00825 PCHAR VendorId; 00826 ULONG VendorIdLength; 00827 PCHAR DeviceId; 00828 ULONG DeviceIdLength; 00829 }BROKEN_CONTROLLER_INFORMATION, *PBROKEN_CONTROLLER_INFORMATION; 00830 00831 BROKEN_CONTROLLER_INFORMATION const BrokenAdapters[] = { 00832 // CMD 640 ATA controller !WARNING! buggy chip data loss possible 00833 PCI_DEV_HW_SPEC( 0640, 1095 ), //{ "1095", 4, "0640", 4}, 00834 // ?? 00835 PCI_DEV_HW_SPEC( 0601, 1039 ), //{ "1039", 4, "0601", 4} 00836 // RZ 100? ATA controller !WARNING! buggy chip data loss possible 00837 PCI_DEV_HW_SPEC( 1000, 1042 ), 00838 PCI_DEV_HW_SPEC( 1001, 1042 ) 00839 }; 00840 00841 #define BROKEN_ADAPTERS (sizeof(BrokenAdapters) / sizeof(BROKEN_CONTROLLER_INFORMATION)) 00842 00843 typedef struct _NATIVE_MODE_CONTROLLER_INFORMATION { 00844 PCHAR VendorId; 00845 ULONG VendorIdLength; 00846 PCHAR DeviceId; 00847 ULONG DeviceIdLength; 00848 }NATIVE_MODE_CONTROLLER_INFORMATION, *PNATIVE_MODE_CONTROLLER_INFORMATION; 00849 00850 NATIVE_MODE_CONTROLLER_INFORMATION const NativeModeAdapters[] = { 00851 PCI_DEV_HW_SPEC( 0105, 10ad ) //{ "10ad", 4, "0105", 4} 00852 }; 00853 00854 #define NUM_NATIVE_MODE_ADAPTERS (sizeof(NativeModeAdapters) / sizeof(NATIVE_MODE_CONTROLLER_INFORMATION)) 00855 */ 00856 // 00857 // Beautification macros 00858 // 00859 00860 #ifndef USER_MODE 00861 00862 #define GetStatus(chan, Status) \ 00863 Status = AtapiReadPort1(chan, IDX_IO2_AltStatus); 00864 00865 #define GetBaseStatus(chan, pStatus) \ 00866 pStatus = AtapiReadPort1(chan, IDX_IO1_i_Status); 00867 00868 #define WriteCommand(chan, _Command) \ 00869 AtapiWritePort1(chan, IDX_IO1_o_Command, _Command); 00870 00871 00872 #define SelectDrive(chan, unit) { \ 00873 if(chan && chan->lun[unit] && chan->lun[unit]->DeviceFlags & DFLAGS_ATAPI_CHANGER) KdPrint3((" Select %d\n", unit)); \ 00874 AtapiWritePort1(chan, IDX_IO1_o_DriveSelect, (unit) ? IDE_DRIVE_SELECT_2 : IDE_DRIVE_SELECT_1); \ 00875 } 00876 00877 00878 #define ReadBuffer(chan, Buffer, Count, timing) \ 00879 AtapiReadBuffer2(chan, IDX_IO1_i_Data, \ 00880 Buffer, \ 00881 Count, \ 00882 timing); 00883 00884 #define WriteBuffer(chan, Buffer, Count, timing) \ 00885 AtapiWriteBuffer2(chan, IDX_IO1_o_Data, \ 00886 Buffer, \ 00887 Count, \ 00888 timing); 00889 00890 #define ReadBuffer2(chan, Buffer, Count, timing) \ 00891 AtapiReadBuffer4(chan, IDX_IO1_i_Data, \ 00892 Buffer, \ 00893 Count, \ 00894 timing); 00895 00896 #define WriteBuffer2(chan, Buffer, Count, timing) \ 00897 AtapiWriteBuffer4(chan, IDX_IO1_o_Data, \ 00898 Buffer, \ 00899 Count, \ 00900 timing); 00901 00902 UCHAR 00903 DDKFASTAPI 00904 WaitOnBusy( 00905 IN struct _HW_CHANNEL* chan/*, 00906 PIDE_REGISTERS_2 BaseIoAddress*/ 00907 ); 00908 00909 UCHAR 00910 DDKFASTAPI 00911 WaitOnBusyLong( 00912 IN struct _HW_CHANNEL* chan/*, 00913 PIDE_REGISTERS_2 BaseIoAddress*/ 00914 ); 00915 00916 UCHAR 00917 DDKFASTAPI 00918 WaitOnBaseBusy( 00919 IN struct _HW_CHANNEL* chan/*, 00920 PIDE_REGISTERS_1 BaseIoAddress*/ 00921 ); 00922 00923 UCHAR 00924 DDKFASTAPI 00925 WaitOnBaseBusyLong( 00926 IN struct _HW_CHANNEL* chan/*, 00927 PIDE_REGISTERS_1 BaseIoAddress*/ 00928 ); 00929 00930 UCHAR 00931 DDKFASTAPI 00932 WaitForDrq( 00933 IN struct _HW_CHANNEL* chan/*, 00934 PIDE_REGISTERS_2 BaseIoAddress*/ 00935 ); 00936 00937 UCHAR 00938 DDKFASTAPI 00939 WaitShortForDrq( 00940 IN struct _HW_CHANNEL* chan/*, 00941 PIDE_REGISTERS_2 BaseIoAddress*/ 00942 ); 00943 00944 VOID 00945 DDKFASTAPI 00946 AtapiSoftReset( 00947 IN struct _HW_CHANNEL* chan,/* 00948 PIDE_REGISTERS_1 BaseIoAddress*/ 00949 ULONG DeviceNumber 00950 ); 00951 00952 00953 #endif //USER_MODE 00954 00955 #define IS_RDP(OperationCode)\ 00956 ((OperationCode == SCSIOP_ERASE)||\ 00957 (OperationCode == SCSIOP_LOAD_UNLOAD)||\ 00958 (OperationCode == SCSIOP_LOCATE)||\ 00959 (OperationCode == SCSIOP_REWIND) ||\ 00960 (OperationCode == SCSIOP_SPACE)||\ 00961 (OperationCode == SCSIOP_SEEK)||\ 00962 /* (OperationCode == SCSIOP_FORMAT_UNIT)||\ 00963 (OperationCode == SCSIOP_BLANK)||*/ \ 00964 (OperationCode == SCSIOP_WRITE_FILEMARKS)) 00965 00966 #ifndef USER_MODE 00967 00968 PSCSI_REQUEST_BLOCK 00969 NTAPI 00970 BuildMechanismStatusSrb ( 00971 IN PVOID HwDeviceExtension, 00972 IN PSCSI_REQUEST_BLOCK Srb 00973 ); 00974 00975 PSCSI_REQUEST_BLOCK 00976 NTAPI 00977 BuildRequestSenseSrb ( 00978 IN PVOID HwDeviceExtension, 00979 IN PSCSI_REQUEST_BLOCK Srb 00980 ); 00981 00982 VOID 00983 NTAPI 00984 AtapiHwInitializeChanger ( 00985 IN PVOID HwDeviceExtension, 00986 IN ULONG TargetId, 00987 IN PMECHANICAL_STATUS_INFORMATION_HEADER MechanismStatus 00988 ); 00989 00990 ULONG 00991 NTAPI 00992 AtapiSendCommand( 00993 IN PVOID HwDeviceExtension, 00994 IN PSCSI_REQUEST_BLOCK Srb, 00995 IN ULONG CmdAction 00996 ); 00997 00998 ULONG 00999 NTAPI 01000 IdeSendCommand( 01001 IN PVOID HwDeviceExtension, 01002 IN PSCSI_REQUEST_BLOCK Srb, 01003 IN ULONG CmdAction 01004 ); 01005 01006 #define AtapiCopyMemory RtlCopyMemory 01007 01008 VOID 01009 NTAPI 01010 AtapiHexToString ( 01011 ULONG Value, 01012 PCHAR *Buffer 01013 ); 01014 01015 #define AtapiStringCmp(s1, s2, n) _strnicmp(s1, s2, n) 01016 01017 BOOLEAN 01018 NTAPI 01019 AtapiInterrupt( 01020 IN PVOID HwDeviceExtension 01021 ); 01022 01023 BOOLEAN 01024 NTAPI 01025 AtapiInterrupt__( 01026 IN PVOID HwDeviceExtension, 01027 IN UCHAR c 01028 ); 01029 01030 UCHAR 01031 NTAPI 01032 AtapiCheckInterrupt__( 01033 IN PVOID HwDeviceExtension, 01034 IN UCHAR c 01035 ); 01036 01037 #define INTERRUPT_REASON_IGNORE 0 01038 #define INTERRUPT_REASON_OUR 1 01039 #define INTERRUPT_REASON_UNEXPECTED 2 01040 01041 BOOLEAN 01042 NTAPI 01043 AtapiHwInitialize( 01044 IN PVOID HwDeviceExtension 01045 ); 01046 01047 ULONG 01048 NTAPI 01049 IdeBuildSenseBuffer( 01050 IN PVOID HwDeviceExtension, 01051 IN PSCSI_REQUEST_BLOCK Srb 01052 ); 01053 01054 VOID 01055 NTAPI 01056 IdeMediaStatus( 01057 BOOLEAN EnableMSN, 01058 IN PVOID HwDeviceExtension, 01059 IN ULONG lChannel, 01060 IN ULONG DeviceNumber 01061 ); 01062 01063 ULONG NTAPI 01064 AtapiFindController( 01065 IN PVOID HwDeviceExtension, 01066 IN PVOID Context, 01067 IN PVOID BusInformation, 01068 IN PCHAR ArgumentString, 01069 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, 01070 OUT PBOOLEAN Again 01071 ); 01072 01073 ULONG 01074 NTAPI 01075 AtapiParseArgumentString( 01076 IN PCCH String, 01077 IN PCCH KeyWord 01078 ); 01079 01080 BOOLEAN 01081 NTAPI 01082 IssueIdentify( 01083 IN PVOID HwDeviceExtension, 01084 IN ULONG DeviceNumber, 01085 IN ULONG Channel, 01086 IN UCHAR Command, 01087 IN BOOLEAN NoSetup 01088 ); 01089 01090 BOOLEAN 01091 NTAPI 01092 SetDriveParameters( 01093 IN PVOID HwDeviceExtension, 01094 IN ULONG DeviceNumber, 01095 IN ULONG Channel 01096 ); 01097 01098 ULONG 01099 NTAPI 01100 CheckDevice( 01101 IN PVOID HwDeviceExtension, 01102 IN ULONG Channel, 01103 IN ULONG deviceNumber, 01104 IN BOOLEAN ResetBus 01105 ); 01106 01107 #define UNIATA_FIND_DEV_UNHIDE 0x01 01108 01109 BOOLEAN 01110 NTAPI 01111 FindDevices( 01112 IN PVOID HwDeviceExtension, 01113 IN ULONG Flags, 01114 IN ULONG Channel 01115 ); 01116 01117 #endif //USER_MODE 01118 01119 #ifdef __cplusplus 01120 }; 01121 #endif //__cplusplus 01122 01123 #ifndef USER_MODE 01124 01125 BOOLEAN 01126 NTAPI 01127 AtapiResetController( 01128 IN PVOID HwDeviceExtension, 01129 IN ULONG PathId 01130 ); 01131 01132 BOOLEAN 01133 NTAPI 01134 AtapiStartIo( 01135 IN PVOID HwDeviceExtension, 01136 IN PSCSI_REQUEST_BLOCK Srb 01137 ); 01138 01139 BOOLEAN 01140 NTAPI 01141 AtapiStartIo__( 01142 IN PVOID HwDeviceExtension, 01143 IN PSCSI_REQUEST_BLOCK Srb, 01144 IN BOOLEAN TopLevel 01145 ); 01146 01147 extern UCHAR 01148 NTAPI 01149 AtaCommand48( 01150 // IN PVOID HwDeviceExtension, 01151 IN struct _HW_DEVICE_EXTENSION* deviceExtension, 01152 IN ULONG DeviceNumber, 01153 IN ULONG Channel, 01154 IN UCHAR command, 01155 IN ULONGLONG lba, 01156 IN USHORT count, 01157 IN USHORT feature, 01158 IN ULONG flags 01159 ); 01160 01161 extern UCHAR 01162 NTAPI 01163 AtaCommand( 01164 // IN PVOID HwDeviceExtension, 01165 IN struct _HW_DEVICE_EXTENSION* deviceExtension, 01166 IN ULONG DeviceNumber, 01167 IN ULONG Channel, 01168 IN UCHAR command, 01169 IN USHORT cylinder, 01170 IN UCHAR head, 01171 IN UCHAR sector, 01172 IN UCHAR count, 01173 IN UCHAR feature, 01174 IN ULONG flags 01175 ); 01176 01177 extern LONG 01178 NTAPI 01179 AtaPioMode(PIDENTIFY_DATA2 ident); 01180 01181 extern LONG 01182 NTAPI 01183 AtaWmode(PIDENTIFY_DATA2 ident); 01184 01185 extern LONG 01186 NTAPI 01187 AtaUmode(PIDENTIFY_DATA2 ident); 01188 01189 extern VOID 01190 NTAPI 01191 AtapiDpcDispatch( 01192 IN PKDPC Dpc, 01193 IN PVOID DeferredContext, 01194 IN PVOID SystemArgument1, 01195 IN PVOID SystemArgument2 01196 ); 01197 01198 //#define AtaCommand(de, devn, chan, cmd, cyl, hd, sec, cnt, feat, flg) 01199 01200 extern LONG 01201 NTAPI 01202 AtaPio2Mode(LONG pio); 01203 01204 extern LONG 01205 NTAPI 01206 AtaPioMode(PIDENTIFY_DATA2 ident); 01207 01208 extern VOID 01209 NTAPI 01210 AtapiEnableInterrupts( 01211 IN PVOID HwDeviceExtension, 01212 IN ULONG c 01213 ); 01214 01215 extern VOID 01216 NTAPI 01217 AtapiDisableInterrupts( 01218 IN PVOID HwDeviceExtension, 01219 IN ULONG c 01220 ); 01221 01222 #define CHAN_NOT_SPECIFIED (0xffffffffL) 01223 #define CHAN_NOT_SPECIFIED_CHECK_CABLE (0xfffffffeL) 01224 #define DEVNUM_NOT_SPECIFIED (0xffffffffL) 01225 #define IOMODE_NOT_SPECIFIED (0xffffffffL) 01226 01227 extern ULONG 01228 NTAPI 01229 AtapiRegCheckDevValue( 01230 IN PVOID HwDeviceExtension, 01231 IN ULONG chan, 01232 IN ULONG dev, 01233 IN PCWSTR Name, 01234 IN ULONG Default 01235 ); 01236 01237 extern ULONG 01238 NTAPI 01239 AtapiRegCheckParameterValue( 01240 IN PVOID HwDeviceExtension, 01241 IN PCWSTR PathSuffix, 01242 IN PCWSTR Name, 01243 IN ULONG Default 01244 ); 01245 01246 extern ULONG g_LogToDisplay; 01247 01248 extern "C" 01249 VOID 01250 _cdecl 01251 _PrintNtConsole( 01252 PCCH DebugMessage, 01253 ... 01254 ); 01255 01256 VOID 01257 NTAPI 01258 UniataInitMapBM( 01259 IN struct _HW_DEVICE_EXTENSION* deviceExtension, 01260 IN struct _IDE_BUSMASTER_REGISTERS* BaseIoAddressBM_0, 01261 IN BOOLEAN MemIo 01262 ); 01263 01264 VOID 01265 NTAPI 01266 UniataInitMapBase( 01267 IN struct _HW_CHANNEL* chan, 01268 IN PIDE_REGISTERS_1 BaseIoAddress1, 01269 IN PIDE_REGISTERS_2 BaseIoAddress2 01270 ); 01271 01272 VOID 01273 NTAPI 01274 UniataInitSyncBaseIO( 01275 IN struct _HW_CHANNEL* chan 01276 ); 01277 01278 UCHAR 01279 DDKFASTAPI 01280 UniataIsIdle( 01281 IN struct _HW_DEVICE_EXTENSION* deviceExtension, 01282 IN UCHAR Status 01283 ); 01284 01285 VOID 01286 NTAPI 01287 UniataDumpATARegs( 01288 IN struct _HW_CHANNEL* chan 01289 ); 01290 01291 ULONG 01292 NTAPI 01293 EncodeVendorStr( 01294 OUT PWCHAR Buffer, 01295 IN PUCHAR Str, 01296 IN ULONG Length 01297 ); 01298 01299 ULONGLONG 01300 NTAPI 01301 UniAtaCalculateLBARegsBack( 01302 struct _HW_LU_EXTENSION* LunExt, 01303 ULONGLONG lba 01304 ); 01305 01306 BOOLEAN 01307 NTAPI 01308 UniataAnybodyHome( 01309 IN PVOID HwDeviceExtension, 01310 IN ULONG Channel, 01311 IN ULONG deviceNumber 01312 ); 01313 01314 #define ATA_CMD_FLAG_LBAIOsupp 0x01 01315 #define ATA_CMD_FLAG_48supp 0x02 01316 #define ATA_CMD_FLAG_48 0x04 01317 #define ATA_CMD_FLAG_DMA 0x08 01318 01319 extern UCHAR AtaCommands48[256]; 01320 extern UCHAR AtaCommandFlags[256]; 01321 01322 /* 01323 We need LBA48 when requested LBA or BlockCount are too large. 01324 But for LBA-based commands we have *special* limitation 01325 */ 01326 #define UniAta_need_lba48(command, lba, count, supp48) \ 01327 ( ((AtaCommandFlags[command] & ATA_CMD_FLAG_LBAIOsupp) && (supp48) && (((lba+count) >= ATA_MAX_IOLBA28) || (count > 256)) ) || \ 01328 (lba > ATA_MAX_LBA28) || (count > 255) ) 01329 01330 #ifdef _DEBUG 01331 #define PrintNtConsole _PrintNtConsole 01332 #else //_DEBUG 01333 #define PrintNtConsole(x) {;} 01334 #endif //_DEBUG 01335 01336 #endif //USER_MODE 01337 01338 #pragma pack(pop) 01339 01340 #endif // __GLOBAL_H__
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