ReactOS 0.4.15-dev-8076-g06e89b2
Classes | Macros | Typedefs | Functions | Variables
bsmaster.h File Reference
#include "config.h"
#include "tools.h"
#include "bm_devs_decl.h"
#include "uata_ctl.h"
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Classes

struct  _BUSMASTER_CTX
 
struct  BM_DMA_ENTRY
 
struct  _IDE_BUSMASTER_REGISTERS
 
struct  _IDE_AHCI_REGISTERS
 
union  _SATA_SSTATUS_REG
 
union  _SATA_SCONTROL_REG
 
union  _SATA_SERROR_REG
 
struct  _IDE_SATA_REGISTERS
 
union  _AHCI_IS_REG
 
struct  _IDE_AHCI_PORT_REGISTERS
 
struct  _IDE_AHCI_PRD_ENTRY
 
struct  _AHCI_ATA_H2D_FIS
 
struct  _IDE_AHCI_CMD
 
struct  _IDE_AHCI_CMD_LIST
 
struct  _IDE_AHCI_RCV_FIS
 
struct  _IDE_AHCI_CHANNEL_CTL_BLOCK
 
union  _ATA_REQ
 
struct  _IORES
 
struct  _HW_CHANNEL
 
struct  _HW_LU_EXTENSION
 
struct  _HW_DEVICE_EXTENSION
 
struct  _ISR2_DEVICE_EXTENSION
 

Macros

#define ATA_IDLE   0x0
 
#define ATA_IMMEDIATE   0x1
 
#define ATA_WAIT_INTR   0x2
 
#define ATA_WAIT_READY   0x3
 
#define ATA_ACTIVE   0x4
 
#define ATA_ACTIVE_ATA   0x5
 
#define ATA_ACTIVE_ATAPI   0x6
 
#define ATA_REINITING   0x7
 
#define ATA_WAIT_BASE_READY   0x8
 
#define ATA_WAIT_IDLE   0x9
 
#define MAX_RETRIES   6
 
#define RETRY_UDMA2   1
 
#define RETRY_WDMA   2
 
#define RETRY_PIO   3
 
#define IO_WD1   0x1F0 /* Primary Fixed Disk Controller */
 
#define IO_WD2   0x170 /* Secondary Fixed Disk Controller */
 
#define IP_PC98_BANK   0x432
 
#define IO_FLOPPY_INT   0x3F6 /* AltStatus inside Floppy I/O range */
 
#define PCI_ADDRESS_IOMASK   0xfffffff0
 
#define ATA_BM_OFFSET1   0x08
 
#define ATA_IOSIZE   0x08
 
#define ATA_ALTOFFSET   0x206 /* alternate registers offset */
 
#define ATA_PCCARD_ALTOFFSET   0x0e /* do for PCCARD devices */
 
#define ATA_ALTIOSIZE   0x01 /* alternate registers size */
 
#define ATA_BMIOSIZE   0x20
 
#define ATA_PC98_BANKIOSIZE   0x01
 
#define ATA_MAX_IOLBA28   DEF_U64(0x0fffff80)
 
#define ATA_MAX_LBA28   DEF_U64(0x0fffffff)
 
#define ATA_MAX_IOLBA32   DEF_U64(0xffffff80)
 
#define ATA_MAX_LBA32   DEF_U64(0xffffffff)
 
#define ATA_DMA_ENTRIES   256 /* PAGESIZE/2/sizeof(BM_DMA_ENTRY)*/
 
#define ATA_DMA_EOT   0x80000000
 
#define DEV_BSIZE   512
 
#define ATAPI_MAGIC_LSB   0x14
 
#define ATAPI_MAGIC_MSB   0xeb
 
#define AHCI_MAX_PORT   32
 
#define SATA_MAX_PM_UNITS   16
 
#define PCI_DEV_CLASS_STORAGE   0x01
 
#define PCI_DEV_SUBCLASS_IDE   0x01
 
#define PCI_DEV_SUBCLASS_RAID   0x04
 
#define PCI_DEV_SUBCLASS_ATA   0x05
 
#define PCI_DEV_SUBCLASS_SATA   0x06
 
#define PCI_DEV_PROGIF_AHCI_1_0   0x01
 
#define BM_STATUS_ACTIVE   0x01
 
#define BM_STATUS_ERR   0x02
 
#define BM_STATUS_INTR   0x04
 
#define BM_STATUS_MASK   0x07
 
#define BM_STATUS_DRIVE_0_DMA   0x20
 
#define BM_STATUS_DRIVE_1_DMA   0x40
 
#define BM_STATUS_SIMPLEX_ONLY   0x80
 
#define BM_COMMAND_START_STOP   0x01
 
#define BM_COMMAND_WRITE   0x00
 
#define BM_COMMAND_READ   0x08
 
#define BM_DS0_SII_DMA_ENABLE   (1 << 0) /* DMA run switch */
 
#define BM_DS0_SII_IRQ   (1 << 3) /* ??? */
 
#define BM_DS0_SII_DMA_SATA_IRQ   (1 << 4) /* OR of all SATA IRQs */
 
#define BM_DS0_SII_DMA_ERROR   (1 << 17) /* PCI bus error */
 
#define BM_DS0_SII_DMA_COMPLETE   (1 << 18) /* cmd complete / IRQ pending */
 
#define IDX_BM_IO   (IDX_IO2_o+IDX_IO2_o_SZ)
 
#define IDX_BM_IO_SZ   5
 
#define IDX_BM_Command   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Command )+IDX_BM_IO)
 
#define IDX_BM_DeviceSpecific0   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific0)+IDX_BM_IO)
 
#define IDX_BM_Status   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Status )+IDX_BM_IO)
 
#define IDX_BM_DeviceSpecific1   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific1)+IDX_BM_IO)
 
#define IDX_BM_PRD_Table   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, PRD_Table )+IDX_BM_IO)
 
#define AHCI_CAP_NOP_MASK   0x0000001f
 
#define AHCI_CAP_CCC   0x00000080
 
#define AHCI_CAP_NCS_MASK   0x00001f00
 
#define AHCI_CAP_PMD   0x00008000
 
#define AHCI_CAP_SPM   0x00020000
 
#define AHCI_CAP_SAM   0x00040000
 
#define AHCI_CAP_ISS_MASK   0x00f00000
 
#define AHCI_CAP_SCLO   0x01000000
 
#define AHCI_CAP_SNTF   0x20000000
 
#define AHCI_CAP_NCQ   0x40000000
 
#define AHCI_CAP_S64A   0x80000000
 
#define AHCI_GHC   0x04
 
#define AHCI_GHC_HR   0x00000001
 
#define AHCI_GHC_IE   0x00000002
 
#define AHCI_GHC_AE   0x80000000
 
#define AHCI_CAP2_BOH   0x00000001
 
#define AHCI_CAP2_NVMP   0x00000002
 
#define AHCI_CAP2_APST   0x00000004
 
#define AHCI_BOHC_BB   0x00000001
 
#define AHCI_BOHC_OOC   0x00000002
 
#define AHCI_BOHC_SOOE   0x00000004
 
#define AHCI_BOHC_OOS   0x00000008
 
#define AHCI_BOHC_BOS   0x00000010
 
#define IDX_AHCI_CAP   (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP))
 
#define IDX_AHCI_GHC   (FIELD_OFFSET(IDE_AHCI_REGISTERS, GHC))
 
#define IDX_AHCI_IS   (FIELD_OFFSET(IDE_AHCI_REGISTERS, IS))
 
#define IDX_AHCI_VS   (FIELD_OFFSET(IDE_AHCI_REGISTERS, VS))
 
#define IDX_AHCI_PI   (FIELD_OFFSET(IDE_AHCI_REGISTERS, PI))
 
#define IDX_AHCI_CAP2   (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP2))
 
#define IDX_AHCI_BOHC   (FIELD_OFFSET(IDE_AHCI_REGISTERS, BOHC))
 
#define SStatus_DET_NoDev   0x00
 
#define SStatus_DET_Dev_NoPhy   0x01
 
#define SStatus_DET_Dev_Ok   0x03
 
#define SStatus_DET_Offline   0x04
 
#define SStatus_SPD_NoDev   0x00
 
#define SStatus_SPD_Gen1   0x01
 
#define SStatus_SPD_Gen2   0x02
 
#define SStatus_SPD_Gen3   0x03
 
#define SStatus_IPM_NoDev   0x00
 
#define SStatus_IPM_Active   0x01
 
#define SStatus_IPM_Partial   0x02
 
#define SStatus_IPM_Slumber   0x06
 
#define ATA_SS_DET_MASK   0x0000000f
 
#define ATA_SS_DET_NO_DEVICE   0x00000000
 
#define ATA_SS_DET_DEV_PRESENT   0x00000001
 
#define ATA_SS_DET_PHY_ONLINE   0x00000003
 
#define ATA_SS_DET_PHY_OFFLINE   0x00000004
 
#define ATA_SS_SPD_MASK   0x000000f0
 
#define ATA_SS_SPD_NO_SPEED   0x00000000
 
#define ATA_SS_SPD_GEN1   0x00000010
 
#define ATA_SS_SPD_GEN2   0x00000020
 
#define ATA_SS_IPM_MASK   0x00000f00
 
#define ATA_SS_IPM_NO_DEVICE   0x00000000
 
#define ATA_SS_IPM_ACTIVE   0x00000100
 
#define ATA_SS_IPM_PARTIAL   0x00000200
 
#define ATA_SS_IPM_SLUMBER   0x00000600
 
#define SControl_DET_DoNothing   0x00
 
#define SControl_DET_Idle   0x00
 
#define SControl_DET_Init   0x01
 
#define SControl_DET_Disable   0x04
 
#define SControl_SPD_NoRestrict   0x00
 
#define SControl_SPD_LimGen1   0x01
 
#define SControl_SPD_LimGen2   0x02
 
#define SControl_SPD_LimGen3   0x03
 
#define SControl_IPM_NoRestrict   0x00
 
#define SControl_IPM_NoPartial   0x01
 
#define SControl_IPM_NoSlumber   0x02
 
#define SControl_IPM_NoPartialSlumber   0x03
 
#define ATA_SC_DET_MASK   0x0000000f
 
#define ATA_SC_DET_IDLE   0x00000000
 
#define ATA_SC_DET_RESET   0x00000001
 
#define ATA_SC_DET_DISABLE   0x00000004
 
#define ATA_SC_SPD_MASK   0x000000f0
 
#define ATA_SC_SPD_NO_SPEED   0x00000000
 
#define ATA_SC_SPD_SPEED_GEN1   0x00000010
 
#define ATA_SC_SPD_SPEED_GEN2   0x00000020
 
#define ATA_SC_SPD_SPEED_GEN3   0x00000040
 
#define ATA_SC_IPM_MASK   0x00000f00
 
#define ATA_SC_IPM_NONE   0x00000000
 
#define ATA_SC_IPM_DIS_PARTIAL   0x00000100
 
#define ATA_SC_IPM_DIS_SLUMBER   0x00000200
 
#define ATA_SE_DATA_CORRECTED   0x00000001
 
#define ATA_SE_COMM_CORRECTED   0x00000002
 
#define ATA_SE_DATA_ERR   0x00000100
 
#define ATA_SE_COMM_ERR   0x00000200
 
#define ATA_SE_PROT_ERR   0x00000400
 
#define ATA_SE_HOST_ERR   0x00000800
 
#define ATA_SE_PHY_CHANGED   0x00010000
 
#define ATA_SE_PHY_IERROR   0x00020000
 
#define ATA_SE_COMM_WAKE   0x00040000
 
#define ATA_SE_DECODE_ERR   0x00080000
 
#define ATA_SE_PARITY_ERR   0x00100000
 
#define ATA_SE_CRC_ERR   0x00200000
 
#define ATA_SE_HANDSHAKE_ERR   0x00400000
 
#define ATA_SE_LINKSEQ_ERR   0x00800000
 
#define ATA_SE_TRANSPORT_ERR   0x01000000
 
#define ATA_SE_UNKNOWN_FIS   0x02000000
 
#define IDX_SATA_IO   (IDX_BM_IO+IDX_BM_IO_SZ)
 
#define IDX_SATA_IO_SZ   5
 
#define IDX_SATA_SStatus   (0+IDX_SATA_IO)
 
#define IDX_SATA_SError   (1+IDX_SATA_IO)
 
#define IDX_SATA_SControl   (2+IDX_SATA_IO)
 
#define IDX_SATA_SActive   (3+IDX_SATA_IO)
 
#define IDX_SATA_SNTF_PMN   (4+IDX_SATA_IO)
 
#define IDX_INDEXED_IO   (IDX_SATA_IO+IDX_SATA_IO_SZ)
 
#define IDX_INDEXED_IO_SZ   2
 
#define IDX_INDEXED_ADDR   (0+IDX_INDEXED_IO)
 
#define IDX_INDEXED_DATA   (1+IDX_INDEXED_IO)
 
#define IDX_MAX_REG   (IDX_INDEXED_IO+IDX_INDEXED_IO_SZ)
 
#define ATA_AHCI_P_IX_DHR   0x00000001
 
#define ATA_AHCI_P_IX_PS   0x00000002
 
#define ATA_AHCI_P_IX_DS   0x00000004
 
#define ATA_AHCI_P_IX_SDB   0x00000008
 
#define ATA_AHCI_P_IX_UF   0x00000010
 
#define ATA_AHCI_P_IX_DP   0x00000020
 
#define ATA_AHCI_P_IX_PC   0x00000040
 
#define ATA_AHCI_P_IX_DI   0x00000080
 
#define ATA_AHCI_P_IX_PRC   0x00400000
 
#define ATA_AHCI_P_IX_IPM   0x00800000
 
#define ATA_AHCI_P_IX_OF   0x01000000
 
#define ATA_AHCI_P_IX_INF   0x04000000
 
#define ATA_AHCI_P_IX_IF   0x08000000
 
#define ATA_AHCI_P_IX_HBD   0x10000000
 
#define ATA_AHCI_P_IX_HBF   0x20000000
 
#define ATA_AHCI_P_IX_TFE   0x40000000
 
#define ATA_AHCI_P_IX_CPD   0x80000000
 
#define AHCI_CLB_ALIGNEMENT_MASK   ((ULONGLONG)(1024-1))
 
#define AHCI_FIS_ALIGNEMENT_MASK   ((ULONGLONG)(256-1))
 
#define AHCI_CMD_ALIGNEMENT_MASK   ((ULONGLONG)(128-1))
 
#define SATA_CMD_ICC_Idle   0x00
 
#define SATA_CMD_ICC_NoOp   0x00
 
#define SATA_CMD_ICC_Active   0x01
 
#define SATA_CMD_ICC_Partial   0x02
 
#define SATA_CMD_ICC_Slumber   0x06
 
#define IDX_AHCI_P_CLB   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CLB))
 
#define IDX_AHCI_P_FB   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, FB))
 
#define IDX_AHCI_P_IS   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IS))
 
#define IDX_AHCI_P_IE   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IE))
 
#define IDX_AHCI_P_CI   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CI))
 
#define IDX_AHCI_P_TFD   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, TFD))
 
#define IDX_AHCI_P_SIG   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SIG))
 
#define IDX_AHCI_P_CMD   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CMD))
 
#define IDX_AHCI_P_SStatus   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SStatus))
 
#define IDX_AHCI_P_SControl   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SControl))
 
#define IDX_AHCI_P_SError   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SError))
 
#define IDX_AHCI_P_ACT   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SACT))
 
#define IDX_AHCI_P_SNTF   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SNTF))
 
#define ATA_AHCI_P_CMD_ST   0x00000001
 
#define ATA_AHCI_P_CMD_SUD   0x00000002
 
#define ATA_AHCI_P_CMD_POD   0x00000004
 
#define ATA_AHCI_P_CMD_CLO   0x00000008
 
#define ATA_AHCI_P_CMD_FRE   0x00000010
 
#define ATA_AHCI_P_CMD_CCS_MASK   0x00001f00
 
#define ATA_AHCI_P_CMD_ISS   0x00002000
 
#define ATA_AHCI_P_CMD_FR   0x00004000
 
#define ATA_AHCI_P_CMD_CR   0x00008000
 
#define ATA_AHCI_P_CMD_CPS   0x00010000
 
#define ATA_AHCI_P_CMD_PMA   0x00020000
 
#define ATA_AHCI_P_CMD_HPCP   0x00040000
 
#define ATA_AHCI_P_CMD_ISP   0x00080000
 
#define ATA_AHCI_P_CMD_CPD   0x00100000
 
#define ATA_AHCI_P_CMD_ESP   0x00200000
 
#define ATA_AHCI_P_CMD_ATAPI   0x01000000
 
#define ATA_AHCI_P_CMD_DLAE   0x02000000
 
#define ATA_AHCI_P_CMD_ALPE   0x04000000
 
#define ATA_AHCI_P_CMD_ASP   0x08000000
 
#define ATA_AHCI_P_CMD_ICC_MASK   0xf0000000
 
#define ATA_AHCI_P_CMD_NOOP   0x00000000
 
#define ATA_AHCI_P_CMD_ACTIVE   0x10000000
 
#define ATA_AHCI_P_CMD_PARTIAL   0x20000000
 
#define ATA_AHCI_P_CMD_SLUMBER   0x60000000
 
#define ATA_AHCI_DMA_ENTRIES   (PAGE_SIZE/2/sizeof(IDE_AHCI_PRD_ENTRY)) /* 128 */
 
#define ATA_AHCI_MAX_TAGS   32
 
#define AHCI_FIS_TYPE_ATA_H2D   0x27
 
#define AHCI_FIS_TYPE_ATA_D2H   0x34
 
#define AHCI_FIS_TYPE_DMA_D2H   0x39
 
#define AHCI_FIS_TYPE_DMA_BiDi   0x41
 
#define AHCI_FIS_TYPE_DATA_BiDi   0x46
 
#define AHCI_FIS_TYPE_BIST_BiDi   0x58
 
#define AHCI_FIS_TYPE_PIO_D2H   0x5f
 
#define AHCI_FIS_TYPE_DEV_BITS_D2H   0xA1
 
#define IDX_AHCI_o_Command   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Command))
 
#define IDX_AHCI_o_Feature   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Feature))
 
#define IDX_AHCI_o_BlockNumber   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockNumber ))
 
#define IDX_AHCI_o_CylinderLow   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderLow ))
 
#define IDX_AHCI_o_CylinderHigh   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderHigh))
 
#define IDX_AHCI_o_DriveSelect   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, DriveSelect ))
 
#define IDX_AHCI_o_BlockCount   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockCount))
 
#define IDX_AHCI_o_Control   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Control))
 
#define IDX_AHCI_o_FeatureExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, FeatureExp))
 
#define IDX_AHCI_o_BlockNumberExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockNumberExp ))
 
#define IDX_AHCI_o_CylinderLowExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderLowExp ))
 
#define IDX_AHCI_o_CylinderHighExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderHighExp))
 
#define IDX_AHCI_o_BlockCountExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockCountExp))
 
#define AHCI_FIS_COMM_PM   (0x80 | AHCI_DEV_SEL_PM)
 
#define AHCI_DEV_SEL_1   0x00
 
#define AHCI_DEV_SEL_2   0x01
 
#define AHCI_DEV_SEL_PM   0x0f
 
#define ATA_AHCI_CMD_ATAPI   0x0020
 
#define ATA_AHCI_CMD_WRITE   0x0040
 
#define ATA_AHCI_CMD_PREFETCH   0x0080
 
#define ATA_AHCI_CMD_RESET   0x0100
 
#define ATA_AHCI_CMD_BIST   0x0200
 
#define ATA_AHCI_CMD_CLR_BUSY   0x0400
 
#define IsBusMaster(pciData)
 
#define PCI_IDE_PROGIF_NATIVE_1   0x01
 
#define PCI_IDE_PROGIF_NATIVE_2   0x04
 
#define PCI_IDE_PROGIF_NATIVE_ALL   0x05
 
#define IsMasterDev(pciData)
 
#define MIN_REQ_TTL   4
 
#define REQ_FLAG_FORCE_DOWNRATE   0x01
 
#define REQ_FLAG_DMA_OPERATION   0x02
 
#define REQ_FLAG_REORDERABLE_CMD   0x04
 
#define REQ_FLAG_RW_MASK   0x08
 
#define REQ_FLAG_READ   0x08
 
#define REQ_FLAG_WRITE   0x00
 
#define REQ_FLAG_FORCE_DOWNRATE_LBA48   0x10
 
#define REQ_FLAG_DMA_DBUF   0x20
 
#define REQ_FLAG_DMA_DBUF_PRD   0x40
 
#define REQ_FLAG_LBA48   0x80
 
#define REQ_STATE_NONE   0x00
 
#define REQ_STATE_QUEUED   0x10
 
#define REQ_STATE_PREPARE_TO_TRANSFER   0x20
 
#define REQ_STATE_PREPARE_TO_NEXT   0x21
 
#define REQ_STATE_READY_TO_TRANSFER   0x30
 
#define REQ_STATE_EXPECTING_INTR   0x40
 
#define REQ_STATE_ATAPI_EXPECTING_CMD_INTR   0x41
 
#define REQ_STATE_ATAPI_EXPECTING_DATA_INTR   0x42
 
#define REQ_STATE_ATAPI_EXPECTING_DATA_INTR2   0x43
 
#define REQ_STATE_ATAPI_DO_NOTHING_INTR   0x44
 
#define REQ_STATE_EARLY_INTR   0x48
 
#define REQ_STATE_PROCESSING_INTR   0x50
 
#define REQ_STATE_DPC_INTR_REQ   0x51
 
#define REQ_STATE_DPC_RESET_REQ   0x52
 
#define REQ_STATE_DPC_COMPLETE_REQ   0x53
 
#define REQ_STATE_DPC_WAIT_BUSY0   0x57
 
#define REQ_STATE_DPC_WAIT_BUSY1   0x58
 
#define REQ_STATE_DPC_WAIT_BUSY   0x59
 
#define REQ_STATE_DPC_WAIT_DRQ   0x5a
 
#define REQ_STATE_DPC_WAIT_DRQ0   0x5b
 
#define REQ_STATE_DPC_WAIT_DRQ_ERR   0x5c
 
#define REQ_STATE_TRANSFER_COMPLETE   0x7f
 
#define CMD_ACTION_PREPARE   0x01
 
#define CMD_ACTION_EXEC   0x02
 
#define CMD_ACTION_ALL   (CMD_ACTION_PREPARE | CMD_ACTION_EXEC)
 
#define REORDER_COST_MAX   ((DEF_I64(0x1) << 60) - 1)
 
#define REORDER_COST_TTL   (REORDER_COST_MAX - 1)
 
#define REORDER_COST_INTERSECT   (REORDER_COST_MAX - 2)
 
#define REORDER_COST_DENIED   (REORDER_COST_MAX - 3)
 
#define REORDER_COST_RESELECT   (REORDER_COST_MAX/4)
 
#define REORDER_COST_SWITCH_RW_CD   (REORDER_COST_MAX/8)
 
#define REORDER_MCOST_SWITCH_RW_CD   (0)
 
#define REORDER_MCOST_SEEK_BACK_CD   (16)
 
#define REORDER_COST_SWITCH_RW_HDD   (0)
 
#define REORDER_MCOST_SWITCH_RW_HDD   (4)
 
#define REORDER_MCOST_SEEK_BACK_HDD   (2)
 
#define CHECK_INTR_ACTIVE   0x03
 
#define CHECK_INTR_DETECTED   0x02
 
#define CHECK_INTR_CHECK   0x01
 
#define CHECK_INTR_IDLE   0x00
 
#define CTRFLAGS_DMA_ACTIVE   0x0001
 
#define CTRFLAGS_DMA_RO   0x0002
 
#define CTRFLAGS_DMA_OPERATION   0x0004
 
#define CTRFLAGS_INTR_DISABLED   0x0008
 
#define CTRFLAGS_DPC_REQ   0x0010
 
#define CTRFLAGS_ENABLE_INTR_REQ   0x0020
 
#define CTRFLAGS_LBA48   0x0040
 
#define CTRFLAGS_DSC_BSY   0x0080
 
#define CTRFLAGS_NO_SLAVE   0x0100
 
#define CTRFLAGS_AHCI_PM   0x0400
 
#define CTRFLAGS_AHCI_PM2   0x0800
 
#define CTRFLAGS_PERMANENT   (CTRFLAGS_DMA_RO | CTRFLAGS_NO_SLAVE)
 
#define GEOM_AUTO   0xffffffff
 
#define GEOM_STD   0x0000
 
#define GEOM_UNIATA   0x0001
 
#define GEOM_ORIG   0x0002
 
#define GEOM_MANUAL   0x0003
 
#define DPC_STATE_NONE   0x00
 
#define DPC_STATE_ISR   0x10
 
#define DPC_STATE_DPC   0x20
 
#define DPC_STATE_TIMER   0x30
 
#define DPC_STATE_COMPLETE   0x40
 
#define HBAFLAGS_DMA_DISABLED   0x01
 
#define HBAFLAGS_DMA_DISABLED_LBA48   0x02
 
#define UNIATA_ALLOCATE_NEW_LUNS   0x00
 
#define PCIBUSNUM_NOT_SPECIFIED   (0xffffffffL)
 
#define PCISLOTNUM_NOT_SPECIFIED   (0xffffffffL)
 
#define GetPciConfig1(offs, op)
 
#define SetPciConfig1(offs, op)
 
#define ChangePciConfig1(offs, _op)
 
#define GetPciConfig2(offs, op)
 
#define SetPciConfig2(offs, op)
 
#define ChangePciConfig2(offs, _op)
 
#define GetPciConfig4(offs, op)
 
#define SetPciConfig4(offs, op)
 
#define ChangePciConfig4(offs, _op)
 
#define DMA_MODE_NONE   0x00
 
#define DMA_MODE_BM   0x01
 
#define DMA_MODE_AHCI   0x02
 
#define GetDmaStatus(de, c)    (((de)->BusMaster == DMA_MODE_BM) ? AtapiReadPort1(&((de)->chan[c]), IDX_BM_Status) : 0)
 
#define AtapiVirtToPhysAddr(hwde, srb, phaddr, plen, phaddru)    AtapiVirtToPhysAddr_(hwde, srb, phaddr, plen, phaddru);
 
#define GET_CHANNEL(Srb)   (Srb->PathId)
 
#define GET_CDEV(Srb)   (Srb->TargetId)
 
#define VM_AUTO   0x00
 
#define VM_NONE   0x01
 
#define VM_VBOX   0x02
 
#define VM_VMWARE   0x03
 
#define VM_QEMU   0x04
 
#define VM_BOCHS   0x05
 
#define VM_PCEM   0x06
 
#define VM_MAX_KNOWN   VM_PCEM
 

Typedefs

typedef struct _BUSMASTER_CTX BUSMASTER_CTX
 
typedef struct _BUSMASTER_CTX * PBUSMASTER_CTX
 
typedef struct BM_DMA_ENTRY BM_DMA_ENTRY
 
typedef struct BM_DMA_ENTRY * PBM_DMA_ENTRY
 
typedef struct _IDE_BUSMASTER_REGISTERS IDE_BUSMASTER_REGISTERS
 
typedef struct _IDE_BUSMASTER_REGISTERS * PIDE_BUSMASTER_REGISTERS
 
typedef struct _IDE_AHCI_REGISTERS IDE_AHCI_REGISTERS
 
typedef struct _IDE_AHCI_REGISTERS * PIDE_AHCI_REGISTERS
 
typedef union _SATA_SSTATUS_REG SATA_SSTATUS_REG
 
typedef union _SATA_SSTATUS_REG * PSATA_SSTATUS_REG
 
typedef union _SATA_SCONTROL_REG SATA_SCONTROL_REG
 
typedef union _SATA_SCONTROL_REG * PSATA_SCONTROL_REG
 
typedef union _SATA_SERROR_REG SATA_SERROR_REG
 
typedef union _SATA_SERROR_REG * PSATA_SERROR_REG
 
typedef struct _IDE_SATA_REGISTERS IDE_SATA_REGISTERS
 
typedef struct _IDE_SATA_REGISTERS * PIDE_SATA_REGISTERS
 
typedef union _AHCI_IS_REG AHCI_IS_REG
 
typedef union _AHCI_IS_REG * PAHCI_IS_REG
 
typedef struct _IDE_AHCI_PORT_REGISTERS IDE_AHCI_PORT_REGISTERS
 
typedef struct _IDE_AHCI_PORT_REGISTERS * PIDE_AHCI_PORT_REGISTERS
 
typedef struct _IDE_AHCI_PRD_ENTRY IDE_AHCI_PRD_ENTRY
 
typedef struct _IDE_AHCI_PRD_ENTRY * PIDE_AHCI_PRD_ENTRY
 
typedef struct _AHCI_ATA_H2D_FIS AHCI_ATA_H2D_FIS
 
typedef struct _AHCI_ATA_H2D_FIS * PAHCI_ATA_H2D_FIS
 
typedef struct _IDE_AHCI_CMD IDE_AHCI_CMD
 
typedef struct _IDE_AHCI_CMD * PIDE_AHCI_CMD
 
typedef struct _IDE_AHCI_CMD_LIST IDE_AHCI_CMD_LIST
 
typedef struct _IDE_AHCI_CMD_LIST * PIDE_AHCI_CMD_LIST
 
typedef struct _IDE_AHCI_RCV_FIS IDE_AHCI_RCV_FIS
 
typedef struct _IDE_AHCI_RCV_FIS * PIDE_AHCI_RCV_FIS
 
typedef struct _IDE_AHCI_CHANNEL_CTL_BLOCK IDE_AHCI_CHANNEL_CTL_BLOCK
 
typedef struct _IDE_AHCI_CHANNEL_CTL_BLOCK * PIDE_AHCI_CHANNEL_CTL_BLOCK
 
typedef union _ATA_REQ ATA_REQ
 
typedef union _ATA_REQ * PATA_REQ
 
typedef struct _IORES IORES
 
typedef struct _IORES * PIORES
 
typedef struct _HW_CHANNEL HW_CHANNEL
 
typedef struct _HW_CHANNEL * PHW_CHANNEL
 
typedef struct _HW_LU_EXTENSION HW_LU_EXTENSION
 
typedef struct _HW_LU_EXTENSION * PHW_LU_EXTENSION
 
typedef struct _HW_DEVICE_EXTENSION HW_DEVICE_EXTENSION
 
typedef struct _HW_DEVICE_EXTENSION * PHW_DEVICE_EXTENSION
 
typedef struct _ISR2_DEVICE_EXTENSION ISR2_DEVICE_EXTENSION
 
typedef struct _ISR2_DEVICE_EXTENSION * PISR2_DEVICE_EXTENSION
 
typedef ISR2_DEVICE_EXTENSION PCIIDE_DEVICE_EXTENSION
 
typedef PISR2_DEVICE_EXTENSION PPCIIDE_DEVICE_EXTENSION
 

Functions

VOID NTAPI UniataEnumBusMasterController (IN PVOID DriverObject, PVOID Argument2)
 
ULONG NTAPI UniataFindCompatBusMasterController1 (IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
 
ULONG NTAPI UniataFindCompatBusMasterController2 (IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
 
BOOLEAN NTAPI UniataAllocateLunExt (PHW_DEVICE_EXTENSION deviceExtension, ULONG NewNumberChannels)
 
VOID NTAPI UniataFreeLunExt (PHW_DEVICE_EXTENSION deviceExtension)
 
ULONG NTAPI UniataFindBusMasterController (IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
 
NTSTATUS NTAPI UniataClaimLegacyPCIIDE (ULONG i)
 
NTSTATUS NTAPI UniataConnectIntr2 (IN PVOID HwDeviceExtension)
 
NTSTATUS NTAPI UniataDisconnectIntr2 (IN PVOID HwDeviceExtension)
 
ULONG NTAPI ScsiPortGetBusDataByOffset (IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
 
ULONG NTAPI AtapiFindListedDev (PBUSMASTER_CONTROLLER_INFORMATION_BASE BusMasterAdapters, ULONG lim, IN PVOID HwDeviceExtension, IN ULONG BusNumber, IN ULONG SlotNumber, OUT PCI_SLOT_NUMBER *_slotData)
 
ULONG NTAPI AtapiFindDev (IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN ULONG dev_id, IN ULONG RevID)
 
VOID NTAPI AtapiDmaAlloc (IN PVOID HwDeviceExtension, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN ULONG lChannel)
 
BOOLEAN NTAPI AtapiDmaSetup (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb, IN PUCHAR data, IN ULONG count)
 
BOOLEAN NTAPI AtapiDmaPioSync (PVOID HwDeviceExtension, PSCSI_REQUEST_BLOCK Srb, PUCHAR data, ULONG count)
 
BOOLEAN NTAPI AtapiDmaDBSync (PHW_CHANNEL chan, PSCSI_REQUEST_BLOCK Srb)
 
BOOLEAN NTAPI AtapiDmaDBPreSync (IN PVOID HwDeviceExtension, PHW_CHANNEL chan, PSCSI_REQUEST_BLOCK Srb)
 
VOID NTAPI AtapiDmaStart (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb)
 
UCHAR NTAPI AtapiDmaDone (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb)
 
VOID NTAPI AtapiDmaReinit (IN PHW_DEVICE_EXTENSION deviceExtension, IN PHW_LU_EXTENSION LunExt, IN PATA_REQ AtaReq)
 
VOID NTAPI AtapiDmaInit__ (IN PHW_DEVICE_EXTENSION deviceExtension, IN PHW_LU_EXTENSION LunExt)
 
VOID NTAPI AtapiDmaInit (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN SCHAR apiomode, IN SCHAR wdmamode, IN SCHAR udmamode)
 
BOOLEAN NTAPI AtapiInterrupt2 (IN PKINTERRUPT Interrupt, IN PVOID HwDeviceExtension)
 
BOOLEAN NTAPI UniataChipDetectChannels (IN PVOID HwDeviceExtension, IN PPCI_COMMON_CONFIG pciData, IN ULONG DeviceNumber, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo)
 
NTSTATUS NTAPI UniataChipDetect (IN PVOID HwDeviceExtension, IN PPCI_COMMON_CONFIG pciData, IN ULONG DeviceNumber, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN BOOLEAN *simplexOnly)
 
BOOLEAN NTAPI AtapiChipInit (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG c)
 
ULONGIO_PTR NTAPI AtapiGetIoRange (IN PVOID HwDeviceExtension, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN PPCI_COMMON_CONFIG pciData, IN ULONG SystemIoBusNumber, IN ULONG rid, IN ULONG offset, IN ULONG length)
 
USHORT NTAPI UniataEnableIoPCI (IN ULONG busNumber, IN ULONG slotNumber, IN OUT PPCI_COMMON_CONFIG pciData)
 
VOID DDKFASTAPI AtapiWritePort4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG data)
 
VOID DDKFASTAPI AtapiWritePort2 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN USHORT data)
 
VOID DDKFASTAPI AtapiWritePort1 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN UCHAR data)
 
VOID DDKFASTAPI AtapiWritePortEx4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN ULONG data)
 
VOID DDKFASTAPI AtapiWritePortEx1 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN UCHAR data)
 
ULONG DDKFASTAPI AtapiReadPort4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
 
USHORT DDKFASTAPI AtapiReadPort2 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
 
UCHAR DDKFASTAPI AtapiReadPort1 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
 
ULONG DDKFASTAPI AtapiReadPortEx4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
 
UCHAR DDKFASTAPI AtapiReadPortEx1 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
 
VOID DDKFASTAPI AtapiWriteBuffer4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
 
VOID DDKFASTAPI AtapiWriteBuffer2 (IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
 
VOID DDKFASTAPI AtapiReadBuffer4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
 
VOID DDKFASTAPI AtapiReadBuffer2 (IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
 
VOID NTAPI AtapiSetupLunPtrs (IN PHW_CHANNEL chan, IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG c)
 
BOOLEAN NTAPI AtapiReadChipConfig (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG channel)
 
VOID NTAPI UniataForgetDevice (PHW_LU_EXTENSION LunExt)
 

Variables

UCHAR pciBuffer [256]
 
PBUSMASTER_CONTROLLER_INFORMATION BMList
 
ULONG BMListLen
 
ULONG IsaCount
 
ULONG MCACount
 
UNICODE_STRING SavedRegPath
 
PDRIVER_OBJECT SavedDriverObject
 
ULONG SkipRaids
 
ULONG ForceSimplex
 
BOOLEAN g_opt_AtapiDmaRawRead
 
BOOLEAN hasPCI
 
BOOLEAN InDriverEntry
 
BOOLEAN g_Dump
 
BOOLEAN g_opt_Verbose
 
ULONG g_opt_VirtualMachine
 
ULONG g_opt_WaitBusyResetCount
 
ULONG CPU_num
 
BOOLEAN WinVer_WDM_Model
 

Macro Definition Documentation

◆ AHCI_BOHC_BB

#define AHCI_BOHC_BB   0x00000001

Definition at line 259 of file bsmaster.h.

◆ AHCI_BOHC_BOS

#define AHCI_BOHC_BOS   0x00000010

Definition at line 263 of file bsmaster.h.

◆ AHCI_BOHC_OOC

#define AHCI_BOHC_OOC   0x00000002

Definition at line 260 of file bsmaster.h.

◆ AHCI_BOHC_OOS

#define AHCI_BOHC_OOS   0x00000008

Definition at line 262 of file bsmaster.h.

◆ AHCI_BOHC_SOOE

#define AHCI_BOHC_SOOE   0x00000004

Definition at line 261 of file bsmaster.h.

◆ AHCI_CAP2_APST

#define AHCI_CAP2_APST   0x00000004

Definition at line 247 of file bsmaster.h.

◆ AHCI_CAP2_BOH

#define AHCI_CAP2_BOH   0x00000001

Definition at line 245 of file bsmaster.h.

◆ AHCI_CAP2_NVMP

#define AHCI_CAP2_NVMP   0x00000002

Definition at line 246 of file bsmaster.h.

◆ AHCI_CAP_CCC

#define AHCI_CAP_CCC   0x00000080

Definition at line 201 of file bsmaster.h.

◆ AHCI_CAP_ISS_MASK

#define AHCI_CAP_ISS_MASK   0x00f00000

Definition at line 206 of file bsmaster.h.

◆ AHCI_CAP_NCQ

#define AHCI_CAP_NCQ   0x40000000

Definition at line 209 of file bsmaster.h.

◆ AHCI_CAP_NCS_MASK

#define AHCI_CAP_NCS_MASK   0x00001f00

Definition at line 202 of file bsmaster.h.

◆ AHCI_CAP_NOP_MASK

#define AHCI_CAP_NOP_MASK   0x0000001f

Definition at line 200 of file bsmaster.h.

◆ AHCI_CAP_PMD

#define AHCI_CAP_PMD   0x00008000

Definition at line 203 of file bsmaster.h.

◆ AHCI_CAP_S64A

#define AHCI_CAP_S64A   0x80000000

Definition at line 210 of file bsmaster.h.

◆ AHCI_CAP_SAM

#define AHCI_CAP_SAM   0x00040000

Definition at line 205 of file bsmaster.h.

◆ AHCI_CAP_SCLO

#define AHCI_CAP_SCLO   0x01000000

Definition at line 207 of file bsmaster.h.

◆ AHCI_CAP_SNTF

#define AHCI_CAP_SNTF   0x20000000

Definition at line 208 of file bsmaster.h.

◆ AHCI_CAP_SPM

#define AHCI_CAP_SPM   0x00020000

Definition at line 204 of file bsmaster.h.

◆ AHCI_CLB_ALIGNEMENT_MASK

#define AHCI_CLB_ALIGNEMENT_MASK   ((ULONGLONG)(1024-1))

Definition at line 518 of file bsmaster.h.

◆ AHCI_CMD_ALIGNEMENT_MASK

#define AHCI_CMD_ALIGNEMENT_MASK   ((ULONGLONG)(128-1))

Definition at line 520 of file bsmaster.h.

◆ AHCI_DEV_SEL_1

#define AHCI_DEV_SEL_1   0x00

Definition at line 801 of file bsmaster.h.

◆ AHCI_DEV_SEL_2

#define AHCI_DEV_SEL_2   0x01

Definition at line 802 of file bsmaster.h.

◆ AHCI_DEV_SEL_PM

#define AHCI_DEV_SEL_PM   0x0f

Definition at line 803 of file bsmaster.h.

◆ AHCI_FIS_ALIGNEMENT_MASK

#define AHCI_FIS_ALIGNEMENT_MASK   ((ULONGLONG)(256-1))

Definition at line 519 of file bsmaster.h.

◆ AHCI_FIS_COMM_PM

#define AHCI_FIS_COMM_PM   (0x80 | AHCI_DEV_SEL_PM)

Definition at line 799 of file bsmaster.h.

◆ AHCI_FIS_TYPE_ATA_D2H

#define AHCI_FIS_TYPE_ATA_D2H   0x34

Definition at line 753 of file bsmaster.h.

◆ AHCI_FIS_TYPE_ATA_H2D

#define AHCI_FIS_TYPE_ATA_H2D   0x27

Definition at line 752 of file bsmaster.h.

◆ AHCI_FIS_TYPE_BIST_BiDi

#define AHCI_FIS_TYPE_BIST_BiDi   0x58

Definition at line 757 of file bsmaster.h.

◆ AHCI_FIS_TYPE_DATA_BiDi

#define AHCI_FIS_TYPE_DATA_BiDi   0x46

Definition at line 756 of file bsmaster.h.

◆ AHCI_FIS_TYPE_DEV_BITS_D2H

#define AHCI_FIS_TYPE_DEV_BITS_D2H   0xA1

Definition at line 759 of file bsmaster.h.

◆ AHCI_FIS_TYPE_DMA_BiDi

#define AHCI_FIS_TYPE_DMA_BiDi   0x41

Definition at line 755 of file bsmaster.h.

◆ AHCI_FIS_TYPE_DMA_D2H

#define AHCI_FIS_TYPE_DMA_D2H   0x39

Definition at line 754 of file bsmaster.h.

◆ AHCI_FIS_TYPE_PIO_D2H

#define AHCI_FIS_TYPE_PIO_D2H   0x5f

Definition at line 758 of file bsmaster.h.

◆ AHCI_GHC

#define AHCI_GHC   0x04

Definition at line 220 of file bsmaster.h.

◆ AHCI_GHC_AE

#define AHCI_GHC_AE   0x80000000

Definition at line 223 of file bsmaster.h.

◆ AHCI_GHC_HR

#define AHCI_GHC_HR   0x00000001

Definition at line 221 of file bsmaster.h.

◆ AHCI_GHC_IE

#define AHCI_GHC_IE   0x00000002

Definition at line 222 of file bsmaster.h.

◆ AHCI_MAX_PORT

#define AHCI_MAX_PORT   32

Definition at line 108 of file bsmaster.h.

◆ ATA_ACTIVE

#define ATA_ACTIVE   0x4

Definition at line 58 of file bsmaster.h.

◆ ATA_ACTIVE_ATA

#define ATA_ACTIVE_ATA   0x5

Definition at line 59 of file bsmaster.h.

◆ ATA_ACTIVE_ATAPI

#define ATA_ACTIVE_ATAPI   0x6

Definition at line 60 of file bsmaster.h.

◆ ATA_AHCI_CMD_ATAPI

#define ATA_AHCI_CMD_ATAPI   0x0020

Definition at line 815 of file bsmaster.h.

◆ ATA_AHCI_CMD_BIST

#define ATA_AHCI_CMD_BIST   0x0200

Definition at line 819 of file bsmaster.h.

◆ ATA_AHCI_CMD_CLR_BUSY

#define ATA_AHCI_CMD_CLR_BUSY   0x0400

Definition at line 820 of file bsmaster.h.

◆ ATA_AHCI_CMD_PREFETCH

#define ATA_AHCI_CMD_PREFETCH   0x0080

Definition at line 817 of file bsmaster.h.

◆ ATA_AHCI_CMD_RESET

#define ATA_AHCI_CMD_RESET   0x0100

Definition at line 818 of file bsmaster.h.

◆ ATA_AHCI_CMD_WRITE

#define ATA_AHCI_CMD_WRITE   0x0040

Definition at line 816 of file bsmaster.h.

◆ ATA_AHCI_DMA_ENTRIES

#define ATA_AHCI_DMA_ENTRIES   (PAGE_SIZE/2/sizeof(IDE_AHCI_PRD_ENTRY)) /* 128 */

Definition at line 749 of file bsmaster.h.

◆ ATA_AHCI_MAX_TAGS

#define ATA_AHCI_MAX_TAGS   32

Definition at line 750 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ACTIVE

#define ATA_AHCI_P_CMD_ACTIVE   0x10000000

Definition at line 719 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ALPE

#define ATA_AHCI_P_CMD_ALPE   0x04000000

Definition at line 715 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ASP

#define ATA_AHCI_P_CMD_ASP   0x08000000

Definition at line 716 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ATAPI

#define ATA_AHCI_P_CMD_ATAPI   0x01000000

Definition at line 713 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_CCS_MASK

#define ATA_AHCI_P_CMD_CCS_MASK   0x00001f00

Definition at line 703 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_CLO

#define ATA_AHCI_P_CMD_CLO   0x00000008

Definition at line 701 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_CPD

#define ATA_AHCI_P_CMD_CPD   0x00100000

Definition at line 711 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_CPS

#define ATA_AHCI_P_CMD_CPS   0x00010000

Definition at line 707 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_CR

#define ATA_AHCI_P_CMD_CR   0x00008000

Definition at line 706 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_DLAE

#define ATA_AHCI_P_CMD_DLAE   0x02000000

Definition at line 714 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ESP

#define ATA_AHCI_P_CMD_ESP   0x00200000

Definition at line 712 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_FR

#define ATA_AHCI_P_CMD_FR   0x00004000

Definition at line 705 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_FRE

#define ATA_AHCI_P_CMD_FRE   0x00000010

Definition at line 702 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_HPCP

#define ATA_AHCI_P_CMD_HPCP   0x00040000

Definition at line 709 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ICC_MASK

#define ATA_AHCI_P_CMD_ICC_MASK   0xf0000000

Definition at line 717 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ISP

#define ATA_AHCI_P_CMD_ISP   0x00080000

Definition at line 710 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ISS

#define ATA_AHCI_P_CMD_ISS   0x00002000

Definition at line 704 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_NOOP

#define ATA_AHCI_P_CMD_NOOP   0x00000000

Definition at line 718 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_PARTIAL

#define ATA_AHCI_P_CMD_PARTIAL   0x20000000

Definition at line 720 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_PMA

#define ATA_AHCI_P_CMD_PMA   0x00020000

Definition at line 708 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_POD

#define ATA_AHCI_P_CMD_POD   0x00000004

Definition at line 700 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_SLUMBER

#define ATA_AHCI_P_CMD_SLUMBER   0x60000000

Definition at line 721 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ST

#define ATA_AHCI_P_CMD_ST   0x00000001

Definition at line 698 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_SUD

#define ATA_AHCI_P_CMD_SUD   0x00000002

Definition at line 699 of file bsmaster.h.

◆ ATA_AHCI_P_IX_CPD

#define ATA_AHCI_P_IX_CPD   0x80000000

Definition at line 516 of file bsmaster.h.

◆ ATA_AHCI_P_IX_DHR

#define ATA_AHCI_P_IX_DHR   0x00000001

Definition at line 499 of file bsmaster.h.

◆ ATA_AHCI_P_IX_DI

#define ATA_AHCI_P_IX_DI   0x00000080

Definition at line 506 of file bsmaster.h.

◆ ATA_AHCI_P_IX_DP

#define ATA_AHCI_P_IX_DP   0x00000020

Definition at line 504 of file bsmaster.h.

◆ ATA_AHCI_P_IX_DS

#define ATA_AHCI_P_IX_DS   0x00000004

Definition at line 501 of file bsmaster.h.

◆ ATA_AHCI_P_IX_HBD

#define ATA_AHCI_P_IX_HBD   0x10000000

Definition at line 513 of file bsmaster.h.

◆ ATA_AHCI_P_IX_HBF

#define ATA_AHCI_P_IX_HBF   0x20000000

Definition at line 514 of file bsmaster.h.

◆ ATA_AHCI_P_IX_IF

#define ATA_AHCI_P_IX_IF   0x08000000

Definition at line 512 of file bsmaster.h.

◆ ATA_AHCI_P_IX_INF

#define ATA_AHCI_P_IX_INF   0x04000000

Definition at line 511 of file bsmaster.h.

◆ ATA_AHCI_P_IX_IPM

#define ATA_AHCI_P_IX_IPM   0x00800000

Definition at line 509 of file bsmaster.h.

◆ ATA_AHCI_P_IX_OF

#define ATA_AHCI_P_IX_OF   0x01000000

Definition at line 510 of file bsmaster.h.

◆ ATA_AHCI_P_IX_PC

#define ATA_AHCI_P_IX_PC   0x00000040

Definition at line 505 of file bsmaster.h.

◆ ATA_AHCI_P_IX_PRC

#define ATA_AHCI_P_IX_PRC   0x00400000

Definition at line 508 of file bsmaster.h.

◆ ATA_AHCI_P_IX_PS

#define ATA_AHCI_P_IX_PS   0x00000002

Definition at line 500 of file bsmaster.h.

◆ ATA_AHCI_P_IX_SDB

#define ATA_AHCI_P_IX_SDB   0x00000008

Definition at line 502 of file bsmaster.h.

◆ ATA_AHCI_P_IX_TFE

#define ATA_AHCI_P_IX_TFE   0x40000000

Definition at line 515 of file bsmaster.h.

◆ ATA_AHCI_P_IX_UF

#define ATA_AHCI_P_IX_UF   0x00000010

Definition at line 503 of file bsmaster.h.

◆ ATA_ALTIOSIZE

#define ATA_ALTIOSIZE   0x01 /* alternate registers size */

Definition at line 89 of file bsmaster.h.

◆ ATA_ALTOFFSET

#define ATA_ALTOFFSET   0x206 /* alternate registers offset */

Definition at line 87 of file bsmaster.h.

◆ ATA_BM_OFFSET1

#define ATA_BM_OFFSET1   0x08

Definition at line 85 of file bsmaster.h.

◆ ATA_BMIOSIZE

#define ATA_BMIOSIZE   0x20

Definition at line 90 of file bsmaster.h.

◆ ATA_DMA_ENTRIES

#define ATA_DMA_ENTRIES   256 /* PAGESIZE/2/sizeof(BM_DMA_ENTRY)*/

Definition at line 100 of file bsmaster.h.

◆ ATA_DMA_EOT

#define ATA_DMA_EOT   0x80000000

Definition at line 101 of file bsmaster.h.

◆ ATA_IDLE

#define ATA_IDLE   0x0

Definition at line 54 of file bsmaster.h.

◆ ATA_IMMEDIATE

#define ATA_IMMEDIATE   0x1

Definition at line 55 of file bsmaster.h.

◆ ATA_IOSIZE

#define ATA_IOSIZE   0x08

Definition at line 86 of file bsmaster.h.

◆ ATA_MAX_IOLBA28

#define ATA_MAX_IOLBA28   DEF_U64(0x0fffff80)

Definition at line 94 of file bsmaster.h.

◆ ATA_MAX_IOLBA32

#define ATA_MAX_IOLBA32   DEF_U64(0xffffff80)

Definition at line 97 of file bsmaster.h.

◆ ATA_MAX_LBA28

#define ATA_MAX_LBA28   DEF_U64(0x0fffffff)

Definition at line 95 of file bsmaster.h.

◆ ATA_MAX_LBA32

#define ATA_MAX_LBA32   DEF_U64(0xffffffff)

Definition at line 98 of file bsmaster.h.

◆ ATA_PC98_BANKIOSIZE

#define ATA_PC98_BANKIOSIZE   0x01

Definition at line 91 of file bsmaster.h.

◆ ATA_PCCARD_ALTOFFSET

#define ATA_PCCARD_ALTOFFSET   0x0e /* do for PCCARD devices */

Definition at line 88 of file bsmaster.h.

◆ ATA_REINITING

#define ATA_REINITING   0x7

Definition at line 61 of file bsmaster.h.

◆ ATA_SC_DET_DISABLE

#define ATA_SC_DET_DISABLE   0x00000004

Definition at line 361 of file bsmaster.h.

◆ ATA_SC_DET_IDLE

#define ATA_SC_DET_IDLE   0x00000000

Definition at line 359 of file bsmaster.h.

◆ ATA_SC_DET_MASK

#define ATA_SC_DET_MASK   0x0000000f

Definition at line 358 of file bsmaster.h.

◆ ATA_SC_DET_RESET

#define ATA_SC_DET_RESET   0x00000001

Definition at line 360 of file bsmaster.h.

◆ ATA_SC_IPM_DIS_PARTIAL

#define ATA_SC_IPM_DIS_PARTIAL   0x00000100

Definition at line 371 of file bsmaster.h.

◆ ATA_SC_IPM_DIS_SLUMBER

#define ATA_SC_IPM_DIS_SLUMBER   0x00000200

Definition at line 372 of file bsmaster.h.

◆ ATA_SC_IPM_MASK

#define ATA_SC_IPM_MASK   0x00000f00

Definition at line 369 of file bsmaster.h.

◆ ATA_SC_IPM_NONE

#define ATA_SC_IPM_NONE   0x00000000

Definition at line 370 of file bsmaster.h.

◆ ATA_SC_SPD_MASK

#define ATA_SC_SPD_MASK   0x000000f0

Definition at line 363 of file bsmaster.h.

◆ ATA_SC_SPD_NO_SPEED

#define ATA_SC_SPD_NO_SPEED   0x00000000

Definition at line 364 of file bsmaster.h.

◆ ATA_SC_SPD_SPEED_GEN1

#define ATA_SC_SPD_SPEED_GEN1   0x00000010

Definition at line 365 of file bsmaster.h.

◆ ATA_SC_SPD_SPEED_GEN2

#define ATA_SC_SPD_SPEED_GEN2   0x00000020

Definition at line 366 of file bsmaster.h.

◆ ATA_SC_SPD_SPEED_GEN3

#define ATA_SC_SPD_SPEED_GEN3   0x00000040

Definition at line 367 of file bsmaster.h.

◆ ATA_SE_COMM_CORRECTED

#define ATA_SE_COMM_CORRECTED   0x00000002

Definition at line 410 of file bsmaster.h.

◆ ATA_SE_COMM_ERR

#define ATA_SE_COMM_ERR   0x00000200

Definition at line 412 of file bsmaster.h.

◆ ATA_SE_COMM_WAKE

#define ATA_SE_COMM_WAKE   0x00040000

Definition at line 417 of file bsmaster.h.

◆ ATA_SE_CRC_ERR

#define ATA_SE_CRC_ERR   0x00200000

Definition at line 420 of file bsmaster.h.

◆ ATA_SE_DATA_CORRECTED

#define ATA_SE_DATA_CORRECTED   0x00000001

Definition at line 409 of file bsmaster.h.

◆ ATA_SE_DATA_ERR

#define ATA_SE_DATA_ERR   0x00000100

Definition at line 411 of file bsmaster.h.

◆ ATA_SE_DECODE_ERR

#define ATA_SE_DECODE_ERR   0x00080000

Definition at line 418 of file bsmaster.h.

◆ ATA_SE_HANDSHAKE_ERR

#define ATA_SE_HANDSHAKE_ERR   0x00400000

Definition at line 421 of file bsmaster.h.

◆ ATA_SE_HOST_ERR

#define ATA_SE_HOST_ERR   0x00000800

Definition at line 414 of file bsmaster.h.

◆ ATA_SE_LINKSEQ_ERR

#define ATA_SE_LINKSEQ_ERR   0x00800000

Definition at line 422 of file bsmaster.h.

◆ ATA_SE_PARITY_ERR

#define ATA_SE_PARITY_ERR   0x00100000

Definition at line 419 of file bsmaster.h.

◆ ATA_SE_PHY_CHANGED

#define ATA_SE_PHY_CHANGED   0x00010000

Definition at line 415 of file bsmaster.h.

◆ ATA_SE_PHY_IERROR

#define ATA_SE_PHY_IERROR   0x00020000

Definition at line 416 of file bsmaster.h.

◆ ATA_SE_PROT_ERR

#define ATA_SE_PROT_ERR   0x00000400

Definition at line 413 of file bsmaster.h.

◆ ATA_SE_TRANSPORT_ERR

#define ATA_SE_TRANSPORT_ERR   0x01000000

Definition at line 423 of file bsmaster.h.

◆ ATA_SE_UNKNOWN_FIS

#define ATA_SE_UNKNOWN_FIS   0x02000000

Definition at line 424 of file bsmaster.h.

◆ ATA_SS_DET_DEV_PRESENT

#define ATA_SS_DET_DEV_PRESENT   0x00000001

Definition at line 311 of file bsmaster.h.

◆ ATA_SS_DET_MASK

#define ATA_SS_DET_MASK   0x0000000f

Definition at line 309 of file bsmaster.h.

◆ ATA_SS_DET_NO_DEVICE

#define ATA_SS_DET_NO_DEVICE   0x00000000

Definition at line 310 of file bsmaster.h.

◆ ATA_SS_DET_PHY_OFFLINE

#define ATA_SS_DET_PHY_OFFLINE   0x00000004

Definition at line 313 of file bsmaster.h.

◆ ATA_SS_DET_PHY_ONLINE

#define ATA_SS_DET_PHY_ONLINE   0x00000003

Definition at line 312 of file bsmaster.h.

◆ ATA_SS_IPM_ACTIVE

#define ATA_SS_IPM_ACTIVE   0x00000100

Definition at line 322 of file bsmaster.h.

◆ ATA_SS_IPM_MASK

#define ATA_SS_IPM_MASK   0x00000f00

Definition at line 320 of file bsmaster.h.

◆ ATA_SS_IPM_NO_DEVICE

#define ATA_SS_IPM_NO_DEVICE   0x00000000

Definition at line 321 of file bsmaster.h.

◆ ATA_SS_IPM_PARTIAL

#define ATA_SS_IPM_PARTIAL   0x00000200

Definition at line 323 of file bsmaster.h.

◆ ATA_SS_IPM_SLUMBER

#define ATA_SS_IPM_SLUMBER   0x00000600

Definition at line 324 of file bsmaster.h.

◆ ATA_SS_SPD_GEN1

#define ATA_SS_SPD_GEN1   0x00000010

Definition at line 317 of file bsmaster.h.

◆ ATA_SS_SPD_GEN2

#define ATA_SS_SPD_GEN2   0x00000020

Definition at line 318 of file bsmaster.h.

◆ ATA_SS_SPD_MASK

#define ATA_SS_SPD_MASK   0x000000f0

Definition at line 315 of file bsmaster.h.

◆ ATA_SS_SPD_NO_SPEED

#define ATA_SS_SPD_NO_SPEED   0x00000000

Definition at line 316 of file bsmaster.h.

◆ ATA_WAIT_BASE_READY

#define ATA_WAIT_BASE_READY   0x8

Definition at line 62 of file bsmaster.h.

◆ ATA_WAIT_IDLE

#define ATA_WAIT_IDLE   0x9

Definition at line 63 of file bsmaster.h.

◆ ATA_WAIT_INTR

#define ATA_WAIT_INTR   0x2

Definition at line 56 of file bsmaster.h.

◆ ATA_WAIT_READY

#define ATA_WAIT_READY   0x3

Definition at line 57 of file bsmaster.h.

◆ ATAPI_MAGIC_LSB

#define ATAPI_MAGIC_LSB   0x14

Definition at line 105 of file bsmaster.h.

◆ ATAPI_MAGIC_MSB

#define ATAPI_MAGIC_MSB   0xeb

Definition at line 106 of file bsmaster.h.

◆ AtapiVirtToPhysAddr

#define AtapiVirtToPhysAddr (   hwde,
  srb,
  phaddr,
  plen,
  phaddru 
)     AtapiVirtToPhysAddr_(hwde, srb, phaddr, plen, phaddru);

Definition at line 1716 of file bsmaster.h.

◆ BM_COMMAND_READ

#define BM_COMMAND_READ   0x08

Definition at line 154 of file bsmaster.h.

◆ BM_COMMAND_START_STOP

#define BM_COMMAND_START_STOP   0x01

Definition at line 150 of file bsmaster.h.

◆ BM_COMMAND_WRITE

#define BM_COMMAND_WRITE   0x00

Definition at line 153 of file bsmaster.h.

◆ BM_DS0_SII_DMA_COMPLETE

#define BM_DS0_SII_DMA_COMPLETE   (1 << 18) /* cmd complete / IRQ pending */

Definition at line 160 of file bsmaster.h.

◆ BM_DS0_SII_DMA_ENABLE

#define BM_DS0_SII_DMA_ENABLE   (1 << 0) /* DMA run switch */

Definition at line 156 of file bsmaster.h.

◆ BM_DS0_SII_DMA_ERROR

#define BM_DS0_SII_DMA_ERROR   (1 << 17) /* PCI bus error */

Definition at line 159 of file bsmaster.h.

◆ BM_DS0_SII_DMA_SATA_IRQ

#define BM_DS0_SII_DMA_SATA_IRQ   (1 << 4) /* OR of all SATA IRQs */

Definition at line 158 of file bsmaster.h.

◆ BM_DS0_SII_IRQ

#define BM_DS0_SII_IRQ   (1 << 3) /* ??? */

Definition at line 157 of file bsmaster.h.

◆ BM_STATUS_ACTIVE

#define BM_STATUS_ACTIVE   0x01

Definition at line 142 of file bsmaster.h.

◆ BM_STATUS_DRIVE_0_DMA

#define BM_STATUS_DRIVE_0_DMA   0x20

Definition at line 146 of file bsmaster.h.

◆ BM_STATUS_DRIVE_1_DMA

#define BM_STATUS_DRIVE_1_DMA   0x40

Definition at line 147 of file bsmaster.h.

◆ BM_STATUS_ERR

#define BM_STATUS_ERR   0x02

Definition at line 143 of file bsmaster.h.

◆ BM_STATUS_INTR

#define BM_STATUS_INTR   0x04

Definition at line 144 of file bsmaster.h.

◆ BM_STATUS_MASK

#define BM_STATUS_MASK   0x07

Definition at line 145 of file bsmaster.h.

◆ BM_STATUS_SIMPLEX_ONLY

#define BM_STATUS_SIMPLEX_ONLY   0x80

Definition at line 148 of file bsmaster.h.

◆ ChangePciConfig1

#define ChangePciConfig1 (   offs,
  _op 
)
Value:
{ \
UCHAR a = 0; \
GetPciConfig1(offs, a); \
a = (UCHAR)(_op); \
SetPciConfig1(offs, a); \
}
a
GLboolean GLboolean GLboolean GLboolean a
Definition: glext.h:6204
UCHAR
unsigned char UCHAR
Definition: xmlstorage.h:181

Definition at line 1641 of file bsmaster.h.

◆ ChangePciConfig2

#define ChangePciConfig2 (   offs,
  _op 
)
Value:
{ \
USHORT a = 0; \
GetPciConfig2(offs, a); \
a = (USHORT)(_op); \
SetPciConfig2(offs, a); \
}
USHORT
unsigned short USHORT
Definition: pedump.c:61

Definition at line 1670 of file bsmaster.h.

◆ ChangePciConfig4

#define ChangePciConfig4 (   offs,
  _op 
)
Value:
{ \
ULONG a = 0; \
GetPciConfig4(offs, a); \
a = _op; \
SetPciConfig4(offs, a); \
}
ULONG
uint32_t ULONG
Definition: typedefs.h:59

Definition at line 1699 of file bsmaster.h.

◆ CHECK_INTR_ACTIVE

#define CHECK_INTR_ACTIVE   0x03

Definition at line 1066 of file bsmaster.h.

◆ CHECK_INTR_CHECK

#define CHECK_INTR_CHECK   0x01

Definition at line 1068 of file bsmaster.h.

◆ CHECK_INTR_DETECTED

#define CHECK_INTR_DETECTED   0x02

Definition at line 1067 of file bsmaster.h.

◆ CHECK_INTR_IDLE

#define CHECK_INTR_IDLE   0x00

Definition at line 1069 of file bsmaster.h.

◆ CMD_ACTION_ALL

#define CMD_ACTION_ALL   (CMD_ACTION_PREPARE | CMD_ACTION_EXEC)

Definition at line 976 of file bsmaster.h.

◆ CMD_ACTION_EXEC

#define CMD_ACTION_EXEC   0x02

Definition at line 975 of file bsmaster.h.

◆ CMD_ACTION_PREPARE

#define CMD_ACTION_PREPARE   0x01

Definition at line 974 of file bsmaster.h.

◆ CTRFLAGS_AHCI_PM

#define CTRFLAGS_AHCI_PM   0x0400

Definition at line 1143 of file bsmaster.h.

◆ CTRFLAGS_AHCI_PM2

#define CTRFLAGS_AHCI_PM2   0x0800

Definition at line 1144 of file bsmaster.h.

◆ CTRFLAGS_DMA_ACTIVE

#define CTRFLAGS_DMA_ACTIVE   0x0001

Definition at line 1131 of file bsmaster.h.

◆ CTRFLAGS_DMA_OPERATION

#define CTRFLAGS_DMA_OPERATION   0x0004

Definition at line 1133 of file bsmaster.h.

◆ CTRFLAGS_DMA_RO

#define CTRFLAGS_DMA_RO   0x0002

Definition at line 1132 of file bsmaster.h.

◆ CTRFLAGS_DPC_REQ

#define CTRFLAGS_DPC_REQ   0x0010

Definition at line 1135 of file bsmaster.h.

◆ CTRFLAGS_DSC_BSY

#define CTRFLAGS_DSC_BSY   0x0080

Definition at line 1138 of file bsmaster.h.

◆ CTRFLAGS_ENABLE_INTR_REQ

#define CTRFLAGS_ENABLE_INTR_REQ   0x0020

Definition at line 1136 of file bsmaster.h.

◆ CTRFLAGS_INTR_DISABLED

#define CTRFLAGS_INTR_DISABLED   0x0008

Definition at line 1134 of file bsmaster.h.

◆ CTRFLAGS_LBA48

#define CTRFLAGS_LBA48   0x0040

Definition at line 1137 of file bsmaster.h.

◆ CTRFLAGS_NO_SLAVE

#define CTRFLAGS_NO_SLAVE   0x0100

Definition at line 1139 of file bsmaster.h.

◆ CTRFLAGS_PERMANENT

#define CTRFLAGS_PERMANENT   (CTRFLAGS_DMA_RO | CTRFLAGS_NO_SLAVE)

Definition at line 1146 of file bsmaster.h.

◆ DEV_BSIZE

#define DEV_BSIZE   512

Definition at line 103 of file bsmaster.h.

◆ DMA_MODE_AHCI

#define DMA_MODE_AHCI   0x02

Definition at line 1708 of file bsmaster.h.

◆ DMA_MODE_BM

#define DMA_MODE_BM   0x01

Definition at line 1707 of file bsmaster.h.

◆ DMA_MODE_NONE

#define DMA_MODE_NONE   0x00

Definition at line 1706 of file bsmaster.h.

◆ DPC_STATE_COMPLETE

#define DPC_STATE_COMPLETE   0x40

Definition at line 1158 of file bsmaster.h.

◆ DPC_STATE_DPC

#define DPC_STATE_DPC   0x20

Definition at line 1156 of file bsmaster.h.

◆ DPC_STATE_ISR

#define DPC_STATE_ISR   0x10

Definition at line 1155 of file bsmaster.h.

◆ DPC_STATE_NONE

#define DPC_STATE_NONE   0x00

Definition at line 1154 of file bsmaster.h.

◆ DPC_STATE_TIMER

#define DPC_STATE_TIMER   0x30

Definition at line 1157 of file bsmaster.h.

◆ GEOM_AUTO

#define GEOM_AUTO   0xffffffff

Definition at line 1148 of file bsmaster.h.

◆ GEOM_MANUAL

#define GEOM_MANUAL   0x0003

Definition at line 1152 of file bsmaster.h.

◆ GEOM_ORIG

#define GEOM_ORIG   0x0002

Definition at line 1151 of file bsmaster.h.

◆ GEOM_STD

#define GEOM_STD   0x0000

Definition at line 1149 of file bsmaster.h.

◆ GEOM_UNIATA

#define GEOM_UNIATA   0x0001

Definition at line 1150 of file bsmaster.h.

◆ GET_CDEV

#define GET_CDEV (   Srb)    (Srb->TargetId)

Definition at line 1850 of file bsmaster.h.

◆ GET_CHANNEL

#define GET_CHANNEL (   Srb)    (Srb->PathId)

Definition at line 1847 of file bsmaster.h.

◆ GetDmaStatus

#define GetDmaStatus (   de,
  c 
)     (((de)->BusMaster == DMA_MODE_BM) ? AtapiReadPort1(&((de)->chan[c]), IDX_BM_Status) : 0)

Definition at line 1711 of file bsmaster.h.

◆ GetPciConfig1

#define GetPciConfig1 (   offs,
  op 
)
Value:
{ \
ScsiPortGetBusDataByOffset(HwDeviceExtension, \
PCIConfiguration, \
SystemIoBusNumber, \
slotNumber, \
&op, \
offs, \
1); \
}
op
UINT op
Definition: effect.c:236
PCIConfiguration
@ PCIConfiguration
Definition: miniport.h:93

Definition at line 1620 of file bsmaster.h.

◆ GetPciConfig2

#define GetPciConfig2 (   offs,
  op 
)
Value:
{ \
ScsiPortGetBusDataByOffset(HwDeviceExtension, \
PCIConfiguration, \
SystemIoBusNumber, \
slotNumber, \
&op, \
offs, \
2); \
}

Definition at line 1649 of file bsmaster.h.

◆ GetPciConfig4

#define GetPciConfig4 (   offs,
  op 
)
Value:
{ \
ScsiPortGetBusDataByOffset(HwDeviceExtension, \
PCIConfiguration, \
SystemIoBusNumber, \
slotNumber, \
&op, \
offs, \
4); \
}

Definition at line 1678 of file bsmaster.h.

◆ HBAFLAGS_DMA_DISABLED

#define HBAFLAGS_DMA_DISABLED   0x01

Definition at line 1358 of file bsmaster.h.

◆ HBAFLAGS_DMA_DISABLED_LBA48

#define HBAFLAGS_DMA_DISABLED_LBA48   0x02

Definition at line 1359 of file bsmaster.h.

◆ IDX_AHCI_BOHC

#define IDX_AHCI_BOHC   (FIELD_OFFSET(IDE_AHCI_REGISTERS, BOHC))

Definition at line 276 of file bsmaster.h.

◆ IDX_AHCI_CAP

#define IDX_AHCI_CAP   (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP))

Definition at line 270 of file bsmaster.h.

◆ IDX_AHCI_CAP2

#define IDX_AHCI_CAP2   (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP2))

Definition at line 275 of file bsmaster.h.

◆ IDX_AHCI_GHC

#define IDX_AHCI_GHC   (FIELD_OFFSET(IDE_AHCI_REGISTERS, GHC))

Definition at line 271 of file bsmaster.h.

◆ IDX_AHCI_IS

#define IDX_AHCI_IS   (FIELD_OFFSET(IDE_AHCI_REGISTERS, IS))

Definition at line 272 of file bsmaster.h.

◆ IDX_AHCI_o_BlockCount

#define IDX_AHCI_o_BlockCount   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockCount))

Definition at line 791 of file bsmaster.h.

◆ IDX_AHCI_o_BlockCountExp

#define IDX_AHCI_o_BlockCountExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockCountExp))

Definition at line 797 of file bsmaster.h.

◆ IDX_AHCI_o_BlockNumber

#define IDX_AHCI_o_BlockNumber   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockNumber ))

Definition at line 787 of file bsmaster.h.

◆ IDX_AHCI_o_BlockNumberExp

#define IDX_AHCI_o_BlockNumberExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockNumberExp ))

Definition at line 794 of file bsmaster.h.

◆ IDX_AHCI_o_Command

#define IDX_AHCI_o_Command   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Command))

Definition at line 785 of file bsmaster.h.

◆ IDX_AHCI_o_Control

#define IDX_AHCI_o_Control   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Control))

Definition at line 792 of file bsmaster.h.

◆ IDX_AHCI_o_CylinderHigh

#define IDX_AHCI_o_CylinderHigh   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderHigh))

Definition at line 789 of file bsmaster.h.

◆ IDX_AHCI_o_CylinderHighExp

#define IDX_AHCI_o_CylinderHighExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderHighExp))

Definition at line 796 of file bsmaster.h.

◆ IDX_AHCI_o_CylinderLow

#define IDX_AHCI_o_CylinderLow   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderLow ))

Definition at line 788 of file bsmaster.h.

◆ IDX_AHCI_o_CylinderLowExp

#define IDX_AHCI_o_CylinderLowExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderLowExp ))

Definition at line 795 of file bsmaster.h.

◆ IDX_AHCI_o_DriveSelect

#define IDX_AHCI_o_DriveSelect   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, DriveSelect ))

Definition at line 790 of file bsmaster.h.

◆ IDX_AHCI_o_Feature

#define IDX_AHCI_o_Feature   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Feature))

Definition at line 786 of file bsmaster.h.

◆ IDX_AHCI_o_FeatureExp

#define IDX_AHCI_o_FeatureExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, FeatureExp))

Definition at line 793 of file bsmaster.h.

◆ IDX_AHCI_P_ACT

#define IDX_AHCI_P_ACT   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SACT))

Definition at line 693 of file bsmaster.h.

◆ IDX_AHCI_P_CI

#define IDX_AHCI_P_CI   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CI))

Definition at line 686 of file bsmaster.h.

◆ IDX_AHCI_P_CLB

#define IDX_AHCI_P_CLB   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CLB))

Definition at line 682 of file bsmaster.h.

◆ IDX_AHCI_P_CMD

#define IDX_AHCI_P_CMD   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CMD))

Definition at line 689 of file bsmaster.h.

◆ IDX_AHCI_P_FB

#define IDX_AHCI_P_FB   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, FB))

Definition at line 683 of file bsmaster.h.

◆ IDX_AHCI_P_IE

#define IDX_AHCI_P_IE   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IE))

Definition at line 685 of file bsmaster.h.

◆ IDX_AHCI_P_IS

#define IDX_AHCI_P_IS   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IS))

Definition at line 684 of file bsmaster.h.

◆ IDX_AHCI_P_SControl

#define IDX_AHCI_P_SControl   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SControl))

Definition at line 691 of file bsmaster.h.

◆ IDX_AHCI_P_SError

#define IDX_AHCI_P_SError   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SError))

Definition at line 692 of file bsmaster.h.

◆ IDX_AHCI_P_SIG

#define IDX_AHCI_P_SIG   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SIG))

Definition at line 688 of file bsmaster.h.

◆ IDX_AHCI_P_SNTF

#define IDX_AHCI_P_SNTF   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SNTF))

Definition at line 695 of file bsmaster.h.

◆ IDX_AHCI_P_SStatus

#define IDX_AHCI_P_SStatus   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SStatus))

Definition at line 690 of file bsmaster.h.

◆ IDX_AHCI_P_TFD

#define IDX_AHCI_P_TFD   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, TFD))

Definition at line 687 of file bsmaster.h.

◆ IDX_AHCI_PI

#define IDX_AHCI_PI   (FIELD_OFFSET(IDE_AHCI_REGISTERS, PI))

Definition at line 274 of file bsmaster.h.

◆ IDX_AHCI_VS

#define IDX_AHCI_VS   (FIELD_OFFSET(IDE_AHCI_REGISTERS, VS))

Definition at line 273 of file bsmaster.h.

◆ IDX_BM_Command

#define IDX_BM_Command   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Command )+IDX_BM_IO)

Definition at line 167 of file bsmaster.h.

◆ IDX_BM_DeviceSpecific0

#define IDX_BM_DeviceSpecific0   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific0)+IDX_BM_IO)

Definition at line 168 of file bsmaster.h.

◆ IDX_BM_DeviceSpecific1

#define IDX_BM_DeviceSpecific1   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific1)+IDX_BM_IO)

Definition at line 170 of file bsmaster.h.

◆ IDX_BM_IO

#define IDX_BM_IO   (IDX_IO2_o+IDX_IO2_o_SZ)

Definition at line 163 of file bsmaster.h.

◆ IDX_BM_IO_SZ

#define IDX_BM_IO_SZ   5

Definition at line 165 of file bsmaster.h.

◆ IDX_BM_PRD_Table

#define IDX_BM_PRD_Table   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, PRD_Table )+IDX_BM_IO)

Definition at line 171 of file bsmaster.h.

◆ IDX_BM_Status

#define IDX_BM_Status   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Status )+IDX_BM_IO)

Definition at line 169 of file bsmaster.h.

◆ IDX_INDEXED_ADDR

#define IDX_INDEXED_ADDR   (0+IDX_INDEXED_IO)

Definition at line 466 of file bsmaster.h.

◆ IDX_INDEXED_DATA

#define IDX_INDEXED_DATA   (1+IDX_INDEXED_IO)

Definition at line 467 of file bsmaster.h.

◆ IDX_INDEXED_IO

#define IDX_INDEXED_IO   (IDX_SATA_IO+IDX_SATA_IO_SZ)

Definition at line 463 of file bsmaster.h.

◆ IDX_INDEXED_IO_SZ

#define IDX_INDEXED_IO_SZ   2

Definition at line 464 of file bsmaster.h.

◆ IDX_MAX_REG

#define IDX_MAX_REG   (IDX_INDEXED_IO+IDX_INDEXED_IO_SZ)

Definition at line 469 of file bsmaster.h.

◆ IDX_SATA_IO

#define IDX_SATA_IO   (IDX_BM_IO+IDX_BM_IO_SZ)

Definition at line 453 of file bsmaster.h.

◆ IDX_SATA_IO_SZ

#define IDX_SATA_IO_SZ   5

Definition at line 455 of file bsmaster.h.

◆ IDX_SATA_SActive

#define IDX_SATA_SActive   (3+IDX_SATA_IO)

Definition at line 460 of file bsmaster.h.

◆ IDX_SATA_SControl

#define IDX_SATA_SControl   (2+IDX_SATA_IO)

Definition at line 459 of file bsmaster.h.

◆ IDX_SATA_SError

#define IDX_SATA_SError   (1+IDX_SATA_IO)

Definition at line 458 of file bsmaster.h.

◆ IDX_SATA_SNTF_PMN

#define IDX_SATA_SNTF_PMN   (4+IDX_SATA_IO)

Definition at line 461 of file bsmaster.h.

◆ IDX_SATA_SStatus

#define IDX_SATA_SStatus   (0+IDX_SATA_IO)

Definition at line 457 of file bsmaster.h.

◆ IO_FLOPPY_INT

#define IO_FLOPPY_INT   0x3F6 /* AltStatus inside Floppy I/O range */

Definition at line 81 of file bsmaster.h.

◆ IO_WD1

#define IO_WD1   0x1F0 /* Primary Fixed Disk Controller */

Definition at line 78 of file bsmaster.h.

◆ IO_WD2

#define IO_WD2   0x170 /* Secondary Fixed Disk Controller */

Definition at line 79 of file bsmaster.h.

◆ IP_PC98_BANK

#define IP_PC98_BANK   0x432

Definition at line 80 of file bsmaster.h.

◆ IsBusMaster

#define IsBusMaster (   pciData)
Value:
( ((pciData)->Command & (PCI_ENABLE_BUS_MASTER/* | PCI_ENABLE_IO_SPACE*/)) == \
(PCI_ENABLE_BUS_MASTER/* | PCI_ENABLE_IO_SPACE*/))
Command
Definition: shell.h:41
PCI_ENABLE_BUS_MASTER
#define PCI_ENABLE_BUS_MASTER
Definition: iotypes.h:3618

Definition at line 853 of file bsmaster.h.

◆ IsMasterDev

#define IsMasterDev (   pciData)
Value:
( ((pciData)->ProgIf & 0x80) && \
((pciData)->ProgIf & PCI_IDE_PROGIF_NATIVE_ALL) != PCI_IDE_PROGIF_NATIVE_ALL )
PCI_IDE_PROGIF_NATIVE_ALL
#define PCI_IDE_PROGIF_NATIVE_ALL
Definition: bsmaster.h:859

Definition at line 861 of file bsmaster.h.

◆ MAX_RETRIES

#define MAX_RETRIES   6

Definition at line 72 of file bsmaster.h.

◆ MIN_REQ_TTL

#define MIN_REQ_TTL   4

Definition at line 866 of file bsmaster.h.

◆ PCI_ADDRESS_IOMASK

#define PCI_ADDRESS_IOMASK   0xfffffff0

Definition at line 83 of file bsmaster.h.

◆ PCI_DEV_CLASS_STORAGE

#define PCI_DEV_CLASS_STORAGE   0x01

Definition at line 117 of file bsmaster.h.

◆ PCI_DEV_PROGIF_AHCI_1_0

#define PCI_DEV_PROGIF_AHCI_1_0   0x01

Definition at line 124 of file bsmaster.h.

◆ PCI_DEV_SUBCLASS_ATA

#define PCI_DEV_SUBCLASS_ATA   0x05

Definition at line 121 of file bsmaster.h.

◆ PCI_DEV_SUBCLASS_IDE

#define PCI_DEV_SUBCLASS_IDE   0x01

Definition at line 119 of file bsmaster.h.

◆ PCI_DEV_SUBCLASS_RAID

#define PCI_DEV_SUBCLASS_RAID   0x04

Definition at line 120 of file bsmaster.h.

◆ PCI_DEV_SUBCLASS_SATA

#define PCI_DEV_SUBCLASS_SATA   0x06

Definition at line 122 of file bsmaster.h.

◆ PCI_IDE_PROGIF_NATIVE_1

#define PCI_IDE_PROGIF_NATIVE_1   0x01

Definition at line 857 of file bsmaster.h.

◆ PCI_IDE_PROGIF_NATIVE_2

#define PCI_IDE_PROGIF_NATIVE_2   0x04

Definition at line 858 of file bsmaster.h.

◆ PCI_IDE_PROGIF_NATIVE_ALL

#define PCI_IDE_PROGIF_NATIVE_ALL   0x05

Definition at line 859 of file bsmaster.h.

◆ PCIBUSNUM_NOT_SPECIFIED

#define PCIBUSNUM_NOT_SPECIFIED   (0xffffffffL)

Definition at line 1451 of file bsmaster.h.

◆ PCISLOTNUM_NOT_SPECIFIED

#define PCISLOTNUM_NOT_SPECIFIED   (0xffffffffL)

Definition at line 1452 of file bsmaster.h.

◆ REORDER_COST_DENIED

#define REORDER_COST_DENIED   (REORDER_COST_MAX - 3)

Definition at line 982 of file bsmaster.h.

◆ REORDER_COST_INTERSECT

#define REORDER_COST_INTERSECT   (REORDER_COST_MAX - 2)

Definition at line 981 of file bsmaster.h.

◆ REORDER_COST_MAX

#define REORDER_COST_MAX   ((DEF_I64(0x1) << 60) - 1)

Definition at line 979 of file bsmaster.h.

◆ REORDER_COST_RESELECT

#define REORDER_COST_RESELECT   (REORDER_COST_MAX/4)

Definition at line 983 of file bsmaster.h.

◆ REORDER_COST_SWITCH_RW_CD

#define REORDER_COST_SWITCH_RW_CD   (REORDER_COST_MAX/8)

Definition at line 985 of file bsmaster.h.

◆ REORDER_COST_SWITCH_RW_HDD

#define REORDER_COST_SWITCH_RW_HDD   (0)

Definition at line 989 of file bsmaster.h.

◆ REORDER_COST_TTL

#define REORDER_COST_TTL   (REORDER_COST_MAX - 1)

Definition at line 980 of file bsmaster.h.

◆ REORDER_MCOST_SEEK_BACK_CD

#define REORDER_MCOST_SEEK_BACK_CD   (16)

Definition at line 987 of file bsmaster.h.

◆ REORDER_MCOST_SEEK_BACK_HDD

#define REORDER_MCOST_SEEK_BACK_HDD   (2)

Definition at line 991 of file bsmaster.h.

◆ REORDER_MCOST_SWITCH_RW_CD

#define REORDER_MCOST_SWITCH_RW_CD   (0)

Definition at line 986 of file bsmaster.h.

◆ REORDER_MCOST_SWITCH_RW_HDD

#define REORDER_MCOST_SWITCH_RW_HDD   (4)

Definition at line 990 of file bsmaster.h.

◆ REQ_FLAG_DMA_DBUF

#define REQ_FLAG_DMA_DBUF   0x20

Definition at line 938 of file bsmaster.h.

◆ REQ_FLAG_DMA_DBUF_PRD

#define REQ_FLAG_DMA_DBUF_PRD   0x40

Definition at line 939 of file bsmaster.h.

◆ REQ_FLAG_DMA_OPERATION

#define REQ_FLAG_DMA_OPERATION   0x02

Definition at line 932 of file bsmaster.h.

◆ REQ_FLAG_FORCE_DOWNRATE

#define REQ_FLAG_FORCE_DOWNRATE   0x01

Definition at line 931 of file bsmaster.h.

◆ REQ_FLAG_FORCE_DOWNRATE_LBA48

#define REQ_FLAG_FORCE_DOWNRATE_LBA48   0x10

Definition at line 937 of file bsmaster.h.

◆ REQ_FLAG_LBA48

#define REQ_FLAG_LBA48   0x80

Definition at line 940 of file bsmaster.h.

◆ REQ_FLAG_READ

#define REQ_FLAG_READ   0x08

Definition at line 935 of file bsmaster.h.

◆ REQ_FLAG_REORDERABLE_CMD

#define REQ_FLAG_REORDERABLE_CMD   0x04

Definition at line 933 of file bsmaster.h.

◆ REQ_FLAG_RW_MASK

#define REQ_FLAG_RW_MASK   0x08

Definition at line 934 of file bsmaster.h.

◆ REQ_FLAG_WRITE

#define REQ_FLAG_WRITE   0x00

Definition at line 936 of file bsmaster.h.

◆ REQ_STATE_ATAPI_DO_NOTHING_INTR

#define REQ_STATE_ATAPI_DO_NOTHING_INTR   0x44

Definition at line 954 of file bsmaster.h.

◆ REQ_STATE_ATAPI_EXPECTING_CMD_INTR

#define REQ_STATE_ATAPI_EXPECTING_CMD_INTR   0x41

Definition at line 951 of file bsmaster.h.

◆ REQ_STATE_ATAPI_EXPECTING_DATA_INTR

#define REQ_STATE_ATAPI_EXPECTING_DATA_INTR   0x42

Definition at line 952 of file bsmaster.h.

◆ REQ_STATE_ATAPI_EXPECTING_DATA_INTR2

#define REQ_STATE_ATAPI_EXPECTING_DATA_INTR2   0x43

Definition at line 953 of file bsmaster.h.

◆ REQ_STATE_DPC_COMPLETE_REQ

#define REQ_STATE_DPC_COMPLETE_REQ   0x53

Definition at line 962 of file bsmaster.h.

◆ REQ_STATE_DPC_INTR_REQ

#define REQ_STATE_DPC_INTR_REQ   0x51

Definition at line 960 of file bsmaster.h.

◆ REQ_STATE_DPC_RESET_REQ

#define REQ_STATE_DPC_RESET_REQ   0x52

Definition at line 961 of file bsmaster.h.

◆ REQ_STATE_DPC_WAIT_BUSY

#define REQ_STATE_DPC_WAIT_BUSY   0x59

Definition at line 966 of file bsmaster.h.

◆ REQ_STATE_DPC_WAIT_BUSY0

#define REQ_STATE_DPC_WAIT_BUSY0   0x57

Definition at line 964 of file bsmaster.h.

◆ REQ_STATE_DPC_WAIT_BUSY1

#define REQ_STATE_DPC_WAIT_BUSY1   0x58

Definition at line 965 of file bsmaster.h.

◆ REQ_STATE_DPC_WAIT_DRQ

#define REQ_STATE_DPC_WAIT_DRQ   0x5a

Definition at line 967 of file bsmaster.h.

◆ REQ_STATE_DPC_WAIT_DRQ0

#define REQ_STATE_DPC_WAIT_DRQ0   0x5b

Definition at line 968 of file bsmaster.h.

◆ REQ_STATE_DPC_WAIT_DRQ_ERR

#define REQ_STATE_DPC_WAIT_DRQ_ERR   0x5c

Definition at line 969 of file bsmaster.h.

◆ REQ_STATE_EARLY_INTR

#define REQ_STATE_EARLY_INTR   0x48

Definition at line 956 of file bsmaster.h.

◆ REQ_STATE_EXPECTING_INTR

#define REQ_STATE_EXPECTING_INTR   0x40

Definition at line 950 of file bsmaster.h.

◆ REQ_STATE_NONE

#define REQ_STATE_NONE   0x00

Definition at line 943 of file bsmaster.h.

◆ REQ_STATE_PREPARE_TO_NEXT

#define REQ_STATE_PREPARE_TO_NEXT   0x21

Definition at line 947 of file bsmaster.h.

◆ REQ_STATE_PREPARE_TO_TRANSFER

#define REQ_STATE_PREPARE_TO_TRANSFER   0x20

Definition at line 946 of file bsmaster.h.

◆ REQ_STATE_PROCESSING_INTR

#define REQ_STATE_PROCESSING_INTR   0x50

Definition at line 958 of file bsmaster.h.

◆ REQ_STATE_QUEUED

#define REQ_STATE_QUEUED   0x10

Definition at line 944 of file bsmaster.h.

◆ REQ_STATE_READY_TO_TRANSFER

#define REQ_STATE_READY_TO_TRANSFER   0x30

Definition at line 948 of file bsmaster.h.

◆ REQ_STATE_TRANSFER_COMPLETE

#define REQ_STATE_TRANSFER_COMPLETE   0x7f

Definition at line 971 of file bsmaster.h.

◆ RETRY_PIO

#define RETRY_PIO   3

Definition at line 75 of file bsmaster.h.

◆ RETRY_UDMA2

#define RETRY_UDMA2   1

Definition at line 73 of file bsmaster.h.

◆ RETRY_WDMA

#define RETRY_WDMA   2

Definition at line 74 of file bsmaster.h.

◆ SATA_CMD_ICC_Active

#define SATA_CMD_ICC_Active   0x01

Definition at line 602 of file bsmaster.h.

◆ SATA_CMD_ICC_Idle

#define SATA_CMD_ICC_Idle   0x00

Definition at line 600 of file bsmaster.h.

◆ SATA_CMD_ICC_NoOp

#define SATA_CMD_ICC_NoOp   0x00

Definition at line 601 of file bsmaster.h.

◆ SATA_CMD_ICC_Partial

#define SATA_CMD_ICC_Partial   0x02

Definition at line 603 of file bsmaster.h.

◆ SATA_CMD_ICC_Slumber

#define SATA_CMD_ICC_Slumber   0x06

Definition at line 604 of file bsmaster.h.

◆ SATA_MAX_PM_UNITS

#define SATA_MAX_PM_UNITS   16

Definition at line 110 of file bsmaster.h.

◆ SControl_DET_Disable

#define SControl_DET_Disable   0x04

Definition at line 334 of file bsmaster.h.

◆ SControl_DET_DoNothing

#define SControl_DET_DoNothing   0x00

Definition at line 331 of file bsmaster.h.

◆ SControl_DET_Idle

#define SControl_DET_Idle   0x00

Definition at line 332 of file bsmaster.h.

◆ SControl_DET_Init

#define SControl_DET_Init   0x01

Definition at line 333 of file bsmaster.h.

◆ SControl_IPM_NoPartial

#define SControl_IPM_NoPartial   0x01

Definition at line 346 of file bsmaster.h.

◆ SControl_IPM_NoPartialSlumber

#define SControl_IPM_NoPartialSlumber   0x03

Definition at line 348 of file bsmaster.h.

◆ SControl_IPM_NoRestrict

#define SControl_IPM_NoRestrict   0x00

Definition at line 345 of file bsmaster.h.

◆ SControl_IPM_NoSlumber

#define SControl_IPM_NoSlumber   0x02

Definition at line 347 of file bsmaster.h.

◆ SControl_SPD_LimGen1

#define SControl_SPD_LimGen1   0x01

Definition at line 339 of file bsmaster.h.

◆ SControl_SPD_LimGen2

#define SControl_SPD_LimGen2   0x02

Definition at line 340 of file bsmaster.h.

◆ SControl_SPD_LimGen3

#define SControl_SPD_LimGen3   0x03

Definition at line 341 of file bsmaster.h.

◆ SControl_SPD_NoRestrict

#define SControl_SPD_NoRestrict   0x00

Definition at line 338 of file bsmaster.h.

◆ SetPciConfig1

#define SetPciConfig1 (   offs,
  op 
)
Value:
{ \
UCHAR _a = op; \
ScsiPortSetBusDataByOffset(HwDeviceExtension, \
PCIConfiguration, \
SystemIoBusNumber, \
slotNumber, \
&_a, \
offs, \
1); \
}

Definition at line 1630 of file bsmaster.h.

◆ SetPciConfig2

#define SetPciConfig2 (   offs,
  op 
)
Value:
{ \
USHORT _a = op; \
ScsiPortSetBusDataByOffset(HwDeviceExtension, \
PCIConfiguration, \
SystemIoBusNumber, \
slotNumber, \
&_a, \
offs, \
2); \
}

Definition at line 1659 of file bsmaster.h.

◆ SetPciConfig4

#define SetPciConfig4 (   offs,
  op 
)
Value:
{ \
ULONG _a = op; \
ScsiPortSetBusDataByOffset(HwDeviceExtension, \
PCIConfiguration, \
SystemIoBusNumber, \
slotNumber, \
&_a, \
offs, \
4); \
}

Definition at line 1688 of file bsmaster.h.

◆ SStatus_DET_Dev_NoPhy

#define SStatus_DET_Dev_NoPhy   0x01

Definition at line 285 of file bsmaster.h.

◆ SStatus_DET_Dev_Ok

#define SStatus_DET_Dev_Ok   0x03

Definition at line 286 of file bsmaster.h.

◆ SStatus_DET_NoDev

#define SStatus_DET_NoDev   0x00

Definition at line 284 of file bsmaster.h.

◆ SStatus_DET_Offline

#define SStatus_DET_Offline   0x04

Definition at line 287 of file bsmaster.h.

◆ SStatus_IPM_Active

#define SStatus_IPM_Active   0x01

Definition at line 299 of file bsmaster.h.

◆ SStatus_IPM_NoDev

#define SStatus_IPM_NoDev   0x00

Definition at line 298 of file bsmaster.h.

◆ SStatus_IPM_Partial

#define SStatus_IPM_Partial   0x02

Definition at line 300 of file bsmaster.h.

◆ SStatus_IPM_Slumber

#define SStatus_IPM_Slumber   0x06

Definition at line 301 of file bsmaster.h.

◆ SStatus_SPD_Gen1

#define SStatus_SPD_Gen1   0x01

Definition at line 292 of file bsmaster.h.

◆ SStatus_SPD_Gen2

#define SStatus_SPD_Gen2   0x02

Definition at line 293 of file bsmaster.h.

◆ SStatus_SPD_Gen3

#define SStatus_SPD_Gen3   0x03

Definition at line 294 of file bsmaster.h.

◆ SStatus_SPD_NoDev

#define SStatus_SPD_NoDev   0x00

Definition at line 291 of file bsmaster.h.

◆ UNIATA_ALLOCATE_NEW_LUNS

#define UNIATA_ALLOCATE_NEW_LUNS   0x00

Definition at line 1398 of file bsmaster.h.

◆ VM_AUTO

#define VM_AUTO   0x00

Definition at line 1901 of file bsmaster.h.

◆ VM_BOCHS

#define VM_BOCHS   0x05

Definition at line 1906 of file bsmaster.h.

◆ VM_MAX_KNOWN

#define VM_MAX_KNOWN   VM_PCEM

Definition at line 1909 of file bsmaster.h.

◆ VM_NONE

#define VM_NONE   0x01

Definition at line 1902 of file bsmaster.h.

◆ VM_PCEM

#define VM_PCEM   0x06

Definition at line 1907 of file bsmaster.h.

◆ VM_QEMU

#define VM_QEMU   0x04

Definition at line 1905 of file bsmaster.h.

◆ VM_VBOX

#define VM_VBOX   0x02

Definition at line 1903 of file bsmaster.h.

◆ VM_VMWARE

#define VM_VMWARE   0x03

Definition at line 1904 of file bsmaster.h.

Typedef Documentation

◆ AHCI_ATA_H2D_FIS

typedef struct _AHCI_ATA_H2D_FIS AHCI_ATA_H2D_FIS

◆ AHCI_IS_REG

typedef union _AHCI_IS_REG AHCI_IS_REG

◆ ATA_REQ

typedef union _ATA_REQ ATA_REQ

◆ BM_DMA_ENTRY

typedef struct BM_DMA_ENTRY BM_DMA_ENTRY

◆ BUSMASTER_CTX

typedef struct _BUSMASTER_CTX BUSMASTER_CTX

◆ HW_CHANNEL

typedef struct _HW_CHANNEL HW_CHANNEL

◆ HW_DEVICE_EXTENSION

typedef struct _HW_DEVICE_EXTENSION HW_DEVICE_EXTENSION

◆ HW_LU_EXTENSION

typedef struct _HW_LU_EXTENSION HW_LU_EXTENSION

◆ IDE_AHCI_CHANNEL_CTL_BLOCK

typedef struct _IDE_AHCI_CHANNEL_CTL_BLOCK IDE_AHCI_CHANNEL_CTL_BLOCK

◆ IDE_AHCI_CMD

typedef struct _IDE_AHCI_CMD IDE_AHCI_CMD

◆ IDE_AHCI_CMD_LIST

typedef struct _IDE_AHCI_CMD_LIST IDE_AHCI_CMD_LIST

◆ IDE_AHCI_PORT_REGISTERS

typedef struct _IDE_AHCI_PORT_REGISTERS IDE_AHCI_PORT_REGISTERS

◆ IDE_AHCI_PRD_ENTRY

typedef struct _IDE_AHCI_PRD_ENTRY IDE_AHCI_PRD_ENTRY

◆ IDE_AHCI_RCV_FIS

typedef struct _IDE_AHCI_RCV_FIS IDE_AHCI_RCV_FIS

◆ IDE_AHCI_REGISTERS

typedef struct _IDE_AHCI_REGISTERS IDE_AHCI_REGISTERS

◆ IDE_BUSMASTER_REGISTERS

typedef struct _IDE_BUSMASTER_REGISTERS IDE_BUSMASTER_REGISTERS

◆ IDE_SATA_REGISTERS

typedef struct _IDE_SATA_REGISTERS IDE_SATA_REGISTERS

◆ IORES

typedef struct _IORES IORES

◆ ISR2_DEVICE_EXTENSION

typedef struct _ISR2_DEVICE_EXTENSION ISR2_DEVICE_EXTENSION

◆ PAHCI_ATA_H2D_FIS

typedef struct _AHCI_ATA_H2D_FIS * PAHCI_ATA_H2D_FIS

◆ PAHCI_IS_REG

typedef union _AHCI_IS_REG * PAHCI_IS_REG

◆ PATA_REQ

typedef union _ATA_REQ * PATA_REQ

◆ PBM_DMA_ENTRY

typedef struct BM_DMA_ENTRY * PBM_DMA_ENTRY

◆ PBUSMASTER_CTX

typedef struct _BUSMASTER_CTX * PBUSMASTER_CTX

◆ PCIIDE_DEVICE_EXTENSION

typedef ISR2_DEVICE_EXTENSION PCIIDE_DEVICE_EXTENSION

Definition at line 1355 of file bsmaster.h.

◆ PHW_CHANNEL

typedef struct _HW_CHANNEL * PHW_CHANNEL

◆ PHW_DEVICE_EXTENSION

typedef struct _HW_DEVICE_EXTENSION * PHW_DEVICE_EXTENSION

◆ PHW_LU_EXTENSION

typedef struct _HW_LU_EXTENSION * PHW_LU_EXTENSION

◆ PIDE_AHCI_CHANNEL_CTL_BLOCK

typedef struct _IDE_AHCI_CHANNEL_CTL_BLOCK * PIDE_AHCI_CHANNEL_CTL_BLOCK

◆ PIDE_AHCI_CMD

typedef struct _IDE_AHCI_CMD * PIDE_AHCI_CMD

◆ PIDE_AHCI_CMD_LIST

typedef struct _IDE_AHCI_CMD_LIST * PIDE_AHCI_CMD_LIST

◆ PIDE_AHCI_PORT_REGISTERS

typedef struct _IDE_AHCI_PORT_REGISTERS * PIDE_AHCI_PORT_REGISTERS

◆ PIDE_AHCI_PRD_ENTRY

typedef struct _IDE_AHCI_PRD_ENTRY * PIDE_AHCI_PRD_ENTRY

◆ PIDE_AHCI_RCV_FIS

typedef struct _IDE_AHCI_RCV_FIS * PIDE_AHCI_RCV_FIS

◆ PIDE_AHCI_REGISTERS

typedef struct _IDE_AHCI_REGISTERS * PIDE_AHCI_REGISTERS

◆ PIDE_BUSMASTER_REGISTERS

typedef struct _IDE_BUSMASTER_REGISTERS * PIDE_BUSMASTER_REGISTERS

◆ PIDE_SATA_REGISTERS

typedef struct _IDE_SATA_REGISTERS * PIDE_SATA_REGISTERS

◆ PIORES

typedef struct _IORES * PIORES

◆ PISR2_DEVICE_EXTENSION

typedef struct _ISR2_DEVICE_EXTENSION * PISR2_DEVICE_EXTENSION

◆ PPCIIDE_DEVICE_EXTENSION

typedef PISR2_DEVICE_EXTENSION PPCIIDE_DEVICE_EXTENSION

Definition at line 1356 of file bsmaster.h.

◆ PSATA_SCONTROL_REG

typedef union _SATA_SCONTROL_REG * PSATA_SCONTROL_REG

◆ PSATA_SERROR_REG

typedef union _SATA_SERROR_REG * PSATA_SERROR_REG

◆ PSATA_SSTATUS_REG

typedef union _SATA_SSTATUS_REG * PSATA_SSTATUS_REG

◆ SATA_SCONTROL_REG

typedef union _SATA_SCONTROL_REG SATA_SCONTROL_REG

◆ SATA_SERROR_REG

typedef union _SATA_SERROR_REG SATA_SERROR_REG

◆ SATA_SSTATUS_REG

typedef union _SATA_SSTATUS_REG SATA_SSTATUS_REG

Function Documentation

◆ AtapiChipInit()

BOOLEAN NTAPI AtapiChipInit ( IN PVOID  HwDeviceExtension,
IN ULONG  DeviceNumber,
IN ULONG  c 
)

Definition at line 1879 of file id_init.cpp.

1884{
1885 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
1886 ULONG slotNumber = deviceExtension->slotNumber;
1887 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
1888 ULONG VendorID = deviceExtension->DevID & 0xffff;
1889 ULONG DeviceID = (deviceExtension->DevID >> 16) & 0xffff;
1890 ULONG RevID = deviceExtension->RevID;
1891// ULONG i;
1892// BUSMASTER_CONTROLLER_INFORMATION_BASE* DevTypeInfo;
1893 ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
1894 ULONG ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
1895 PHW_CHANNEL chan;
1896 UCHAR tmp8;
1897 USHORT tmp16;
1898 ULONG tmp32;
1899 ULONG c; // logical channel (for Compatible Mode controllers)
1900 BOOLEAN CheckCable = FALSE;
1901 BOOLEAN GlobalInit = FALSE;
1902 //ULONG BaseIoAddress;
1903
1904 switch(channel) {
1905 case CHAN_NOT_SPECIFIED_CHECK_CABLE:
1906 CheckCable = TRUE;
1907 /* FALLTHROUGH */
1908 case CHAN_NOT_SPECIFIED:
1909 c = CHAN_NOT_SPECIFIED;
1910 GlobalInit = TRUE;
1911 break;
1912 default:
1913 //c = channel - deviceExtension->Channel; // logical channel (for Compatible Mode controllers)
1914 c = channel;
1915 channel += deviceExtension->Channel;
1916 }
1917
1918 KdPrint2((PRINT_PREFIX "AtapiChipInit: dev %#x, ph chan %d, c %d\n", DeviceNumber, channel, c));
1919
1920 KdPrint2((PRINT_PREFIX "HwFlags: %#x\n", deviceExtension->HwFlags));
1921 KdPrint2((PRINT_PREFIX "VendorID/DeviceID/Rev %#x/%#x/%#x\n", VendorID, DeviceID, RevID));
1922
1923 if(deviceExtension->UnknownDev) {
1924 KdPrint2((PRINT_PREFIX " Unknown chip\n" ));
1925 //return TRUE;
1926 VendorID = 0xffffffff;
1927 }
1928
1929
1930 if(ChipFlags & UNIATA_AHCI) {
1931 /* if BAR(5) is IO it should point to SATA interface registers */
1932 if(!deviceExtension->BaseIoAHCI_0.Addr) {
1933 KdPrint2((PRINT_PREFIX " !BaseIoAHCI_0, exiting\n" ));
1934 return FALSE;
1935 }
1936 if(c == CHAN_NOT_SPECIFIED) {
1937 return UniataAhciInit(HwDeviceExtension);
1938 } else
1939 if(c<deviceExtension->NumberChannels) {
1940 KdPrint2((PRINT_PREFIX " AHCI single channel init\n" ));
1941 UniataAhciReset(HwDeviceExtension, c);
1942 return TRUE;
1943 } else {
1944 KdPrint2((PRINT_PREFIX " AHCI non-existent channel\n" ));
1945 return FALSE;
1946 }
1947 }
1948
1949 if((WinVer_Id() > WinVer_NT) &&
1950 GlobalInit &&
1951 deviceExtension->MasterDev) {
1952 PCI_COMMON_CONFIG pciData;
1953 ULONG busDataRead;
1954
1955 KdPrint2((PRINT_PREFIX " re-enable IO resources of MasterDev\n" ));
1956
1957 busDataRead = HalGetBusData
1958 //ScsiPortGetBusData
1959 (
1960 //HwDeviceExtension,
1961 PCIConfiguration, SystemIoBusNumber, slotNumber,
1962 &pciData, PCI_COMMON_HDR_LENGTH);
1963 if(busDataRead == PCI_COMMON_HDR_LENGTH) {
1964 UniataEnableIoPCI(SystemIoBusNumber, slotNumber, &pciData);
1965 } else {
1966 KdPrint2((PRINT_PREFIX " re-enable IO resources of MasterDev FAILED\n" ));
1967 }
1968 }
1969
1970 switch(VendorID) {
1971// case ATA_ACARD_ID:
1972// break;
1973 case ATA_ACER_LABS_ID:
1974 if(ChipFlags & UNIATA_SATA) {
1975 if(c == CHAN_NOT_SPECIFIED) {
1976 for(c=0; c<deviceExtension->NumberChannels; c++) {
1977 chan = &deviceExtension->chan[c];
1978 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
1979 /* the southbridge might need the data corruption fix */
1980 if(RevID == 0xc2 || RevID == 0xc3) {
1981 AtapiAliSouthBridgeFixup(HwDeviceExtension, PCIConfiguration,
1982 SystemIoBusNumber, slotNumber, c);
1983 }
1984 }
1985 /* enable PCI interrupt */
1986 ChangePciConfig2(offsetof(PCI_COMMON_CONFIG, Command), (a & ~0x0400));
1987 }
1988 } else
1989 if(ChipFlags & ALINEW) {
1990 if(c == CHAN_NOT_SPECIFIED) {
1991 /* use device interrupt as byte count end */
1992 ChangePciConfig1(0x4a, (a | 0x20));
1993 /* enable cable detection and UDMA support on newer chips, rev < 0xc7 */
1994 if(RevID < 0xc7) {
1995 ChangePciConfig1(0x4b, (a | 0x09));
1996 }
1997
1998 /* enable ATAPI UDMA mode */
1999 ChangePciConfig1(0x53, (a | (RevID >= 0xc7 ? 0x03 : 0x01)));
2000
2001 } else {
2002 // check 80-pin cable
2003 generic_cable80(deviceExtension, channel, 0x4a, 0);
2004 }
2005 } else {
2006 if(c == CHAN_NOT_SPECIFIED) {
2007 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
2008 ChangePciConfig1(0x53, (a | 0x03));
2009 } else {
2010 // ATAPI DMA R/O
2011 deviceExtension->chan[c].ChannelCtrlFlags |= CTRFLAGS_DMA_RO;
2012 }
2013 }
2014 break;
2015 case ATA_AMD_ID:
2016 if(c == CHAN_NOT_SPECIFIED) {
2017 /* set prefetch, postwrite */
2018 if(ChipFlags & AMDBUG) {
2019 ChangePciConfig1(0x41, (a & 0x0f));
2020 } else {
2021 ChangePciConfig1(0x41, (a | 0xf0));
2022 }
2023 }
2024 if(deviceExtension->MaxTransferMode < ATA_UDMA2)
2025 break;
2026 // check 80-pin cable
2027 if(!(ChipFlags & UNIATA_NO80CHK)) {
2028 if(c == CHAN_NOT_SPECIFIED) {
2029 // do nothing
2030 } else {
2031 generic_cable80(deviceExtension, channel, 0x42, 0);
2032 }
2033 }
2034 break;
2035 case ATA_HIGHPOINT_ID:
2036
2037 if(c == CHAN_NOT_SPECIFIED) {
2038
2039 if(ChipFlags & HPTOLD) {
2040 /* turn off interrupt prediction */
2041 ChangePciConfig1(0x51, (a & ~0x80));
2042 } else {
2043 /* turn off interrupt prediction */
2044 ChangePciConfig1(0x51, (a & ~0x03));
2045 ChangePciConfig1(0x55, (a & ~0x03));
2046 /* turn on interrupts */
2047 ChangePciConfig1(0x5a, (a & ~0x10));
2048 /* set clocks etc */
2049 if(ChipType < HPT372) {
2050 SetPciConfig1(0x5b, 0x22);
2051 } else {
2052 ChangePciConfig1(0x5b, ((a & 0x01) | 0x20));
2053 }
2054 }
2055
2056 } else {
2057 // check 80-pin cable
2058 chan = &deviceExtension->chan[c];
2059 if(!hpt_cable80(deviceExtension, channel)) {
2060 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2061 }
2062 }
2063 break;
2064 case ATA_INTEL_ID: {
2065 BOOLEAN IsPata;
2066 USHORT reg54;
2067 if(ChipFlags & UNIATA_SATA) {
2068
2069 KdPrint2((PRINT_PREFIX "Intel SATA\n"));
2070 if(ChipFlags & UNIATA_AHCI) {
2071 KdPrint2((PRINT_PREFIX "Do nothing for AHCI\n"));
2072 /* enable PCI interrupt */
2073 ChangePciConfig2(offsetof(PCI_COMMON_CONFIG, Command), (a & ~0x0400));
2074 break;
2075 }
2076 if(c == CHAN_NOT_SPECIFIED) {
2077 KdPrint2((PRINT_PREFIX "Base init\n"));
2078 /* force all ports active "the legacy way" */
2079 ChangePciConfig2(0x92, (a | 0x0f));
2080
2081 if(deviceExtension->BaseIoAddressSATA_0.Addr && (ChipFlags & ICH7)) {
2082 /* Set SCRAE bit to enable registers access. */
2083 ChangePciConfig4(0x94, (a | (1 << 9)));
2084 /* Set Ports Implemented register bits. */
2085 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x0c,
2086 AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x0c) | 0x0f);
2087 }
2088 /* enable PCI interrupt */
2089 ChangePciConfig2(offsetof(PCI_COMMON_CONFIG, Command), (a & ~0x0400));
2090
2091 } else {
2092
2093 KdPrint2((PRINT_PREFIX "channel init\n"));
2094
2095 GetPciConfig1(0x90, tmp8);
2096 KdPrint2((PRINT_PREFIX "reg 90: %x, init lun map\n", tmp8));
2097
2098 KdPrint2((PRINT_PREFIX "chan %d\n", c));
2099 chan = &deviceExtension->chan[c];
2100 IsPata = FALSE;
2101 if(ChipFlags & ICH5) {
2102 KdPrint2((PRINT_PREFIX "ICH5\n"));
2103 if ((tmp8 & 0x04) == 0) {
2104 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
2105 chan->lun[0]->SATA_lun_map = (tmp8 & 0x01) ^ c;
2106 chan->lun[1]->SATA_lun_map = 0;
2107 } else if ((tmp8 & 0x02) == 0) {
2108 if(c == 0) {
2109 chan->lun[0]->SATA_lun_map = (tmp8 & 0x01) ? 1 : 0;
2110 chan->lun[1]->SATA_lun_map = (tmp8 & 0x01) ? 0 : 1;
2111 } else {
2112 IsPata = TRUE;
2113 //chan->ChannelCtrlFlags |= CTRFLAGS_PATA;
2114 }
2115 } else if ((tmp8 & 0x02) != 0) {
2116 if(c == 1) {
2117 chan->lun[0]->SATA_lun_map = (tmp8 & 0x01) ? 1 : 0;
2118 chan->lun[1]->SATA_lun_map = (tmp8 & 0x01) ? 0 : 1;
2119 } else {
2120 IsPata = TRUE;
2121 //chan->ChannelCtrlFlags |= CTRFLAGS_PATA;
2122 }
2123 }
2124 } else
2125 if(ChipFlags & I6CH2) {
2126 KdPrint2((PRINT_PREFIX "I6CH2\n"));
2127 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
2128 chan->lun[0]->SATA_lun_map = c ? 0 : 1;
2129 chan->lun[1]->SATA_lun_map = 0;
2130 } else {
2131 KdPrint2((PRINT_PREFIX "other Intel\n"));
2132 switch(tmp8 & 0x03) {
2133 case 0:
2134 KdPrint2((PRINT_PREFIX "0 -> %d/%d\n", 0+c, 2+c));
2135 chan->lun[0]->SATA_lun_map = 0+c;
2136 chan->lun[1]->SATA_lun_map = 2+c;
2137 break;
2138 case 2:
2139 if(c==0) {
2140 KdPrint2((PRINT_PREFIX "2 -> %d/%d\n", 0, 2));
2141 chan->lun[0]->SATA_lun_map = 0;
2142 chan->lun[1]->SATA_lun_map = 2;
2143 } else {
2144 // PATA
2145 KdPrint2((PRINT_PREFIX "PATA\n"));
2146 IsPata = TRUE;
2147 }
2148 break;
2149 case 1:
2150 if(c==1) {
2151 KdPrint2((PRINT_PREFIX "2 -> %d/%d\n", 1, 3));
2152 chan->lun[0]->SATA_lun_map = 1;
2153 chan->lun[1]->SATA_lun_map = 3;
2154 } else {
2155 // PATA
2156 KdPrint2((PRINT_PREFIX "PATA\n"));
2157 IsPata = TRUE;
2158 }
2159 break;
2160 }
2161 }
2162
2163 if(IsPata) {
2164 KdPrint2((PRINT_PREFIX "PATA part\n"));
2165 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA5);
2166 }
2167
2168 if(ChipType == INTEL_IDX) {
2169 KdPrint2((PRINT_PREFIX "io indexed\n"));
2170 //for(c=0; c<deviceExtension->NumberChannels; c++) {
2171 chan = &deviceExtension->chan[c];
2172 UniataSataWritePort4(chan, IDX_SATA_SError, 0xffffffff, 0);
2173 if(!(chan->ChannelCtrlFlags & CTRFLAGS_NO_SLAVE)) {
2174 UniataSataWritePort4(chan, IDX_SATA_SError, 0xffffffff, 1);
2175 }
2176 //}
2177 }
2178 }
2179
2180 break;
2181 }
2182 if(deviceExtension->MaxTransferMode <= ATA_UDMA2)
2183 break;
2184 // check 80-pin cable
2185 if(c == CHAN_NOT_SPECIFIED) {
2186 // do nothing
2187 } else {
2188 chan = &deviceExtension->chan[c];
2189 GetPciConfig2(0x54, reg54);
2190 KdPrint2((PRINT_PREFIX " intel 80-pin check (reg54=%x)\n", reg54));
2191 if(deviceExtension->HwFlags & UNIATA_NO80CHK) {
2192 KdPrint2((PRINT_PREFIX " No check (administrative)\n"));
2193 if(chan->Force80pin) {
2194 KdPrint2((PRINT_PREFIX "Force80pin\n"));
2195 }
2196 } else
2197 if(reg54 == 0x0000 || reg54 == 0xffff) {
2198 KdPrint2((PRINT_PREFIX " check failed (not supported)\n"));
2199 } else
2200 if( ((reg54 >> (channel*2)) & 30) == 0) {
2201 KdPrint2((PRINT_PREFIX " intel 40-pin\n"));
2202 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2203 }
2204 }
2205 break; }
2206 case ATA_NVIDIA_ID: {
2207 if(ChipFlags & UNIATA_SATA) {
2208 if(c == CHAN_NOT_SPECIFIED) {
2209 ULONG offs = (ChipFlags & NV4OFF) ? 0x0440 : 0x0010;
2210 /* enable control access */
2211 ChangePciConfig1(0x50, (a | 0x04));
2212 /* MCP55 seems to need some time to allow r_res2 read. */
2213 AtapiStallExecution(10);
2214 KdPrint2((PRINT_PREFIX "BaseIoAddressSATA_0=%x\n", deviceExtension->BaseIoAddressSATA_0.Addr));
2215 if(ChipFlags & NVQ) {
2216 KdPrint2((PRINT_PREFIX "Disable NCQ\n"));
2217 tmp32 = AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x0400);
2218 KdPrint2((PRINT_PREFIX "MODE=%#x\n", tmp32));
2219 if(tmp32 & ~0xfffffff9) {
2220 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x0400,
2221 tmp32 & 0xfffffff9);
2222 }
2223 ChipFlags &= ~NVQ;
2224 deviceExtension->HwFlags = ChipFlags;
2225 }
2226 if(ChipFlags & NVQ) {
2227 /* disable ECO 398 */
2228 ChangePciConfig1(0x7f, (a & ~(1 << 7)));
2229
2230 KdPrint2((PRINT_PREFIX "Enable NCQ\n"));
2231 /* enable NCQ support */
2232 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x0400,
2233 tmp32 | ~0x00000006);
2234
2235 /* clear interrupt status */
2236 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs, 0x00ff00ff);
2237 /* enable device and PHY state change interrupts */
2238 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs+4, 0x000d000d);
2239 } else {
2240 /* clear interrupt status */
2241 AtapiWritePortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs, 0xff);
2242 /* enable device and PHY state change interrupts */
2243 AtapiWritePortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs+1, 0xdd);
2244 }
2245 /* enable PCI interrupt */
2246 ChangePciConfig2(offsetof(PCI_COMMON_CONFIG, Command), (a & ~0x0400));
2247 } else {
2248 //UniataSataPhyEnable(HwDeviceExtension, c);
2249 }
2250 } else {
2251 //UCHAR reg52;
2252
2253 if(c == CHAN_NOT_SPECIFIED) {
2254 /* set prefetch, postwrite */
2255 ChangePciConfig1(0x51, (a & 0x0f));
2256 } else {
2257 // check 80-pin cable
2258 generic_cable80(deviceExtension, channel, 0x52, 1);
2259/* chan = &deviceExtension->chan[c];
2260 GetPciConfig1(0x52, reg52);
2261 if( !((reg52 >> (channel*2)) & 0x01)) {
2262 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2263 }*/
2264 }
2265 }
2266 break; }
2267 case ATA_PROMISE_ID: {
2268 USHORT Reg50;
2269 switch(ChipType) {
2270 case PRNEW:
2271 /* setup clocks */
2272 if(c == CHAN_NOT_SPECIFIED) {
2273// ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
2274 AtapiWritePortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11,
2275 AtapiReadPortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11) | 0x0a );
2276 }
2277 /* FALLTHROUGH */
2278 case PROLD:
2279 /* enable burst mode */
2280// ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
2281 if(c == CHAN_NOT_SPECIFIED) {
2282 AtapiWritePortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x1f,
2283 AtapiReadPortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x1f) | 0x01 );
2284 } else {
2285 // check 80-pin cable
2286 chan = &deviceExtension->chan[c];
2287 GetPciConfig2(0x50, Reg50);
2288 if(Reg50 & (1 << (channel+10))) {
2289 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2290 }
2291 }
2292 break;
2293 case PRTX:
2294 if(c == CHAN_NOT_SPECIFIED) {
2295 // do nothing
2296 } else {
2297 // check 80-pin cable
2298 chan = &deviceExtension->chan[c];
2299 AtapiWritePort1(chan, IDX_BM_DeviceSpecific0, 0x0b);
2300 if(AtapiReadPort1(chan, IDX_BM_DeviceSpecific1) & 0x04) {
2301 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2302 }
2303 }
2304 break;
2305 case PRMIO:
2306 if(c == CHAN_NOT_SPECIFIED) {
2307 /* clear SATA status and unmask interrupts */
2308 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),
2309 (ChipFlags & PRG2) ? 0x60 : 0x6c, 0x000000ff);
2310 if(ChipFlags & UNIATA_SATA) {
2311 /* enable "long burst length" on gen2 chips */
2312 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0), 0x44,
2313 AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0), 0x44) | 0x2000);
2314 }
2315 } else {
2316 chan = &deviceExtension->chan[c];
2317 AtapiWritePort4(chan, IDX_BM_Command,
2318 (AtapiReadPort4(chan, IDX_BM_Command) & ~0x00000f8f) | channel );
2319 AtapiWritePort4(chan, IDX_BM_DeviceSpecific0, 0x00000001);
2320 // check 80-pin cable
2321 if(chan->MaxTransferMode < ATA_SA150 &&
2322 (AtapiReadPort4(chan, IDX_BM_Command) & 0x01000000)) {
2323 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2324 }
2325 }
2326 break;
2327 }
2328 break; }
2329 case ATA_SERVERWORKS_ID:
2330 if(c == CHAN_NOT_SPECIFIED) {
2331 if(ChipType == SWKS33) {
2332 AtapiRosbSouthBridgeFixup(HwDeviceExtension, PCIConfiguration,
2333 SystemIoBusNumber, slotNumber);
2334 } else {
2335 ChangePciConfig1(0x5a, ((a & ~0x40) | ((ChipType == SWKS100) ? 0x03 : 0x02)));
2336 }
2337 }
2338 break;
2339 case ATA_ATI_ID:
2340 if(ChipType == SIIMIO) {
2341 KdPrint2((PRINT_PREFIX "ATI New\n"));
2342 // fall to SiI
2343 } else {
2344 KdPrint2((PRINT_PREFIX "ATI\n"));
2345 break;
2346 }
2347 /* FALLTHROUGH */
2348 case ATA_SILICON_IMAGE_ID:
2349 /* if(ChipFlags & SIIENINTR) {
2350 SetPciConfig1(0x71, 0x01);
2351 }*/
2352 switch(ChipType) {
2353 case SIIMIO: {
2354
2355 KdPrint2((PRINT_PREFIX "SII\n"));
2356 USHORT Reg79;
2357
2358 if(c == CHAN_NOT_SPECIFIED) {
2359 if(ChipFlags & SIISETCLK) {
2360 KdPrint2((PRINT_PREFIX "SIISETCLK\n"));
2361 GetPciConfig1(0x8a, tmp8);
2362 if ((tmp8 & 0x30) != 0x10)
2363 ChangePciConfig1(0x8a, (a & 0xcf) | 0x10);
2364 GetPciConfig1(0x8a, tmp8);
2365 if ((tmp8 & 0x30) != 0x10) {
2366 KdPrint2((PRINT_PREFIX "Sil 0680 could not set ATA133 clock\n"));
2367 deviceExtension->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA5);
2368 }
2369 }
2370 }
2371 if(deviceExtension->MaxTransferMode < ATA_SA150) {
2372 // check 80-pin cable
2373 if(c == CHAN_NOT_SPECIFIED) {
2374 // do nothing
2375 } else {
2376 KdPrint2((PRINT_PREFIX "Check UDMA66 cable\n"));
2377 chan = &deviceExtension->chan[c];
2378 GetPciConfig2(0x79, Reg79);
2379 if(Reg79 & (channel ? 0x02 : 0x01)) {
2380 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2381 }
2382 }
2383 } else {
2384 ULONG unit01 = (c & 1);
2385 ULONG unit10 = (c & 2);
2386 /* enable/disable PHY state change interrupt */
2387 if(c == CHAN_NOT_SPECIFIED) {
2388 for(c=0; c<deviceExtension->NumberChannels; c++) {
2389 unit01 = (c & 1);
2390 unit10 = (c & 2);
2391 if(ChipFlags & SIINOSATAIRQ) {
2392 KdPrint2((PRINT_PREFIX "Disable broken SATA intr on c=%x\n", c));
2393 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x148 + (unit01 << 7) + (unit10 << 8),0);
2394 }
2395 }
2396 } else {
2397 if(ChipFlags & SIINOSATAIRQ) {
2398 KdPrint2((PRINT_PREFIX "Disable broken SATA intr on c=%x\n", c));
2399 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x148 + (unit01 << 7) + (unit10 << 8),0);
2400 } else {
2401 KdPrint2((PRINT_PREFIX "Enable SATA intr on c=%x\n", c));
2402 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
2403 }
2404 }
2405 }
2406 if(c == CHAN_NOT_SPECIFIED) {
2407 /* enable interrupt as BIOS might not */
2408 ChangePciConfig1(0x8a, (a & 0x3f));
2409 // Enable 3rd and 4th channels
2410 if (ChipFlags & SII4CH) {
2411 KdPrint2((PRINT_PREFIX "SII4CH\n"));
2412 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x0200, 0x00000002);
2413 }
2414 } else {
2415 chan = &deviceExtension->chan[c];
2416 /* dont block interrupts */
2417 //ChangePciConfig4(0x48, (a & ~0x03c00000));
2418 /*tmp32 =*/ AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x48);
2419 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x48, (1 << 22) << c);
2420 // flush
2421 /*tmp32 =*/ AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x48);
2422
2423 /* Initialize FIFO PCI bus arbitration */
2424 GetPciConfig1(offsetof(PCI_COMMON_CONFIG, CacheLineSize), tmp8);
2425 if(tmp8) {
2426 KdPrint2((PRINT_PREFIX "SII: CacheLine=%d\n", tmp8));
2427 tmp8 = (tmp8/8)+1;
2428 AtapiWritePort2(chan, IDX_BM_DeviceSpecific1, ((USHORT)tmp8) << 8 | tmp8);
2429 } else {
2430 KdPrint2((PRINT_PREFIX "SII: CacheLine=0 !!!\n"));
2431 }
2432 }
2433 break; }
2434
2435 case SIICMD: {
2436
2437 KdPrint2((PRINT_PREFIX "SII_CMD\n"));
2438 if(c == CHAN_NOT_SPECIFIED) {
2439 /* Setup interrupts. */
2440 SetPciConfig1(0x71, 0x01);
2441
2442 /* GetPciConfig1(0x8a, tmp8);
2443 tmp8 &= ~(0x30);
2444 SetPciConfig1(0x71, tmp8);*/
2445
2446 /* Use MEMORY READ LINE for reads.
2447 * NOTE: Although not mentioned in the PCI0646U specs,
2448 * these bits are write only and won't be read
2449 * back as set or not. The PCI0646U2 specs clarify
2450 * this point.
2451 */
2452 /* tmp8 |= 0x02;
2453 SetPciConfig1(0x71, tmp8);
2454 */
2455 /* Set reasonable active/recovery/address-setup values. */
2456 SetPciConfig1(0x53, 0x40);
2457 SetPciConfig1(0x54, 0x3f);
2458 SetPciConfig1(0x55, 0x40);
2459 SetPciConfig1(0x56, 0x3f);
2460 SetPciConfig1(0x57, 0x1c);
2461 SetPciConfig1(0x58, 0x3f);
2462 SetPciConfig1(0x5b, 0x3f);
2463 }
2464
2465 break; }
2466 case ATI700:
2467 KdPrint2((PRINT_PREFIX "ATI700\n"));
2468 if(c == 0 && !(ChipFlags & UNIATA_AHCI)) {
2469 KdPrint2((PRINT_PREFIX "IXP700 PATA\n"));
2470 chan = &deviceExtension->chan[c];
2471 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA5);
2472 }
2473 break;
2474 } /* switch(ChipType) */
2475 break;
2476 case ATA_SIS_ID:
2477 if(c == CHAN_NOT_SPECIFIED) {
2478 switch(ChipType) {
2479 case SIS33:
2480 break;
2481 case SIS66:
2482 case SIS100OLD:
2483 ChangePciConfig1(0x52, (a & ~0x04));
2484 break;
2485 case SIS100NEW:
2486 case SIS133OLD:
2487 ChangePciConfig1(0x49, (a & ~0x01));
2488 break;
2489 case SIS133NEW:
2490 ChangePciConfig2(0x50, (a | 0x0008));
2491 ChangePciConfig2(0x52, (a | 0x0008));
2492 break;
2493 case SISSATA:
2494 ChangePciConfig2(0x04, (a & ~0x0400));
2495 break;
2496 }
2497 }
2498 if(deviceExtension->HwFlags & UNIATA_SATA) {
2499 // do nothing for SATA
2500 } else
2501 if(ChipType == SIS133NEW) {
2502 // check 80-pin cable
2503 if(c == CHAN_NOT_SPECIFIED) {
2504 // do nothing
2505 } else {
2506 chan = &deviceExtension->chan[c];
2507 GetPciConfig2(channel ? 0x52 : 0x50, tmp16);
2508 if(tmp16 & 0x8000) {
2509 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2510 }
2511 }
2512 } else {
2513 // check 80-pin cable
2514 if(c == CHAN_NOT_SPECIFIED) {
2515 // do nothing
2516 } else {
2517 chan = &deviceExtension->chan[c];
2518 GetPciConfig1(48, tmp8);
2519 if(tmp8 & (0x10 << channel)) {
2520 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2521 }
2522 }
2523 }
2524 break;
2525 case ATA_VIA_ID:
2526
2527/* if(ChipFlags & (UNIATA_SATA | UNIATA_AHCI | VIASATA) {
2528 break;
2529 }*/
2530 if(c == CHAN_NOT_SPECIFIED) {
2531 /* prepare for ATA-66 on the 82C686a and 82C596b */
2532 if(ChipFlags & VIACLK) {
2533 ChangePciConfig4(0x50, (a | 0x030b030b));
2534 }
2535 // no init for SATA
2536 if(ChipFlags & (UNIATA_SATA | VIASATA)) {
2537 /* enable PCI interrupt */
2538 ChangePciConfig2(offsetof(PCI_COMMON_CONFIG, Command), (a & ~0x0400));
2539
2540 /*
2541 * vt6420/1 has problems talking to some drives. The following
2542 * is based on the fix from Joseph Chan <JosephChan@via.com.tw>.
2543 *
2544 * When host issues HOLD, device may send up to 20DW of data
2545 * before acknowledging it with HOLDA and the host should be
2546 * able to buffer them in FIFO. Unfortunately, some WD drives
2547 * send upto 40DW before acknowledging HOLD and, in the
2548 * default configuration, this ends up overflowing vt6421's
2549 * FIFO, making the controller abort the transaction with
2550 * R_ERR.
2551 *
2552 * Rx52[2] is the internal 128DW FIFO Flow control watermark
2553 * adjusting mechanism enable bit and the default value 0
2554 * means host will issue HOLD to device when the left FIFO
2555 * size goes below 32DW. Setting it to 1 makes the watermark
2556 * 64DW.
2557 *
2558 * https://jira.reactos.org/browse/CORE-5897
2559 */
2560
2561 if(DeviceID == 0x3149 || DeviceID == 0x3249) { //vt6420 or vt6421
2562 KdPrint2((PRINT_PREFIX "VIA 642x FIFO\n"));
2563 ChangePciConfig1(0x52, a | (1 << 2));
2564 }
2565
2566 break;
2567 }
2568
2569 /* the southbridge might need the data corruption fix */
2570 if(ChipFlags & VIABUG) {
2571 AtapiViaSouthBridgeFixup(HwDeviceExtension, PCIConfiguration,
2572 SystemIoBusNumber, slotNumber);
2573 }
2574 /* set prefetch, postwrite */
2575 if(ChipType != VIA133) {
2576 ChangePciConfig1(0x41, (a | 0xf0));
2577 }
2578
2579 /* set fifo configuration half'n'half */
2580 ChangePciConfig1(0x43, ((a & ((ChipFlags & VIAPRQ) ? 0x80 : 0x90)) | 0x2a));
2581
2582 /* set status register read retry */
2583 ChangePciConfig1(0x44, (a | 0x08));
2584
2585 /* set DMA read & end-of-sector fifo flush */
2586 ChangePciConfig1(0x46, ((a & 0x0c) | 0xf0));
2587
2588 /* set sector size */
2589 SetPciConfig2(0x60, DEV_BSIZE);
2590 SetPciConfig2(0x68, DEV_BSIZE);
2591 } else {
2592
2593 chan = &deviceExtension->chan[c];
2594 // no init for SATA
2595 if(ChipFlags & (UNIATA_SATA | VIASATA)) {
2596 if((ChipFlags & VIABAR) && (c >= 2)) {
2597 // this is PATA channel
2598 chan->MaxTransferMode = ATA_UDMA5;
2599 break;
2600 }
2601 UniataSataWritePort4(chan, IDX_SATA_SError, 0xffffffff, 0);
2602 break;
2603 }
2604/*
2605 // check 80-pin cable
2606 if(!via_cable80(deviceExtension, channel)) {
2607 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2608 }
2609*/
2610 }
2611
2612 break;
2613
2614 case ATA_ITE_ID:
2615 if(ChipType == ITE_33 || ChipType == ITE_133_NEW) {
2616 break;
2617 }
2618 if(ChipType == ITE_133) {
2619 if(c == CHAN_NOT_SPECIFIED) {
2620 /* set PCI mode and 66Mhz reference clock */
2621 ChangePciConfig1(0x50, a & ~0x83);
2622
2623 /* set default active & recover timings */
2624 SetPciConfig1(0x54, 0x31);
2625 SetPciConfig1(0x56, 0x31);
2626 } else {
2627 // check 80-pin cable
2628 GetPciConfig2(0x40, tmp16);
2629 chan = &deviceExtension->chan[c];
2630 if(!(tmp16 & (channel ? 0x08 : 0x04))) {
2631 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2632 }
2633 }
2634 } else
2635 if(ChipType == ITE_133_NEW) {
2636 }
2637 break;
2638 case ATA_CYRIX_ID:
2639 KdPrint2((PRINT_PREFIX "Cyrix\n"));
2640 if(ChipType == CYRIX_OLD) {
2641 if(c == CHAN_NOT_SPECIFIED) {
2642 GetPciConfig1(0x60, tmp8);
2643 if(!(tmp8 & 0x40)) {
2644 KdPrint2((PRINT_PREFIX "Enable DMA\n"));
2645 tmp8 |= 0x40;
2646 SetPciConfig1(0x60, tmp8);
2647 }
2648 }
2649 }
2650 break;
2651 case ATA_JMICRON_ID:
2652 /* New JMicron PATA controllers */
2653 if(deviceExtension->DevID == ATA_JMB361 ||
2654 deviceExtension->DevID == ATA_JMB363 ||
2655 deviceExtension->DevID == ATA_JMB365 ||
2656 deviceExtension->DevID == ATA_JMB366 ||
2657 deviceExtension->DevID == ATA_JMB368) {
2658 KdPrint2((PRINT_PREFIX "JMicron\n"));
2659
2660 ULONG c_swp = 0;
2661 ULONG reg40, reg80;
2662
2663 GetPciConfig4(0x40, reg40);
2664 KdPrint2((PRINT_PREFIX "reg 40: %x\n", reg40));
2665
2666 c_swp = (reg40 & (1<<22)) ? 1 : 0; // 1=swap, 0=keep
2667 KdPrint2((PRINT_PREFIX "c_swp: %x\n", c_swp));
2668
2669 GetPciConfig4(0x80, reg80);
2670 KdPrint2((PRINT_PREFIX "reg 80: %x\n", reg80));
2671
2672 if(c == CHAN_NOT_SPECIFIED) {
2673 UCHAR P1mode;
2674
2675 P1mode = (reg80 & (1<<24)) ? ATA_UDMA6 : ATA_SA300;
2676 KdPrint2((PRINT_PREFIX "p1 mode: %x\n", P1mode));
2677
2678 if(reg40 & (1 << 23)) {
2679 KdPrint2((PRINT_PREFIX "SATA+PATA0\n"));
2680 deviceExtension->chan[0 ^ c_swp].MaxTransferMode = P1mode;
2681 deviceExtension->chan[1 ^ c_swp].MaxTransferMode = ATA_UDMA6;
2682 deviceExtension->chan[1 ^ c_swp].ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
2683
2684 } else {
2685 KdPrint2((PRINT_PREFIX "SATA+SATA\n"));
2686 deviceExtension->chan[0 ^ c_swp].MaxTransferMode = P1mode;
2687 //deviceExtension->chan[0 ^ c_swp].ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
2688 deviceExtension->chan[1 ^ c_swp].MaxTransferMode = ATA_SA300;
2689 deviceExtension->chan[1 ^ c_swp].ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
2690 }
2691
2692 } else {
2693 /*
2694 deviceExtension->chan[0 ^ c_swp].lun[0]->SATA_lun_map =
2695 deviceExtension->chan[0 ^ c_swp].lun[0]->SATA_lun_map = 0;
2696 deviceExtension->chan[1 ^ c_swp].lun[0]->SATA_lun_map =
2697 deviceExtension->chan[1 ^ c_swp].lun[0]->SATA_lun_map = 1;
2698 */
2699 KdPrint2((PRINT_PREFIX "chan %d\n", c));
2700 chan = &deviceExtension->chan[c];
2701
2702 UCHAR ph_channel = (UCHAR)(c ^ c_swp);
2703 //c_swp = chan->lun[0]->SATA_lun_map;
2704 if(chan->MaxTransferMode >= ATA_SA150) {
2705 KdPrint2((PRINT_PREFIX "SATA, map -> %x\n", ph_channel));
2706 } else {
2707 KdPrint2((PRINT_PREFIX "PATA, map -> %x\n", ph_channel));
2708 if(!ph_channel) {
2709 if(!(reg40 & (1<<5))) {
2710 KdPrint2((PRINT_PREFIX "disabled\n", ph_channel));
2711 } else
2712 if(!(reg40 & (1<<3))) {
2713 KdPrint2((PRINT_PREFIX "40-pin\n"));
2714 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2715 }
2716 } else {
2717 if(!(reg80 & (1<<21))) {
2718 KdPrint2((PRINT_PREFIX "disabled\n", ph_channel));
2719 } else
2720 if(!(reg80 & (1<<19))) {
2721 KdPrint2((PRINT_PREFIX "40-pin\n"));
2722 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2723 }
2724 }
2725 }
2726 }
2727
2728 }
2729 break;
2730 default:
2731 if(c != CHAN_NOT_SPECIFIED) {
2732 // We don't know how to check for 80-pin cable on unknown controllers.
2733 // Later we shall check bit in IDENTIFY structure, but it is not reliable way.
2734 // So, leave this flag to use as hint in error recovery procedures
2735 KdPrint2((PRINT_PREFIX "UNIATA_NO80CHK\n"));
2736 deviceExtension->HwFlags |= UNIATA_NO80CHK;
2737 }
2738 break;
2739 }
2740
2741 // In all places separate channels are inited after common controller init
2742 // The only exception is probe. But there we may need info about 40/80 pin and MaxTransferRate
2743 // Do not check UNIATA_SATA here since we may have controller with mixed ports
2744 if(CheckCable && !(ChipFlags & (UNIATA_NO80CHK/* | UNIATA_SATA*/))) {
2745 for(c=0; c<deviceExtension->NumberChannels; c++) {
2746 AtapiChipInit(HwDeviceExtension, DeviceNumber, c);
2747 }
2748 }
2749
2750 return TRUE;
2751} // end AtapiChipInit()
BOOLEAN
unsigned char BOOLEAN
Definition: ProcessorBind.h:185
PHW_DEVICE_EXTENSION
struct _HW_DEVICE_EXTENSION * PHW_DEVICE_EXTENSION
UNIATA_NO80CHK
#define UNIATA_NO80CHK
Definition: bm_devs_decl.h:630
ITE_33
#define ITE_33
Definition: bm_devs_decl.h:722
ATA_JMB366
#define ATA_JMB366
Definition: bm_devs_decl.h:324
SISSATA
#define SISSATA
Definition: bm_devs_decl.h:676
ATA_INTEL_ID
#define ATA_INTEL_ID
Definition: bm_devs_decl.h:184
ATA_CYRIX_ID
#define ATA_CYRIX_ID
Definition: bm_devs_decl.h:168
NV4OFF
#define NV4OFF
Definition: bm_devs_decl.h:697
ALINEW
#define ALINEW
Definition: bm_devs_decl.h:637
SIS33
#define SIS33
Definition: bm_devs_decl.h:682
ATI700
#define ATI700
Definition: bm_devs_decl.h:666
VIABAR
#define VIABAR
Definition: bm_devs_decl.h:709
PRNEW
#define PRNEW
Definition: bm_devs_decl.h:646
ICH5
#define ICH5
Definition: bm_devs_decl.h:691
HPT372
#define HPT372
Definition: bm_devs_decl.h:641
SIS133NEW
#define SIS133NEW
Definition: bm_devs_decl.h:677
NVQ
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Definition: bm_devs_decl.h:698
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#define ITE_133
Definition: bm_devs_decl.h:723
PRTX
#define PRTX
Definition: bm_devs_decl.h:647
SIINOSATAIRQ
#define SIINOSATAIRQ
Definition: bm_devs_decl.h:673
CHIPTYPE_MASK
#define CHIPTYPE_MASK
Definition: bm_devs_decl.h:620
SIS100OLD
#define SIS100OLD
Definition: bm_devs_decl.h:680
SIIMIO
#define SIIMIO
Definition: bm_devs_decl.h:665
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#define UNIATA_SATA
Definition: bm_devs_decl.h:626
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#define PRG2
Definition: bm_devs_decl.h:654
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#define HPTOLD
Definition: bm_devs_decl.h:643
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#define SWKS33
Definition: bm_devs_decl.h:658
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#define UNIATA_AHCI
Definition: bm_devs_decl.h:629
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#define SIS100NEW
Definition: bm_devs_decl.h:679
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#define ATA_JMB365
Definition: bm_devs_decl.h:323
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#define PROLD
Definition: bm_devs_decl.h:645
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#define ATA_PROMISE_ID
Definition: bm_devs_decl.h:454
ATA_VIA_ID
#define ATA_VIA_ID
Definition: bm_devs_decl.h:571
VIAPRQ
#define VIAPRQ
Definition: bm_devs_decl.h:714
ATA_AMD_ID
#define ATA_AMD_ID
Definition: bm_devs_decl.h:129
PRMIO
#define PRMIO
Definition: bm_devs_decl.h:648
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#define VIASATA
Definition: bm_devs_decl.h:715
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#define SIS66
Definition: bm_devs_decl.h:681
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#define CYRIX_OLD
Definition: bm_devs_decl.h:717
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Definition: bm_devs_decl.h:325
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#define ATA_SIS_ID
Definition: bm_devs_decl.h:521
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#define I6CH2
Definition: bm_devs_decl.h:693
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#define VIACLK
Definition: bm_devs_decl.h:710
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#define ATA_NVIDIA_ID
Definition: bm_devs_decl.h:355
ATA_ATI_ID
#define ATA_ATI_ID
Definition: bm_devs_decl.h:147
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#define ATA_JMB361
Definition: bm_devs_decl.h:320
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#define SIICMD
Definition: bm_devs_decl.h:664
ICH7
#define ICH7
Definition: bm_devs_decl.h:695
ATA_JMB363
#define ATA_JMB363
Definition: bm_devs_decl.h:322
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#define VIA133
Definition: bm_devs_decl.h:705
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#define SII4CH
Definition: bm_devs_decl.h:670
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#define SWKS100
Definition: bm_devs_decl.h:660
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#define ITE_133_NEW
Definition: bm_devs_decl.h:724
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#define ATA_HIGHPOINT_ID
Definition: bm_devs_decl.h:177
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#define SIISETCLK
Definition: bm_devs_decl.h:671
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#define CHIPFLAG_MASK
Definition: bm_devs_decl.h:621
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#define ATA_SILICON_IMAGE_ID
Definition: bm_devs_decl.h:507
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#define AMDBUG
Definition: bm_devs_decl.h:708
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#define VIABUG
Definition: bm_devs_decl.h:711
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#define ATA_JMICRON_ID
Definition: bm_devs_decl.h:318
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#define ATA_SERVERWORKS_ID
Definition: bm_devs_decl.h:494
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#define SIS133OLD
Definition: bm_devs_decl.h:678
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#define ATA_ITE_ID
Definition: bm_devs_decl.h:604
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#define ATA_ACER_LABS_ID
Definition: bm_devs_decl.h:120
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#define INTEL_IDX
Definition: bm_devs_decl.h:688
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VOID DDKFASTAPI AtapiWritePortEx1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN UCHAR data)
ChangePciConfig1
#define ChangePciConfig1(offs, _op)
Definition: bsmaster.h:1641
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#define IDX_BM_DeviceSpecific1
Definition: bsmaster.h:170
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#define ChangePciConfig4(offs, _op)
Definition: bsmaster.h:1699
IDX_BM_DeviceSpecific0
#define IDX_BM_DeviceSpecific0
Definition: bsmaster.h:168
AtapiReadPort1
UCHAR DDKFASTAPI AtapiReadPort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
AtapiReadPort4
ULONG DDKFASTAPI AtapiReadPort4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
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#define GetPciConfig1(offs, op)
Definition: bsmaster.h:1620
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VOID DDKFASTAPI AtapiWritePortEx4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN ULONG data)
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#define ChangePciConfig2(offs, _op)
Definition: bsmaster.h:1670
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ULONG DDKFASTAPI AtapiReadPortEx4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
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#define GetPciConfig4(offs, op)
Definition: bsmaster.h:1678
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#define DEV_BSIZE
Definition: bsmaster.h:103
AtapiWritePort4
VOID DDKFASTAPI AtapiWritePort4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG data)
AtapiWritePort2
VOID DDKFASTAPI AtapiWritePort2(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN USHORT data)
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#define IDX_BM_Command
Definition: bsmaster.h:167
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#define SetPciConfig2(offs, op)
Definition: bsmaster.h:1659
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#define GetPciConfig2(offs, op)
Definition: bsmaster.h:1649
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VOID DDKFASTAPI AtapiWritePort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN UCHAR data)
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#define CTRFLAGS_NO_SLAVE
Definition: bsmaster.h:1139
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#define IDX_SATA_SError
Definition: bsmaster.h:458
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USHORT NTAPI UniataEnableIoPCI(IN ULONG busNumber, IN ULONG slotNumber, IN OUT PPCI_COMMON_CONFIG pciData)
Definition: id_probe.cpp:95
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UCHAR DDKFASTAPI AtapiReadPortEx1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
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#define SetPciConfig1(offs, op)
Definition: bsmaster.h:1630
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#define CTRFLAGS_DMA_RO
Definition: bsmaster.h:1132
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_In_ PCHAR _In_ ULONG DeviceNumber
Definition: classpnp.h:1230
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#define NULL
Definition: types.h:112
TRUE
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Definition: types.h:120
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Definition: types.h:117
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#define ULONGIO_PTR
Definition: config.h:102
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NTHALAPI ULONG NTAPI HalGetBusData(BUS_DATA_TYPE, ULONG, ULONG, PVOID, ULONG)
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#define WinVer_Id()
Definition: CrossNt.h:109
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#define WinVer_NT
Definition: CrossNt.h:112
c
const GLubyte * c
Definition: glext.h:8905
generic_cable80
BOOLEAN NTAPI generic_cable80(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG channel, IN ULONG pci_reg, IN ULONG bit_offs)
Definition: id_init.cpp:1638
hpt_cable80
ULONG NTAPI hpt_cable80(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG channel)
Definition: id_init.cpp:1537
AtapiChipInit
BOOLEAN NTAPI AtapiChipInit(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG channel)
Definition: id_init.cpp:1879
AtapiRosbSouthBridgeFixup
VOID NTAPI AtapiRosbSouthBridgeFixup(IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG SystemIoBusNumber, IN ULONG slotNumber)
Definition: id_init.cpp:1433
AtapiAliSouthBridgeFixup
VOID NTAPI AtapiAliSouthBridgeFixup(IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG SystemIoBusNumber, IN ULONG slotNumber, IN ULONG c)
Definition: id_init.cpp:1485
AtapiViaSouthBridgeFixup
VOID NTAPI AtapiViaSouthBridgeFixup(IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG SystemIoBusNumber, IN ULONG slotNumber)
Definition: id_init.cpp:1368
UniataSataWritePort4
VOID NTAPI UniataSataWritePort4(IN PHW_CHANNEL chan, IN ULONG io_port_ndx, IN ULONG data, IN ULONG pm_port)
Definition: id_sata.cpp:357
UniataAhciReset
VOID NTAPI UniataAhciReset(IN PVOID HwDeviceExtension, IN ULONG lChannel)
Definition: id_sata.cpp:1925
UniataAhciInit
BOOLEAN NTAPI UniataAhciInit(IN PVOID HwDeviceExtension)
Definition: id_sata.cpp:645
c
#define c
Definition: ke_i.h:80
min
#define min(a, b)
Definition: monoChain.cc:55
offsetof
#define offsetof(TYPE, MEMBER)
Definition: sdbstringtable.c:26
_HW_CHANNEL
Definition: bsmaster.h:1019
_HW_CHANNEL::ChannelCtrlFlags
ULONG ChannelCtrlFlags
Definition: bsmaster.h:1059
_HW_CHANNEL::lun
struct _HW_LU_EXTENSION * lun[IDE_MAX_LUN_PER_CHAN]
Definition: bsmaster.h:1088
_HW_CHANNEL::Force80pin
BOOLEAN Force80pin
Definition: bsmaster.h:1048
_HW_CHANNEL::MaxTransferMode
ULONG MaxTransferMode
Definition: bsmaster.h:1057
_HW_DEVICE_EXTENSION
Definition: atapi.c:22
_HW_DEVICE_EXTENSION::UnknownDev
BOOLEAN UnknownDev
Definition: bsmaster.h:1302
_HW_DEVICE_EXTENSION::slotNumber
ULONG slotNumber
Definition: bsmaster.h:1290
_HW_DEVICE_EXTENSION::Channel
ULONG Channel
Definition: bsmaster.h:1296
_HW_DEVICE_EXTENSION::SystemIoBusNumber
ULONG SystemIoBusNumber
Definition: bsmaster.h:1291
_HW_DEVICE_EXTENSION::MasterDev
BOOLEAN MasterDev
Definition: bsmaster.h:1303
_HW_DEVICE_EXTENSION::NumberChannels
ULONG NumberChannels
Definition: atapi.c:68
_HW_DEVICE_EXTENSION::BaseIoAHCI_0
IORES BaseIoAHCI_0
Definition: bsmaster.h:1328
_HW_DEVICE_EXTENSION::RevID
ULONG RevID
Definition: bsmaster.h:1289
_HW_DEVICE_EXTENSION::DevID
ULONG DevID
Definition: bsmaster.h:1288
_HW_DEVICE_EXTENSION::MaxTransferMode
ULONG MaxTransferMode
Definition: bsmaster.h:1313
_HW_DEVICE_EXTENSION::HwFlags
ULONG HwFlags
Definition: bsmaster.h:1314
_HW_DEVICE_EXTENSION::BaseIoAddressBM_0
IORES BaseIoAddressBM_0
Definition: bsmaster.h:1284
_HW_DEVICE_EXTENSION::BaseIoAddressSATA_0
IORES BaseIoAddressSATA_0
Definition: bsmaster.h:1325
_HW_DEVICE_EXTENSION::chan
PHW_CHANNEL chan
Definition: bsmaster.h:1257
_IORES::Addr
ULONG Addr
Definition: bsmaster.h:1009
_PCI_COMMON_CONFIG
Definition: iotypes.h:3588
GlobalInit
static void GlobalInit()
Definition: treelist.c:438
ATA_UDMA2
#define ATA_UDMA2
Definition: atapi.h:330
ATA_SA150
#define ATA_SA150
Definition: atapi.h:337
AtapiStallExecution
#define AtapiStallExecution(dt)
Definition: atapi.h:158
CHAN_NOT_SPECIFIED_CHECK_CABLE
#define CHAN_NOT_SPECIFIED_CHECK_CABLE
Definition: atapi.h:1482
ATA_SA300
#define ATA_SA300
Definition: atapi.h:338
KdPrint2
#define KdPrint2(_x_)
Definition: atapi.h:154
ATA_UDMA6
#define ATA_UDMA6
Definition: atapi.h:334
CHAN_NOT_SPECIFIED
#define CHAN_NOT_SPECIFIED
Definition: atapi.h:1481
ATA_UDMA5
#define ATA_UDMA5
Definition: atapi.h:333
PRINT_PREFIX
#define PRINT_PREFIX
Definition: atapi.h:150
DeviceID
_Must_inspect_result_ _In_ PWDFDEVICE_INIT _In_ PCUNICODE_STRING DeviceID
Definition: wdfpdo.h:278
PCI_COMMON_HDR_LENGTH
#define PCI_COMMON_HDR_LENGTH
Definition: iotypes.h:3594

Referenced by AtapiAdapterControl(), AtapiChipInit(), AtapiFindIsaController(), AtapiHwInitialize(), AtapiHwInitialize__(), and UniataFindBusMasterController().

◆ AtapiDmaAlloc()

VOID NTAPI AtapiDmaAlloc ( IN PVOID  HwDeviceExtension,
IN PPORT_CONFIGURATION_INFORMATION  ConfigInfo,
IN ULONG  lChannel 
)

Definition at line 138 of file id_dma.cpp.

143{
144#ifdef USE_OWN_DMA
145 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
146 PHW_CHANNEL chan = &(deviceExtension->chan[lChannel]);
147 ULONG c = lChannel;
148 ULONG i;
149 ULONG ph_addru;
150
151 deviceExtension->chan[c].CopyDmaBuffer = FALSE;
152
153 if(!deviceExtension->Host64 && (WinVer_Id() > WinVer_NT)) {
154 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: allocate tmp buffers below 4Gb\n"));
155 if(chan->DB_PRD) {
156 KdPrint2((PRINT_PREFIX " already initialized %x\n", chan->DB_PRD));
157 return;
158 }
159 chan->DB_PRD = MmAllocateContiguousMemory(sizeof(((PATA_REQ)NULL)->dma_tab), ph4gb);
160 if(chan->DB_PRD) {
161 chan->DB_PRD_PhAddr = AtapiVirtToPhysAddr(HwDeviceExtension, NULL, (PUCHAR)(chan->DB_PRD), &i, &ph_addru);
162 if(!chan->DB_PRD_PhAddr || !i || ((LONG)(chan->DB_PRD_PhAddr) == -1)) {
163 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No DB PRD BASE\n" ));
164 chan->DB_PRD = NULL;
165 chan->DB_PRD_PhAddr = 0;
166 return;
167 }
168 if(ph_addru) {
169 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No DB PRD below 4Gb\n" ));
170 goto err_1;
171 }
172 }
173 chan->DB_IO = MmAllocateContiguousMemory(deviceExtension->MaximumDmaTransferLength, ph4gb);
174 if(chan->DB_IO) {
175 chan->DB_IO_PhAddr = AtapiVirtToPhysAddr(HwDeviceExtension, NULL, (PUCHAR)(chan->DB_IO), &i, &ph_addru);
176 if(!chan->DB_IO_PhAddr || !i || ((LONG)(chan->DB_IO_PhAddr) == -1)) {
177 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No DB IO BASE\n" ));
178err_1:
179 MmFreeContiguousMemory(chan->DB_PRD);
180 chan->DB_PRD = NULL;
181 chan->DB_PRD_PhAddr = 0;
182 chan->DB_IO = NULL;
183 chan->DB_IO_PhAddr = 0;
184 return;
185 }
186 if(ph_addru) {
187 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No DB IO below 4Gb\n" ));
188 MmFreeContiguousMemory(chan->DB_IO);
189 goto err_1;
190 }
191 }
192 }
193
194
195 if(deviceExtension->HwFlags & UNIATA_AHCI) {
196 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: AHCI\n" ));
197 if(chan->AhciCtlBlock) {
198 KdPrint2((PRINT_PREFIX " already initialized %x\n", chan->AhciCtlBlock));
199 return;
200 }
201 // Need 1K-byte alignment
202 chan->AhciCtlBlock0 = (PIDE_AHCI_CHANNEL_CTL_BLOCK)MmAllocateContiguousMemory(
203 sizeof(IDE_AHCI_CHANNEL_CTL_BLOCK)+AHCI_CLB_ALIGNEMENT_MASK,
204 ph4gb);
205 if(chan->AhciCtlBlock0) {
206 union {
207 PUCHAR AhciCtlBlock;
208 ULONGLONG AhciCtlBlock64;
209 };
210 AhciCtlBlock64 = 0;
211 AhciCtlBlock = (PUCHAR)chan->AhciCtlBlock0;
212
213 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: CLP BASE %I64x\n", AhciCtlBlock64));
214
215 AhciCtlBlock64 += AHCI_CLB_ALIGNEMENT_MASK;
216 AhciCtlBlock64 &= ~AHCI_CLB_ALIGNEMENT_MASK;
217
218 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: CLP BASE 1k-aligned %I64x\n", AhciCtlBlock64));
219
220 chan->AhciCtlBlock = (PIDE_AHCI_CHANNEL_CTL_BLOCK)AhciCtlBlock;
221
222 chan->AHCI_CTL_PhAddr = AtapiVirtToPhysAddr(HwDeviceExtension, NULL, (PUCHAR)(chan->AhciCtlBlock), &i, &ph_addru);
223 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: CLP Phys BASE %I64x\n", chan->AHCI_CTL_PhAddr));
224 if(!chan->AHCI_CTL_PhAddr || !i || ((LONG)(chan->AHCI_CTL_PhAddr) == -1)) {
225 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No AHCI CLP BASE\n" ));
226 chan->AhciCtlBlock = NULL;
227 chan->AHCI_CTL_PhAddr = 0;
228 return;
229 }
230 if(ph_addru) {
231 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No AHCI CLP below 4Gb\n" ));
232 MmFreeContiguousMemory(chan->AhciCtlBlock0);
233 chan->AhciCtlBlock = NULL;
234 chan->AHCI_CTL_PhAddr = 0;
235 return;
236 }
237 } else {
238 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: Can't alloc AHCI CLP\n"));
239 }
240 }
241#endif //USE_OWN_DMA
242 return;
243} // end AtapiDmaAlloc()
AHCI_CLB_ALIGNEMENT_MASK
#define AHCI_CLB_ALIGNEMENT_MASK
Definition: bsmaster.h:518
PIDE_AHCI_CHANNEL_CTL_BLOCK
struct _IDE_AHCI_CHANNEL_CTL_BLOCK * PIDE_AHCI_CHANNEL_CTL_BLOCK
AtapiVirtToPhysAddr
#define AtapiVirtToPhysAddr(hwde, srb, phaddr, plen, phaddru)
Definition: bsmaster.h:1716
MmAllocateContiguousMemory
PVOID NTAPI MmAllocateContiguousMemory(IN SIZE_T NumberOfBytes, IN PHYSICAL_ADDRESS HighestAcceptableAddress)
Definition: contmem.c:626
MmFreeContiguousMemory
VOID NTAPI MmFreeContiguousMemory(IN PVOID BaseAddress)
Definition: contmem.c:653
i
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
ph4gb
PHYSICAL_ADDRESS ph4gb
Definition: id_dma.cpp:56
LONG
long LONG
Definition: pedump.c:60
_HW_CHANNEL::DB_IO
PVOID DB_IO
Definition: bsmaster.h:1096
_HW_CHANNEL::DB_PRD
PVOID DB_PRD
Definition: bsmaster.h:1094
_HW_CHANNEL::DB_PRD_PhAddr
ULONG DB_PRD_PhAddr
Definition: bsmaster.h:1095
_HW_CHANNEL::AhciCtlBlock0
PIDE_AHCI_CHANNEL_CTL_BLOCK AhciCtlBlock0
Definition: bsmaster.h:1102
_HW_CHANNEL::AHCI_CTL_PhAddr
ULONGLONG AHCI_CTL_PhAddr
Definition: bsmaster.h:1104
_HW_CHANNEL::AhciCtlBlock
PIDE_AHCI_CHANNEL_CTL_BLOCK AhciCtlBlock
Definition: bsmaster.h:1103
_HW_CHANNEL::DB_IO_PhAddr
ULONG DB_IO_PhAddr
Definition: bsmaster.h:1097
_HW_CHANNEL::CopyDmaBuffer
BOOLEAN CopyDmaBuffer
Definition: bsmaster.h:1045
_HW_DEVICE_EXTENSION::MaximumDmaTransferLength
ULONG MaximumDmaTransferLength
Definition: bsmaster.h:1317
_HW_DEVICE_EXTENSION::Host64
BOOLEAN Host64
Definition: bsmaster.h:1304
_IDE_AHCI_CHANNEL_CTL_BLOCK
Definition: bsmaster.h:845
PUCHAR
unsigned char * PUCHAR
Definition: typedefs.h:53
ULONGLONG
uint64_t ULONGLONG
Definition: typedefs.h:67
_ATA_REQ
Definition: bsmaster.h:870

Referenced by UniataAhciInit(), and UniataFindBusMasterController().

◆ AtapiDmaDBPreSync()

BOOLEAN NTAPI AtapiDmaDBPreSync ( IN PVOID  HwDeviceExtension,
PHW_CHANNEL  chan,
PSCSI_REQUEST_BLOCK  Srb 
)

Definition at line 553 of file id_dma.cpp.

558{
559 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
560 PATA_REQ AtaReq = (PATA_REQ)(Srb->SrbExtension);
561
562 if(!AtaReq->ata.dma_base) {
563 KdPrint2((PRINT_PREFIX "AtapiDmaDBPreSync: *** !AtaReq->ata.dma_base\n"));
564 return FALSE;
565 }
566// GetStatus(chan, statusByte2);
567 if(AtaReq->Flags & REQ_FLAG_DMA_DBUF_PRD) {
568 KdPrint2((PRINT_PREFIX " DBUF_PRD\n"));
569 ASSERT(FALSE);
570 if(deviceExtension->HwFlags & UNIATA_AHCI) {
571 RtlCopyMemory(chan->DB_PRD, AtaReq->ahci.ahci_cmd_ptr, sizeof(AtaReq->ahci_cmd0));
572 } else {
573 RtlCopyMemory(chan->DB_PRD, &(AtaReq->dma_tab), sizeof(AtaReq->dma_tab));
574 }
575 }
576 if(!(Srb->SrbFlags & SRB_FLAGS_DATA_IN) &&
577 (AtaReq->Flags & REQ_FLAG_DMA_DBUF)) {
578 KdPrint2((PRINT_PREFIX " DBUF (Write)\n"));
579 ASSERT(FALSE);
580 RtlCopyMemory(chan->DB_IO, AtaReq->DataBuffer,
581 Srb->DataTransferLength);
582 }
583 return TRUE;
584} // end AtapiDmaDBPreSync()
REQ_FLAG_DMA_DBUF
#define REQ_FLAG_DMA_DBUF
Definition: bsmaster.h:938
PATA_REQ
union _ATA_REQ * PATA_REQ
REQ_FLAG_DMA_DBUF_PRD
#define REQ_FLAG_DMA_DBUF_PRD
Definition: bsmaster.h:939
Srb
_In_ PSCSI_REQUEST_BLOCK Srb
Definition: cdrom.h:989
SRB_FLAGS_DATA_IN
#define SRB_FLAGS_DATA_IN
Definition: srb.h:400
ASSERT
#define ASSERT(a)
Definition: mode.c:44
_SCSI_REQUEST_BLOCK::DataTransferLength
ULONG DataTransferLength
Definition: srb.h:261
_SCSI_REQUEST_BLOCK::SrbExtension
PVOID SrbExtension
Definition: srb.h:267
_SCSI_REQUEST_BLOCK::SrbFlags
ULONG SrbFlags
Definition: srb.h:260
RtlCopyMemory
#define RtlCopyMemory(Destination, Source, Length)
Definition: typedefs.h:263
_ATA_REQ::ahci
struct _ATA_REQ::@1162::@1164::@1168::@1171 ahci
_ATA_REQ::ahci_cmd0
IDE_AHCI_CMD ahci_cmd0
Definition: bsmaster.h:922
_ATA_REQ::DataBuffer
PUSHORT DataBuffer
Definition: bsmaster.h:882
_ATA_REQ::ata
struct _ATA_REQ::@1162::@1164::@1168::@1170 ata
_ATA_REQ::dma_tab
BM_DMA_ENTRY dma_tab[ATA_DMA_ENTRIES]
Definition: bsmaster.h:921
_ATA_REQ::Flags
UCHAR Flags
Definition: bsmaster.h:892

Referenced by AtapiInterrupt__(), AtapiSendCommand(), IdeReadWrite(), and IdeSendCommand().

◆ AtapiDmaDBSync()

BOOLEAN NTAPI AtapiDmaDBSync ( PHW_CHANNEL  chan,
PSCSI_REQUEST_BLOCK  Srb 
)

Definition at line 532 of file id_dma.cpp.

536{
537 PATA_REQ AtaReq;
538
539 AtaReq = (PATA_REQ)(Srb->SrbExtension);
540 if((Srb->SrbFlags & SRB_FLAGS_DATA_IN) &&
541 (AtaReq->Flags & REQ_FLAG_DMA_DBUF)) {
542 KdPrint2((PRINT_PREFIX " AtapiDmaDBSync is issued.\n"));
543 ASSERT(FALSE);
544 KdPrint2((PRINT_PREFIX " DBUF (Read)\n"));
545 RtlCopyMemory(AtaReq->DataBuffer, chan->DB_IO,
546 Srb->DataTransferLength);
547 }
548 return TRUE;
549} // end AtapiDmaDBSync()

Referenced by AtapiCallBack__(), AtapiInterrupt__(), and AtapiStartIo__().

◆ AtapiDmaDone()

UCHAR NTAPI AtapiDmaDone ( IN PVOID  HwDeviceExtension,
IN ULONG  DeviceNumber,
IN ULONG  lChannel,
IN PSCSI_REQUEST_BLOCK  Srb 
)

Definition at line 685 of file id_dma.cpp.

691{
692 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
693 //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM = deviceExtension->BaseIoAddressBM[lChannel];
694 PHW_CHANNEL chan = &deviceExtension->chan[lChannel];
695 UCHAR dma_status;
696
697 ULONG VendorID = deviceExtension->DevID & 0xffff;
698 ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
699
700 KdPrint2((PRINT_PREFIX "AtapiDmaDone: dev %d\n", DeviceNumber));
701
702 if(deviceExtension->HwFlags & UNIATA_AHCI) {
703 KdPrint2((PRINT_PREFIX " ACHTUNG! should not be called for AHCI!\n"));
704 return IDE_STATUS_WRONG;
705 }
706
707 switch(VendorID) {
708 case ATA_PROMISE_ID:
709 if(ChipType == PRNEW) {
710 ULONG Channel = deviceExtension->Channel + lChannel;
711/*
712 AtapiWritePortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11,
713 AtapiReadPortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11) &
714 ~(Channel ? 0x08 : 0x02));
715*/
716 if(chan->ChannelCtrlFlags & CTRFLAGS_LBA48) {
717 AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),(Channel ? 0x24 : 0x20),
718 0
719 );
720 }
721/*
722 } else
723 if(deviceExtension->MemIo) {
724 // end transaction
725 AtapiWritePort4(chan,
726 IDX_BM_Command,
727 (AtapiReadPort4(chan,
728 IDX_BM_Command) & ~0x00000080) );
729 // clear flag
730 chan->ChannelCtrlFlags &= ~CTRFLAGS_DMA_ACTIVE;
731 return 0;
732*/
733 }
734 break;
735 }
736
737 // get status
738 dma_status = AtapiReadPort1(chan, IDX_BM_Status) & BM_STATUS_MASK;
739 // end transaction
740 AtapiWritePort1(chan, IDX_BM_Command,
741 AtapiReadPort1(chan, IDX_BM_Command) &
742 ~BM_COMMAND_START_STOP);
743 // clear interrupt and error status
744 AtapiWritePort1(chan, IDX_BM_Status, BM_STATUS_ERR | BM_STATUS_INTR);
745 // clear flag
746 chan->ChannelCtrlFlags &= ~CTRFLAGS_DMA_ACTIVE;
747
748 return dma_status;
749
750} // end AtapiDmaDone()
BM_STATUS_ERR
#define BM_STATUS_ERR
Definition: bsmaster.h:143
BM_STATUS_MASK
#define BM_STATUS_MASK
Definition: bsmaster.h:145
IDX_BM_Status
#define IDX_BM_Status
Definition: bsmaster.h:169
CTRFLAGS_LBA48
#define CTRFLAGS_LBA48
Definition: bsmaster.h:1137
BM_STATUS_INTR
#define BM_STATUS_INTR
Definition: bsmaster.h:144
BM_COMMAND_START_STOP
#define BM_COMMAND_START_STOP
Definition: bsmaster.h:150
IDE_STATUS_WRONG
#define IDE_STATUS_WRONG
Definition: hwide.h:121

Referenced by AtapiCheckInterrupt__(), AtapiInterrupt__(), AtapiResetController__(), AtapiSoftReset(), IdeSendCommand(), and UniataFindBusMasterController().

◆ AtapiDmaInit()

VOID NTAPI AtapiDmaInit ( IN PVOID  HwDeviceExtension,
IN ULONG  DeviceNumber,
IN ULONG  lChannel,
IN SCHAR  apiomode,
IN SCHAR  wdmamode,
IN SCHAR  udmamode 
)

Definition at line 975 of file id_dma.cpp.

984{
985 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
986 ULONG Channel = deviceExtension->Channel + lChannel;
987 PHW_CHANNEL chan = &deviceExtension->chan[lChannel];
988 //LONG statusByte = 0;
989 ULONG dev = Channel*2 + DeviceNumber; // for non-SATA/AHCI only!
990 //ULONG ldev = lChannel*2 + DeviceNumber; // for non-SATA/AHCI only!
991 BOOLEAN isAtapi = ATAPI_DEVICE(chan, DeviceNumber);
992 ULONG slotNumber = deviceExtension->slotNumber;
993 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
994 LONG i;
995 PHW_LU_EXTENSION LunExt = chan->lun[DeviceNumber];
996 UCHAR ModeByte;
997
998 ULONG VendorID = deviceExtension->DevID & 0xffff;
999 //ULONG DeviceID = (deviceExtension->DevID >> 16) & 0xffff;
1000 //ULONG RevID = deviceExtension->RevID;
1001 ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
1002 ULONG ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
1003
1004 LONG statusByte = 0;
1005
1006 //UCHAR *reg_val = NULL;
1007
1008 LunExt->DeviceFlags &= ~DFLAGS_REINIT_DMA;
1009 /* set our most pessimistic default mode */
1010 LunExt->TransferMode = ATA_PIO;
1011// if(!deviceExtension->BaseIoAddressBM[lChannel]) {
1012 if(!deviceExtension->BusMaster) {
1013 KdPrint2((PRINT_PREFIX " !deviceExtension->BusMaster: NO DMA\n"));
1014 wdmamode = udmamode = -1;
1015 }
1016
1017 // Limit transfer mode (controller limitation)
1018 if((LONG)chan->MaxTransferMode >= ATA_UDMA) {
1019 KdPrint2((PRINT_PREFIX "AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA\n"));
1020 udmamode = min( udmamode, (CHAR)(chan->MaxTransferMode - ATA_UDMA));
1021 } else
1022 if((LONG)chan->MaxTransferMode >= ATA_WDMA) {
1023 KdPrint2((PRINT_PREFIX "AtapiDmaInit: chan->MaxTransferMode >= ATA_WDMA\n"));
1024 udmamode = -1;
1025 wdmamode = min( wdmamode, (CHAR)(chan->MaxTransferMode - ATA_WDMA));
1026 } else
1027 if((LONG)chan->MaxTransferMode >= ATA_PIO0) {
1028 KdPrint2((PRINT_PREFIX "AtapiDmaInit: NO DMA\n"));
1029 wdmamode = udmamode = -1;
1030 apiomode = min( apiomode, (CHAR)(chan->MaxTransferMode - ATA_PIO0));
1031 } else {
1032 KdPrint2((PRINT_PREFIX "AtapiDmaInit: PIO0\n"));
1033 wdmamode = udmamode = -1;
1034 apiomode = 0;
1035 }
1036 // Limit transfer mode (device limitation)
1037 KdPrint2((PRINT_PREFIX "AtapiDmaInit: LunExt->LimitedTransferMode %#x\n", LunExt->LimitedTransferMode));
1038 if((LONG)LunExt->LimitedTransferMode >= ATA_UDMA) {
1039 KdPrint2((PRINT_PREFIX "AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => %#x\n",
1040 min( udmamode, (CHAR)(LunExt->LimitedTransferMode - ATA_UDMA))
1041 ));
1042 udmamode = min( udmamode, (CHAR)(LunExt->LimitedTransferMode - ATA_UDMA));
1043 } else
1044 if((LONG)LunExt->LimitedTransferMode >= ATA_WDMA) {
1045 KdPrint2((PRINT_PREFIX "AtapiDmaInit: LunExt->MaxTransferMode >= ATA_WDMA => %#x\n",
1046 min( wdmamode, (CHAR)(LunExt->LimitedTransferMode - ATA_WDMA))
1047 ));
1048 udmamode = -1;
1049 wdmamode = min( wdmamode, (CHAR)(LunExt->LimitedTransferMode - ATA_WDMA));
1050 } else
1051 if((LONG)LunExt->LimitedTransferMode >= ATA_PIO0) {
1052 KdPrint2((PRINT_PREFIX "AtapiDmaInit: lun NO DMA\n"));
1053 wdmamode = udmamode = -1;
1054 apiomode = min( apiomode, (CHAR)(LunExt->LimitedTransferMode - ATA_PIO0));
1055 } else {
1056 KdPrint2((PRINT_PREFIX "AtapiDmaInit: lun PIO0\n"));
1057 wdmamode = udmamode = -1;
1058 apiomode = 0;
1059 }
1060
1061 //if(!(ChipFlags & UNIATA_AHCI)) {
1062
1063 // this is necessary for future PM support
1064 SelectDrive(chan, DeviceNumber);
1065 GetStatus(chan, statusByte);
1066 // we can see here IDE_STATUS_ERROR status after previous operation
1067 if(statusByte & IDE_STATUS_ERROR) {
1068 KdPrint2((PRINT_PREFIX "IDE_STATUS_ERROR detected on entry, statusByte = %#x\n", statusByte));
1069 //GetBaseStatus(chan, statusByte);
1070 }
1071 if(statusByte && UniataIsIdle(deviceExtension, statusByte & ~IDE_STATUS_ERROR) != IDE_STATUS_IDLE) {
1072 KdPrint2((PRINT_PREFIX "Can't setup transfer mode: statusByte = %#x\n", statusByte));
1073 return;
1074 }
1075 //}
1076
1077 chan->last_cdev = DeviceNumber;
1078 if(UniataIsSATARangeAvailable(deviceExtension, lChannel) ||
1079 (ChipFlags & UNIATA_AHCI) || (chan->MaxTransferMode >= ATA_SA150)
1080 ) {
1081 //if(ChipFlags & (UNIATA_SATA | UNIATA_AHCI)) {
1082 /****************/
1083 /* SATA Generic */
1084 /****************/
1085
1086 KdPrint2((PRINT_PREFIX "SATA Generic\n"));
1087
1088 if((udmamode >= 5) || (ChipFlags & UNIATA_AHCI) || ((udmamode >= 0) && (chan->MaxTransferMode >= ATA_SA150))) {
1089 /* some drives report UDMA6, some UDMA5 */
1090 /* ATAPI may not have SataCapabilities set in IDENTIFY DATA */
1091 if(ata_is_sata(&(LunExt->IdentifyData))) {
1092 //udmamode = min(udmamode, 6);
1093 KdPrint2((PRINT_PREFIX "LunExt->LimitedTransferMode %x, LunExt->OrigTransferMode %x\n",
1094 LunExt->LimitedTransferMode, LunExt->OrigTransferMode));
1095 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, min(LunExt->LimitedTransferMode, LunExt->OrigTransferMode))) {
1096 return;
1097 }
1098 udmamode = min(udmamode, 6);
1099
1100 } else {
1101 KdPrint2((PRINT_PREFIX "SATA -> PATA adapter ?\n"));
1102 if (udmamode > 2 && (!LunExt->IdentifyData.HwResCableId && (LunExt->IdentifyData.HwResValid == IDENTIFY_CABLE_ID_VALID) )) {
1103 KdPrint2((PRINT_PREFIX "AtapiDmaInit: DMA limited to UDMA33, non-ATA66 compliant cable\n"));
1104 udmamode = 2;
1105 apiomode = min( apiomode, (CHAR)(LunExt->LimitedTransferMode - ATA_PIO0));
1106 } else {
1107 udmamode = min(udmamode, 6);
1108 }
1109 }
1110 }
1111 if(udmamode >= 0) {
1112 ModeByte = ATA_UDMA0 + udmamode;
1113 } else
1114 if(wdmamode >= 0) {
1115 ModeByte = ATA_WDMA0 + wdmamode;
1116 } else
1117 if(apiomode >= 0) {
1118 ModeByte = ATA_PIO0 + apiomode;
1119 } else {
1120 ModeByte = ATA_PIO;
1121 }
1122
1123 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ModeByte);
1124 return;
1125 }
1126
1127 if(deviceExtension->UnknownDev) {
1128 KdPrint2((PRINT_PREFIX "Unknown chip, omit Vendor/Dev checks\n"));
1129 goto try_generic_dma;
1130 }
1131
1132 if(udmamode > 2 && (!LunExt->IdentifyData.HwResCableId && (LunExt->IdentifyData.HwResValid == IDENTIFY_CABLE_ID_VALID)) ) {
1133 if(ata_is_sata(&(LunExt->IdentifyData))) {
1134 KdPrint2((PRINT_PREFIX "AtapiDmaInit: SATA beyond adapter or Controller compat mode\n"));
1135 } else {
1136 KdPrint2((PRINT_PREFIX "AtapiDmaInit: DMA limited to UDMA33, non-ATA66 compliant cable\n"));
1137 udmamode = 2;
1138 apiomode = min( apiomode, (CHAR)(LunExt->LimitedTransferMode - ATA_PIO));
1139 }
1140 }
1141
1142 KdPrint2((PRINT_PREFIX "Setup chip a:w:u=%d:%d:%d\n",
1143 apiomode,
1144 wdmamode,
1145 udmamode));
1146
1147 switch(VendorID) {
1148 case ATA_ACARD_ID: {
1149 /*********/
1150 /* Acard */
1151 /*********/
1152 static const USHORT reg4a = 0xa6;
1153 UCHAR reg = 0x40 + (UCHAR)dev;
1154
1155 if(ChipType == ATPOLD) {
1156 /* Old Acard 850 */
1157 static const USHORT reg4x2 = 0x0301;
1158
1159 for(i=udmamode; i>=0; i--) {
1160 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA + i)) {
1161set_old_acard:
1162 ChangePciConfig1(0x54, a | (0x01 << dev) | ((i+1) << (dev*2)));
1163 SetPciConfig1(0x4a, reg4a);
1164 SetPciConfig2(reg, reg4x2);
1165 return;
1166 }
1167
1168 }
1169 if (wdmamode >= 2 && apiomode >= 4) {
1170 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA2)) {
1171 goto set_old_acard;
1172 }
1173 }
1174 } else {
1175 /* New Acard 86X */
1176 static const UCHAR reg4x = 0x31;
1177
1178 for(i=udmamode; i>=0; i--) {
1179 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA + i)) {
1180set_new_acard:
1181 ChangePciConfig2(0x44, (a & ~(0x000f << (dev * 4))) | ((i+1) << (dev*4)));
1182 SetPciConfig1(0x4a, reg4a);
1183 SetPciConfig1(reg, reg4x);
1184 return;
1185 }
1186
1187 }
1188 if (wdmamode >= 2 && apiomode >= 4) {
1189 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA2)) {
1190 goto set_new_acard;
1191 }
1192 }
1193 }
1194 /* Use GENERIC PIO */
1195 break; }
1196 case ATA_ACER_LABS_ID: {
1197 /************************/
1198 /* Acer Labs Inc. (ALI) */
1199 /************************/
1200 static const UCHAR ali_udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f};
1201 static const ULONG ali_pio[] =
1202 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1203 0x00310001, 0x00440001};
1204 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
1205 if ((ChipFlags & ALIOLD) &&
1206 (udmamode >= 0 || wdmamode >= 0)) {
1207 if(ATAPI_DEVICE(chan, 0) &&
1208 ATAPI_DEVICE(chan, 1)) {
1209 // 2 devices on this channel - NO DMA
1210 chan->MaxTransferMode =
1211 min(chan->MaxTransferMode, ATA_PIO4);
1212 udmamode = wdmamode = -1;
1213 break;
1214 }
1215 }
1216 for(i=udmamode; i>=0; i--) {
1217 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1218 ULONG word54;
1219
1220 GetPciConfig4(0x54, word54);
1221 word54 &= ~(0x000f000f << (dev * 4));
1222 word54 |= (((ali_udma[i]<<16) | 5) << (dev * 4));
1223 SetPciConfig4(0x54, word54);
1224 ChangePciConfig1(0x53, a | 0x03);
1225 SetPciConfig4(0x58 + (Channel<<2), 0x00310001);
1226 return;
1227 }
1228 }
1229 /* make sure eventual UDMA mode from the BIOS is disabled */
1230 ChangePciConfig2(0x56, a & ~(0x0008 << (dev * 4)) );
1231 if (wdmamode >= 2 && apiomode >= 4) {
1232 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA2)) {
1233 ChangePciConfig1(0x53, a | 0x03);
1234 chan->ChannelCtrlFlags |= CTRFLAGS_DMA_RO;
1235 return;
1236 }
1237 }
1238 ChangePciConfig1(0x53, (a & ~0x01) | 0x02);
1239
1240 for(i=apiomode; i>=0; i--) {
1241 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + i)) {
1242 ChangePciConfig4(0x54, a & ~(0x0008000f << (dev * 4)));
1243 SetPciConfig4(0x58 + (Channel<<2), ali_pio[i]);
1244 return;
1245 }
1246 }
1247 return;
1248 break; }
1249 case ATA_AMD_ID:
1250 case ATA_NVIDIA_ID:
1251 case ATA_VIA_ID: {
1252 /********************/
1253 /* AMD, nVidia, VIA */
1254 /********************/
1255 if(VendorID == ATA_VIA_ID) {
1256 if((ChipFlags & VIASATA) &&
1257 (Channel == 0)) {
1258 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_SA150);
1259 return;
1260 }
1261 if((ChipFlags & VIABAR) &&
1262 (Channel < 2)) {
1263 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_SA150);
1264 return;
1265 }
1266 }
1267
1268 static const UCHAR via_modes[6][7] = {
1269 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* ATA33 and New Chips */
1270 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* ATA66 */
1271 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* ATA100 */
1272 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
1273 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }, /* AMD/nVIDIA */
1274 { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }}; /* VIA new */
1275 static const UCHAR via_pio[] =
1276 { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
1277 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1278 const UCHAR *reg_val = NULL;
1279 UCHAR reg = 0x53-(UCHAR)dev;
1280 UCHAR reg2 = reg-0x08;
1281
1282 if(ChipFlags & VIABAR) {
1283 reg = 0xb3;
1284 reg2 = 0xab;
1285 }
1286
1287 reg_val = &via_modes[ChipType][0];
1288
1289 if(VendorID == ATA_NVIDIA_ID) {
1290 reg += 0x10;
1291 reg2 += 0x10;
1292 }
1293
1294 for(i = udmamode; i>=0; i--) {
1295 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1296 SetPciConfig1(reg2, via_pio[8+i]);
1297 SetPciConfig1(reg, (UCHAR)reg_val[i]);
1298 return;
1299 }
1300 }
1301 if(!(ChipFlags & VIABAR)) {
1302 /* This chip can't do WDMA. */
1303 for(i = wdmamode; i>=0; i--) {
1304 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1305 SetPciConfig1(reg2, via_pio[5+i]);
1306 SetPciConfig1(reg, 0x8b);
1307 return;
1308 }
1309 }
1310 }
1311 /* set PIO mode timings */
1312 if((apiomode >= 0) && (ChipType != VIA133)) {
1313 SetPciConfig1(reg2, via_pio[apiomode]);
1314 }
1315 if(VendorID == ATA_VIA_ID /*&& (ChipType == VIA33 || ChipType == VIA66)*/) {
1316 via82c_timing(deviceExtension, dev, ATA_PIO0 + apiomode);
1317 }
1318 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1319 return;
1320
1321 break; }
1322 case ATA_CYRIX_ID: {
1323 /*********/
1324 /* Cyrix */
1325 /*********/
1326dma_cs55xx:
1327 if(apiomode >= 4)
1328 apiomode = 4;
1329
1330 if(ChipType == CYRIX_3x) {
1331#ifdef __REACTOS__
1332 static const ULONG cyr_piotiming[] =
1333 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1334 static const ULONG cyr_wdmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1335 static const ULONG cyr_udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1336#else
1337 ULONG cyr_piotiming[] =
1338 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1339 ULONG cyr_wdmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1340 ULONG cyr_udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1341#endif
1342 ULONG mode_reg = 0x24+(dev << 3);
1343
1344 for(i=udmamode; i>=0; i--) {
1345 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1346 AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0), mode_reg, cyr_udmatiming[udmamode]);
1347 return;
1348 }
1349 }
1350 for(i=wdmamode; i>=0; i--) {
1351 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1352 AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0), mode_reg, cyr_wdmatiming[wdmamode]);
1353 return;
1354 }
1355 }
1356 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode)) {
1357 AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0), mode_reg, cyr_piotiming[apiomode]);
1358 return;
1359 }
1360 } else
1361 if(ChipType == CYRIX_OLD) {
1362#ifdef __REACTOS__
1363 static const UCHAR cyr_piotiming_old[] = { 11, 6, 3, 2, 1 };
1364#else
1365 UCHAR cyr_piotiming_old[] =
1366 { 11, 6, 3, 2, 1 };
1367#endif
1368 UCHAR timing;
1369
1370 for(i=wdmamode; i>=0; i--) {
1371 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1372 return;
1373 }
1374 }
1375 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode)) {
1376 timing = (6-apiomode) | (cyr_piotiming_old[i]);
1377 /* Channel command timing */
1378 SetPciConfig1(0x62+Channel, timing);
1379 /* Read command timing */
1380 SetPciConfig1(0x64+Channel*4+dev, timing);
1381 /* Write command timing */
1382 SetPciConfig1(0x66+Channel*4+dev, timing);
1383 return;
1384 }
1385 } else
1386 if(ChipType == CYRIX_35) {
1387/*
1388 USHORT c35_pio_timings[5] = {
1389 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131
1390 };
1391 USHORT c35_pio_cmd_timings[5] = {
1392 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
1393 };
1394 ULONG c35_udma_timings[5] = {
1395 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061
1396 };
1397 ULONG c35_mwdma_timings[3] = {
1398 0x7F0FFFF3, 0x7F035352, 0x7F024241
1399 };
1400 ULONG mode_reg = 0x24+(dev << 3);
1401*/
1402 /* No MSR support yet, do not touch any regs */
1403 for(i=udmamode; i>=0; i--) {
1404 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1405 return;
1406 }
1407 }
1408 for(i=wdmamode; i>=0; i--) {
1409 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1410 return;
1411 }
1412 }
1413 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode)) {
1414 return;
1415 }
1416 }
1417 return;
1418
1419 break; }
1420 case ATA_NATIONAL_ID: {
1421 /************/
1422 /* National */
1423 /************/
1424 if(!ChipType) {
1425#ifdef __REACTOS__
1426 static const ULONG nat_piotiming[] =
1427 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010, 0x00803020,
1428 0x20102010, 0x00100010, 0x00100010, 0x00100010, 0x00100010 };
1429 static const ULONG nat_dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
1430 static const ULONG nat_udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
1431#else
1432 ULONG nat_piotiming[] =
1433 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
1434 0x00803020, 0x20102010, 0x00100010,
1435 0x00100010, 0x00100010, 0x00100010 };
1436 ULONG nat_dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
1437 ULONG nat_udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
1438#endif
1439
1440 if(apiomode >= 4)
1441 apiomode = 4;
1442 for(i=udmamode; i>=0; i--) {
1443 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1444 SetPciConfig4(0x44 + (dev * 8), nat_udmatiming[i]);
1445 SetPciConfig4(0x40 + (dev * 8), nat_piotiming[i+8]);
1446 return;
1447 }
1448 }
1449 for(i=wdmamode; i>=0; i--) {
1450 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1451 SetPciConfig4(0x44 + (dev * 8), nat_dmatiming[i]);
1452 SetPciConfig4(0x40 + (dev * 8), nat_piotiming[i+5]);
1453 return;
1454 }
1455 }
1456 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode)) {
1457 ChangePciConfig4(0x44 + (dev * 8), a | 0x80000000);
1458 SetPciConfig4(0x40 + (dev * 8), nat_piotiming[apiomode]);
1459 return;
1460 }
1461 } else {
1462 goto dma_cs55xx;
1463 }
1464 /* Use GENERIC PIO */
1465 break; }
1466 case ATA_CYPRESS_ID:
1467 /***********/
1468 /* Cypress */
1469 /***********/
1470 if (wdmamode >= 2 && apiomode >= 4) {
1471 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA2)) {
1472 SetPciConfig2(Channel ? 0x4e:0x4c, 0x2020);
1473 return;
1474 }
1475 }
1476 /* Use GENERIC PIO */
1477 break;
1478 case ATA_MARVELL_ID:
1479 /***********/
1480 /* Marvell */
1481 /***********/
1482 for(i=udmamode; i>=0; i--) {
1483 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1484 return;
1485 }
1486 }
1487 for(i=wdmamode; i>=0; i--) {
1488 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1489 return;
1490 }
1491 }
1492 /* try generic DMA, use hpt_timing() */
1493 if (wdmamode >= 0 && apiomode >= 4) {
1494 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_DMA)) {
1495 return;
1496 }
1497 }
1498 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1499 return;
1500 break;
1501 case ATA_NETCELL_ID:
1502 /***********/
1503 /* NetCell */
1504 /***********/
1505 if (wdmamode >= 2 && apiomode >= 4) {
1506 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA2)) {
1507 return;
1508 }
1509 }
1510 /* Use GENERIC PIO */
1511 break;
1512 case ATA_HIGHPOINT_ID: {
1513 /********************/
1514 /* High Point (HPT) */
1515 /********************/
1516 for(i=udmamode; i>=0; i--) {
1517 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1518 hpt_timing(deviceExtension, dev, (UCHAR)(ATA_UDMA + i)); // ???
1519 return;
1520 }
1521 }
1522
1523 for(i=wdmamode; i>=0; i--) {
1524 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1525 hpt_timing(deviceExtension, dev, (UCHAR)(ATA_WDMA0+i));
1526 return;
1527 }
1528 }
1529 /* try generic DMA, use hpt_timing() */
1530 if (wdmamode >= 0 && apiomode >= 4) {
1531 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_DMA)) {
1532 return;
1533 }
1534 }
1535 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1536 hpt_timing(deviceExtension, dev, ATA_PIO0 + apiomode);
1537 return;
1538 break; }
1539 case ATA_INTEL_ID: {
1540 /*********/
1541 /* Intel */
1542 /*********/
1543
1544 KdPrint2((PRINT_PREFIX "Intel %d\n", Channel));
1545 BOOLEAN udma_ok = FALSE;
1546 ULONG idx = 0;
1547 ULONG reg40;
1548 UCHAR reg44;
1549 USHORT reg48;
1550 USHORT reg4a;
1551 USHORT reg54;
1552 ULONG mask40 = 0;
1553 ULONG new40 = 0;
1554 UCHAR mask44 = 0;
1555 UCHAR new44 = 0;
1556#ifdef __REACTOS__
1557 static const UCHAR intel_timings[] =
1558 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1559 static const UCHAR intel_utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 };
1560#else
1561 UCHAR intel_timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1562 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1563 UCHAR intel_utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 };
1564#endif
1565 const UCHAR needed_pio[3] = {
1566 ATA_PIO0, ATA_PIO3, ATA_PIO4
1567 };
1568
1569 if(deviceExtension->DevID == ATA_I82371FB) {
1570 KdPrint2((PRINT_PREFIX " I82371FB\n"));
1571 USHORT reg4x;
1572 USHORT control=0;
1573 for(i=wdmamode; i>=0; i--) {
1574 idx = 5+i;
1575 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1576 udma_ok = TRUE;
1577 break;
1578 }
1579 }
1580 if(!udma_ok) {
1581 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1582 idx = apiomode;
1583 } else {
1584 /* If the drive MWDMA is faster than it can do PIO then
1585 we must force PIO into PIO0 */
1586 if (apiomode < needed_pio[wdmamode]) {
1587 /* Enable DMA timing only */
1588 control |= 8; /* PIO cycles in PIO0 */
1589 }
1590 }
1591 GetPciConfig2(0x40+Channel*2, reg4x);
1592 if(apiomode > ATA_PIO0) {
1593 control |= 0x03; /* IORDY|TIME0 */
1594 } else {
1595 control |= 0x02; /* IORDY */
1596 }
1597 // if (ata_pio_need_iordy(adev))
1598 //control |= 2; /* IE */
1599 if (!isAtapi) {
1600 control |= 4; /* PPE enable */
1601 }
1602 /* Mask out the relevant control and timing bits we will load. Also
1603 clear the other drive TIME register as a precaution */
1604 reg4x &= 0xCC00 | (0x0E << (DeviceNumber*4));
1605 reg4x |= control << (DeviceNumber*4);
1606 reg4x |= intel_timings[idx] << 8;
1607 SetPciConfig2(0x40+Channel*2, reg4x);
1608 return;
1609 }
1610
1611 if(deviceExtension->DevID == ATA_ISCH) {
1612 ULONG tim;
1613 KdPrint2((PRINT_PREFIX " ISCH\n"));
1614 GetPciConfig4(0x80 + dev*4, tim);
1615
1616 for(i=udmamode; i>=0; i--) {
1617 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1618 tim |= (0x1 << 31);
1619 tim &= ~(0x7 << 16);
1620 tim |= (i << 16);
1621
1622 idx = i+8;
1623 udma_ok = TRUE;
1624 apiomode = ATA_PIO4;
1625 break;
1626 }
1627 }
1628 if(!udma_ok) {
1629 for(i=wdmamode; i>=0; i--) {
1630 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1631 tim &= ~(0x1 << 31);
1632 tim &= ~(0x3 << 8);
1633 tim |= (i << 8);
1634
1635 idx = i+5;
1636 udma_ok = TRUE;
1637 apiomode = (i == 0) ? ATA_PIO0 :
1638 (i == 1) ? ATA_PIO3 : ATA_PIO4;
1639 break;
1640 }
1641 }
1642 }
1643 if(!udma_ok) {
1644 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1645 idx = apiomode;
1646 }
1647 tim &= ~(0x7);
1648 tim |= (apiomode & 0x7);
1649 SetPciConfig4(0x80 + dev*4, tim);
1650
1651 return;
1652 }
1653
1654 GetPciConfig2(0x48, reg48);
1655// if(!(ChipFlags & ICH4_FIX)) {
1656 GetPciConfig2(0x4a, reg4a);
1657// }
1658 GetPciConfig2(0x54, reg54);
1659// if(udmamode >= 0) {
1660 // enable the write buffer to be used in a split (ping/pong) manner.
1661 reg54 |= 0x400;
1662// } else {
1663// reg54 &= ~0x400;
1664// }
1665
1666// reg40 &= ~0x00ff00ff;
1667// reg40 |= 0x40774077;
1668
1669 for(i=udmamode; i>=0; i--) {
1670 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1671
1672 /* Set UDMA reference clock (33 MHz or more). */
1673 SetPciConfig1(0x48, reg48 | (0x0001 << dev));
1674// if(!(ChipFlags & ICH4_FIX)) {
1675 if(deviceExtension->MaxTransferMode == ATA_UDMA3) {
1676 // Special case (undocumented overclock !) for PIIX4e
1677 SetPciConfig2(0x4a, (reg4a | (0x03 << (dev<<2)) ) );
1678 } else {
1679 SetPciConfig2(0x4a, (reg4a & ~(0x03 << (dev<<2))) |
1680 (((USHORT)(intel_utimings[i])) << (dev<<2) ) );
1681 }
1682// }
1683 /* Set UDMA reference clock (66 MHz or more). */
1684 reg54 &= ~(0x1001 << dev);
1685 if(i > 2) {
1686 reg54 |= (0x1 << dev);
1687 }
1688 /* Set UDMA reference clock (133 MHz). */
1689 if(i >= 5) {
1690 reg54 |= (0x1000 << dev);
1691 }
1692 SetPciConfig2(0x54, reg54);
1693
1694 udma_ok = TRUE;
1695 idx = i+8;
1696 if(ChipFlags & ICH4_FIX) {
1697 KdPrint2((PRINT_PREFIX " ICH4_FIX udma\n"));
1698 return;
1699 }
1700 break;
1701 }
1702 }
1703
1704 if(!udma_ok) {
1705 SetPciConfig1(0x48, reg48 & ~(0x0001 << dev));
1706 if(!(ChipFlags & ICH4_FIX)) {
1707 SetPciConfig2(0x4a, (reg4a & ~(0x3 << (dev << 2))) );
1708 }
1709 SetPciConfig2(0x54, reg54 & ~(0x1001 << dev));
1710 for(i=wdmamode; i>=0; i--) {
1711 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1712 udma_ok = TRUE;
1713 idx = i+5;
1714 if(ChipFlags & ICH4_FIX) {
1715 KdPrint2((PRINT_PREFIX " ICH4_FIX wdma\n"));
1716 return;
1717 }
1718 break;
1719 }
1720 }
1721 }
1722
1723 if(!udma_ok) {
1724 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1725 idx = apiomode;
1726 }
1727
1728 GetPciConfig4(0x40, reg40);
1729 GetPciConfig1(0x44, reg44);
1730
1731 /* Allow PIO/WDMA timing controls. */
1732 reg40 &= ~0x00ff00ff;
1733 reg40 |= 0x40774077;
1734
1735 mask40 = 0x000000ff;
1736 /* Set PIO/WDMA timings. */
1737 if(!(DeviceNumber & 1)) {
1738 mask40 = 0x00003300;
1739 new40 = ((USHORT)(intel_timings[idx]) << 8);
1740 } else {
1741 mask44 = 0x0f;
1742 new44 = ((intel_timings[idx] & 0x30) >> 2) |
1743 (intel_timings[idx] & 0x03);
1744 }
1745
1746 if (Channel) {
1747 mask40 <<= 16;
1748 new40 <<= 16;
1749 mask44 <<= 4;
1750 new44 <<= 4;
1751 }
1752
1753 KdPrint2((PRINT_PREFIX " 0x40 %x/%x, 0x44 %x/%x\n", mask40, new40, mask44, new44));
1754 SetPciConfig4(0x40, (reg40 & ~mask40) | new40);
1755 SetPciConfig1(0x44, (reg44 & ~mask44) | new44);
1756
1757 return;
1758 break; }
1759 case ATA_PROMISE_ID: {
1760 /***********/
1761 /* Promise */
1762 /***********/
1763
1764 UCHAR sel66 = Channel ? 0x08: 0x02;
1765
1766 if(ChipType < PRTX) {
1767 if (isAtapi) {
1768 udmamode =
1769 wdmamode = -1;
1770 }
1771 }
1772 for(i=udmamode; i>=0; i--) {
1773
1774 if(ChipType == PRNEW) {
1775 if(i>2) {
1776 AtapiWritePortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11,
1777 AtapiReadPortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11) |
1778 sel66);
1779 } else {
1780 AtapiWritePortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11,
1781 AtapiReadPortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11) &
1782 ~sel66);
1783 }
1784 }
1785
1786 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1787 promise_timing(deviceExtension, dev, (UCHAR)(ATA_UDMA + i)); // ???
1788 return;
1789 }
1790 }
1791 if(ChipType == PRNEW) {
1792 AtapiWritePortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11,
1793 AtapiReadPortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11) &
1794 ~sel66);
1795 }
1796 for(i=wdmamode; i>=0; i--) {
1797 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1798 promise_timing(deviceExtension, dev, (UCHAR)(ATA_WDMA0+i));
1799 return;
1800 }
1801 }
1802 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1803 promise_timing(deviceExtension, dev, ATA_PIO0 + apiomode);
1804 return;
1805 break; }
1806 case ATA_ATI_ID:
1807
1808 KdPrint2((PRINT_PREFIX "ATI\n"));
1809 if(ChipType == SIIMIO) {
1810 goto l_ATA_SILICON_IMAGE_ID;
1811 }
1812 //goto ATA_SERVERWORKS_ID;
1813 // FALL THROUGH
1814
1815 //break; }
1816
1817 case ATA_SERVERWORKS_ID: {
1818 /***************/
1819 /* ServerWorks */
1820 /***************/
1821// static const ULONG udma_modes[] = { 0x70, 0x21, 0x20 };
1822 static const ULONG sw_dma_modes[] = { 0x70, 0x21, 0x20 };
1823 static const ULONG sw_pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1824 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1825 USHORT reg56;
1826 ULONG reg44;
1827 ULONG reg40;
1828 ULONG offset = dev ^ 0x01;
1829 ULONG bit_offset = offset * 8;
1830
1831 for(i=udmamode; i>=0; i--) {
1832 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1833 GetPciConfig2(0x56, reg56);
1834 reg56 &= ~(0xf << (dev * 4));
1835 reg56 |= ((USHORT)i << (dev * 4));
1836 SetPciConfig2(0x56, reg56);
1837 ChangePciConfig1(0x54, a | (0x01 << dev));
1838 // 44
1839 GetPciConfig4(0x44, reg44);
1840 reg44 = (reg44 & ~(0xff << bit_offset)) |
1841 (sw_dma_modes[2] << bit_offset);
1842 SetPciConfig4(0x44, reg44);
1843 // 40
1844 GetPciConfig4(0x40, reg40);
1845 reg40 = (reg40 & ~(0xff << bit_offset)) |
1846 (sw_pio_modes[8+i] << bit_offset);
1847 SetPciConfig4(0x40, reg40);
1848 return;
1849 }
1850 }
1851
1852 for(i=wdmamode; i>=0; i--) {
1853 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1854
1855 ChangePciConfig1(0x54, a & ~(0x01 << dev));
1856 // 44
1857 GetPciConfig4(0x44, reg44);
1858 reg44 = (reg44 & ~(0xff << bit_offset)) |
1859 (sw_dma_modes[wdmamode] << bit_offset);
1860 SetPciConfig4(0x44, reg44);
1861 // 40
1862 GetPciConfig4(0x40, reg40);
1863 reg40 = (reg40 & ~(0xff << bit_offset)) |
1864 (sw_pio_modes[5+i] << bit_offset);
1865 SetPciConfig4(0x40, reg40);
1866 return;
1867 }
1868 }
1869 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1870// SetPciConfig4(0x44, sw_pio_modes[apiomode]);
1871 if(VendorID == ATA_ATI_ID) {
1872 // special case for ATI
1873 // Seems, that PATA ATI are just re-brended ServerWorks
1874 USHORT reg4a;
1875 // 4a
1876 GetPciConfig2(0x4a, reg4a);
1877 reg4a = (reg4a & ~(0xf << (dev*4))) |
1878 (apiomode << (dev*4));
1879 SetPciConfig2(0x4a, reg4a);
1880 }
1881
1882 // 40
1883 GetPciConfig4(0x40, reg40);
1884 reg40 = (reg40 & ~(0xff << bit_offset)) |
1885 (sw_pio_modes[apiomode] << bit_offset);
1886 SetPciConfig4(0x40, reg40);
1887 return;
1888 break; }
1889 case ATA_SILICON_IMAGE_ID: {
1890l_ATA_SILICON_IMAGE_ID:
1891 /********************/
1892 /* SiliconImage/CMD */
1893 /********************/
1894 if(ChipType == SIIMIO) {
1895
1896 static const UCHAR sil_modes[7] =
1897 { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
1898 static const USHORT sil_wdma_modes[3] =
1899 { 0x2208, 0x10c2, 0x10c1 };
1900 static const USHORT sil_pio_modes[6] =
1901 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1, 0x10c1 };
1902
1903 UCHAR ureg = 0xac + ((UCHAR)DeviceNumber * 0x02) + ((UCHAR)Channel * 0x10);
1904 UCHAR uval;
1905 UCHAR mreg = Channel ? 0x84 : 0x80;
1906 UCHAR mask = DeviceNumber ? 0x30 : 0x03;
1907 UCHAR mode;
1908
1909 GetPciConfig1(ureg, uval);
1910 GetPciConfig1(mreg, mode);
1911
1912 /* enable UDMA mode */
1913 for(i = udmamode; i>=0; i--) {
1914
1915 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1916 SetPciConfig1(mreg, mode | mask);
1917 SetPciConfig1(ureg, (uval & 0x3f) | sil_modes[i]);
1918 return;
1919 }
1920 }
1921 /* enable WDMA mode */
1922 for(i = wdmamode; i>=0; i--) {
1923
1924 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1925 SetPciConfig1(mreg, mode | (mask & 0x22));
1926 SetPciConfig2(ureg - 0x4, sil_wdma_modes[i]);
1927 return;
1928 }
1929 }
1930 /* restore PIO mode */
1931 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1932
1933 SetPciConfig1(mreg, mode | (mask & 0x11));
1934 SetPciConfig2(ureg - 0x8, sil_pio_modes[apiomode]);
1935 return;
1936
1937 } else {
1938
1939 static const UCHAR cmd_modes[2][6] = {
1940 { 0x31, 0x21, 0x011, 0x25, 0x15, 0x05 },
1941 { 0xc2, 0x82, 0x042, 0x8a, 0x4a, 0x0a } };
1942 static const UCHAR cmd_wdma_modes[] = { 0x87, 0x32, 0x3f };
1943 static const UCHAR cmd_pio_modes[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
1944 ULONG treg = 0x54 + ((dev < 3) ? (dev << 1) : 7);
1945
1946 udmamode = min(udmamode, 5);
1947 /* enable UDMA mode */
1948 for(i = udmamode; i>=0; i--) {
1949 UCHAR umode;
1950
1951 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1952 GetPciConfig1(Channel ? 0x7b : 0x73, umode);
1953 umode &= ~(!(DeviceNumber & 1) ? 0x35 : 0xca);
1954 umode |= ( cmd_modes[DeviceNumber & 1][i]);
1955 SetPciConfig1(Channel ? 0x7b : 0x73, umode);
1956 return;
1957 }
1958 }
1959 /* make sure eventual UDMA mode from the BIOS is disabled */
1960 ChangePciConfig1(Channel ? 0x7b : 0x73, a & ~(!(DeviceNumber & 1) ? 0x35 : 0xca));
1961
1962 for(i = wdmamode; i>=0; i--) {
1963
1964 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1965 SetPciConfig1(treg, cmd_wdma_modes[i]);
1966 ChangePciConfig1(Channel ? 0x7b : 0x73, a & ~(!(DeviceNumber & 1) ? 0x35 : 0xca));
1967 return;
1968 }
1969 }
1970 /* set PIO mode timings */
1971 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1972
1973 SetPciConfig1(treg, cmd_pio_modes[apiomode]);
1974 ChangePciConfig1(Channel ? 0x7b : 0x73, a & ~(!(DeviceNumber & 1) ? 0x35 : 0xca));
1975 return;
1976
1977 }
1978 return;
1979 break; }
1980 case ATA_SIS_ID: {
1981 /*******/
1982 /* SiS */
1983 /*******/
1984 PULONG sis_modes = NULL;
1985 static const ULONG sis_modes_new133[] =
1986 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
1987 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
1988 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
1989 static const ULONG sis_modes_old133[] =
1990 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
1991 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
1992 static const ULONG sis_modes_old[] =
1993 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 0x0301,
1994 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
1995 static const ULONG sis_modes_new100[] =
1996 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
1997 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
1998
1999 ULONG reg = 0;
2000 UCHAR reg57;
2001 ULONG reg_size = 0;
2002 ULONG offs;
2003
2004 switch(ChipType) {
2005 case SIS133NEW:
2006 sis_modes = (PULONG)(&sis_modes_new133[0]);
2007 reg_size = 4;
2008 GetPciConfig1(0x57, reg57);
2009 reg = (reg57 & 0x40 ? 0x70 : 0x40) + (dev * 4);
2010 break;
2011 case SIS133OLD:
2012 sis_modes = (PULONG)(&sis_modes_old133[0]);
2013 reg_size = 2;
2014 reg = 0x40 + (dev * 2);
2015 break;
2016 case SIS100NEW:
2017 sis_modes = (PULONG)(&sis_modes_new100[0]);
2018 reg_size = 2;
2019 reg = 0x40 + (dev * 2);
2020 break;
2021 case SIS100OLD:
2022 case SIS66:
2023 case SIS33:
2024 sis_modes = (PULONG)(&sis_modes_old[0]);
2025 reg_size = 2;
2026 reg = 0x40 + (dev * 2);
2027 break;
2028 }
2029
2030 offs = 5+3;
2031 for(i=udmamode; i>=0; i--) {
2032 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
2033 if(reg_size == 4) {
2034 SetPciConfig4(reg, sis_modes[offs+i]);
2035 } else {
2036 SetPciConfig2(reg, (USHORT)sis_modes[offs+i]);
2037 }
2038 return;
2039 }
2040 }
2041
2042 offs = 5;
2043 for(i=wdmamode; i>=0; i--) {
2044 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
2045 if(reg_size == 4) {
2046 SetPciConfig4(reg, sis_modes[offs+i]);
2047 } else {
2048 SetPciConfig2(reg, (USHORT)sis_modes[offs+i]);
2049 }
2050 return;
2051 }
2052 }
2053 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
2054 if(reg_size == 4) {
2055 SetPciConfig4(reg, sis_modes[apiomode]);
2056 } else {
2057 SetPciConfig2(reg, (USHORT)sis_modes[apiomode]);
2058 }
2059 return;
2060 break; }
2061 case 0x16ca:
2062 /* Cenatek Rocket Drive controller */
2063 if (wdmamode >= 0 &&
2064 (AtapiReadPort1(chan, IDX_BM_Status) &
2065 (DeviceNumber ? BM_STATUS_DRIVE_1_DMA : BM_STATUS_DRIVE_0_DMA))) {
2066 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + wdmamode);
2067 } else {
2068 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
2069 }
2070 return;
2071 case ATA_ITE_ID: { /* ITE IDE controller */
2072
2073 if(ChipType == ITE_33) {
2074 int a_speed = 3 << (dev * 4);
2075 int u_flag = 1 << dev;
2076 int u_speed = 0;
2077 int pio = 1;
2078 UCHAR reg48, reg4a;
2079 USHORT drive_enables;
2080 ULONG drive_timing;
2081
2082 GetPciConfig1(0x48, reg48);
2083 GetPciConfig1(0x4a, reg4a);
2084
2085 /*
2086 * Setting the DMA cycle time to 2 or 3 PCI clocks (60 and 91 nsec
2087 * at 33 MHz PCI clock) seems to cause BadCRC errors during DMA
2088 * transfers on some drives, even though both numbers meet the minimum
2089 * ATAPI-4 spec of 73 and 54 nsec for UDMA 1 and 2 respectively.
2090 * So the faster times are just commented out here. The good news is
2091 * that the slower cycle time has very little affect on transfer
2092 * performance.
2093 */
2094
2095 for(i=udmamode; i>=0; i--) {
2096 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
2097 SetPciConfig1(0x48, reg48 | u_flag);
2098 reg4a &= ~a_speed;
2099 SetPciConfig1(0x4a, reg4a | u_speed);
2100 pio = 4;
2101 goto setup_drive_ite;
2102 }
2103 }
2104
2105 for(i=wdmamode; i>=0; i--) {
2106 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
2107 SetPciConfig1(0x48, reg48 & ~u_flag);
2108 SetPciConfig1(0x4a, reg4a & ~a_speed);
2109 pio = 3;
2110 return;
2111 }
2112 }
2113 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
2114 SetPciConfig1(0x48, reg48 & ~u_flag);
2115 SetPciConfig1(0x4a, reg4a & ~a_speed);
2116
2117 pio = apiomode;
2118
2119setup_drive_ite:
2120
2121 GetPciConfig2(0x40, drive_enables);
2122 GetPciConfig4(0x44, drive_timing);
2123
2124 /*
2125 * FIX! The DIOR/DIOW pulse width and recovery times in port 0x44
2126 * are being left at the default values of 8 PCI clocks (242 nsec
2127 * for a 33 MHz clock). These can be safely shortened at higher
2128 * PIO modes. The DIOR/DIOW pulse width and recovery times only
2129 * apply to PIO modes, not to the DMA modes.
2130 */
2131
2132 /*
2133 * Enable port 0x44. The IT8172G spec is confused; it calls
2134 * this register the "Slave IDE Timing Register", but in fact,
2135 * it controls timing for both master and slave drives.
2136 */
2137 drive_enables |= 0x4000;
2138
2139 drive_enables &= (0xc000 | (0x06 << (DeviceNumber*4)));
2140 if (pio > 1) {
2141 /* enable prefetch and IORDY sample-point */
2142 drive_enables |= (0x06 << (DeviceNumber*4));
2143 }
2144
2145 SetPciConfig2(0x40, drive_enables);
2146 } else
2147 if(ChipType == ITE_133) {
2148 static const UCHAR udmatiming[] =
2149 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
2150 static const UCHAR chtiming[] =
2151 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
2152 ULONG offset = (Channel<<2) + DeviceNumber;
2153 UCHAR reg54;
2154
2155 for(i=udmamode; i>=0; i--) {
2156 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
2157 ChangePciConfig1(0x50, a & ~(1 << (dev + 3)) );
2158 SetPciConfig1(0x56 + offset, udmatiming[i]);
2159 return;
2160 }
2161 }
2162
2163 for(i=wdmamode; i>=0; i--) {
2164 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
2165
2166 ChangePciConfig1(0x50, a | (1 << (dev + 3)) );
2167 GetPciConfig1(0x54 + offset, reg54);
2168 if(reg54 < chtiming[i+5]) {
2169 SetPciConfig1(0x54 + offset, chtiming[i+5]);
2170 }
2171 return;
2172 }
2173 }
2174 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
2175 ChangePciConfig1(0x50, a | (1 << (dev + 3)) );
2176 GetPciConfig1(0x54 + offset, reg54);
2177 if(reg54 < chtiming[apiomode]) {
2178 SetPciConfig1(0x54 + offset, chtiming[apiomode]);
2179 }
2180 return;
2181 } else
2182 if(ChipType == ITE_133_NEW) {
2183 //static const USHORT reg54_timings[] = { 0x0000, 0x0000, 0x0001, 0x0001, 0x0001, 0x1001, 0x1001 };
2184 static const UCHAR udmatiming[] =
2185 { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 };
2186 static const UCHAR timings[] =
2187 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
2188 0x23, 0x23, 0x23, 0x23, 0x23, 0x02, 0x02 };
2189 BOOLEAN udma_ok = FALSE;
2190 BOOLEAN ok = FALSE;
2191 UCHAR timing = 0;
2192
2193 WCHAR reg40;
2194 UCHAR reg44;
2195 USHORT reg4a;
2196 USHORT reg54;
2197 USHORT mask40=0, new40=0;
2198 UCHAR mask44=0, new44=0;
2199
2200 GetPciConfig2(0x40, reg40);
2201 GetPciConfig1(0x44, reg44);
2202 GetPciConfig2(0x4a, reg4a);
2203 GetPciConfig2(0x54, reg54);
2204
2205 if(!(reg54 & (0x10 << dev))) {
2206 // 80-pin check
2207 udmamode = min(udmamode, 2);
2208 }
2209
2210 for(i=udmamode; i>=0; i--) {
2211 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
2212 ChangePciConfig1(0x48, a | (1 << dev) );
2213 ChangePciConfig2(0x4a,
2214 (a & ~(0x3 << (dev*4))) |
2215 (udmatiming[i] << (dev*4)) );
2216 ok=TRUE;
2217 udma_ok=TRUE;
2218 timing = timings[i+8];
2219 break;
2220 }
2221 }
2222
2223 for(i=wdmamode; !ok && i>=0; i--) {
2224 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
2225
2226 ok=TRUE;
2227 timing = timings[i+5];
2228 break;
2229 }
2230 }
2231
2232 if(!ok) {
2233 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
2234 timing = timings[apiomode];
2235 }
2236
2237 if(!udma_ok) {
2238 ChangePciConfig1(0x48, a & ~(1 << dev) );
2239 ChangePciConfig2(0x4a, a & ~(0x3 << (dev << 2)) );
2240 }
2241 if (udma_ok && udmamode >= ATA_UDMA2) {
2242 reg54 |= (0x1 << dev);
2243 } else {
2244 reg54 &= ~(0x1 << dev);
2245 }
2246 if (udma_ok && udmamode >= ATA_UDMA5) {
2247 reg54 |= (0x1000 << dev);
2248 } else {
2249 reg54 &= ~(0x1000 << dev);
2250 }
2251 SetPciConfig2(0x54, reg54 );
2252
2253 reg40 &= 0xff00;
2254 reg40 |= 0x4033;
2255
2256 if(!(DeviceNumber & 1)) {
2257 reg40 |= (isAtapi ? 0x04 : 0x00);
2258 mask40 = 0x3300;
2259 new40 = timing << 8;
2260 } else {
2261 reg40 |= (isAtapi ? 0x40 : 0x00);
2262 mask44 = 0x0f;
2263 new44 = ((timing & 0x30) >> 2) |
2264 (timing & 0x03);
2265 }
2266 SetPciConfig2(0x40, (reg40 & ~mask40) | new40);
2267 SetPciConfig1(0x44, (reg44 & ~mask44) | new44);
2268 return;
2269 }
2270
2271 return;
2272 break; }
2273 case 0x3388:
2274 /* HiNT Corp. VXPro II EIDE */
2275 if (wdmamode >= 0 &&
2276 (AtapiReadPort1(chan, IDX_BM_Status) &
2277 (DeviceNumber ? BM_STATUS_DRIVE_1_DMA : BM_STATUS_DRIVE_0_DMA))) {
2278 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_DMA);
2279 } else {
2280 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
2281 }
2282 return;
2283 case ATA_JMICRON_ID: {
2284
2285 UCHAR reg40;
2286 GetPciConfig1(0x40, reg40);
2287
2288 /*
2289 This is done on chip-init phase
2290 if(reg40 & 0x08) {
2291 // 80-pin check
2292 udmamode = min(udmamode, 2);
2293 }
2294 */
2295 /* Nothing to do to setup mode, the controller snoop SET_FEATURE cmd. */
2296 if(apiomode >= 4)
2297 apiomode = 4;
2298 for(i=udmamode; i>=0; i--) {
2299 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
2300 return;
2301 }
2302 }
2303 for(i=wdmamode; i>=0; i--) {
2304 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
2305 return;
2306 }
2307 }
2308 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode)) {
2309 return;
2310 }
2311 return;
2312 break; }
2313 }
2314
2315try_generic_dma:
2316
2317 /* unknown controller chip */
2318
2319 /* better not try generic DMA on ATAPI devices it almost never works */
2320 if (isAtapi) {
2321 KdPrint2((PRINT_PREFIX "ATAPI on unknown controller -> PIO\n"));
2322 udmamode =
2323 wdmamode = -1;
2324 }
2325
2326 /* if controller says its setup for DMA take the easy way out */
2327 /* the downside is we dont know what DMA mode we are in */
2328 if ((udmamode >= 0 || /*wdmamode > 1*/ wdmamode >= 0) &&
2329 /*deviceExtension->BaseIoAddressBM[lChannel]*/ (deviceExtension->BusMaster==DMA_MODE_BM) &&
2330 (GetDmaStatus(deviceExtension, lChannel) &
2331 (!(DeviceNumber & 1) ?
2332 BM_STATUS_DRIVE_0_DMA : BM_STATUS_DRIVE_1_DMA))) {
2333// LunExt->TransferMode = ATA_DMA;
2334// return;
2335 KdPrint2((PRINT_PREFIX "try DMA on unknown controller\n"));
2336 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_DMA)) {
2337 return;
2338 }
2339 }
2340
2341#if 0
2342 /* well, we have no support for this, but try anyways */
2343 if ((wdmamode >= 0 && apiomode >= 4) && deviceExtension->BaseIoAddressBM[lChannel]) {
2344 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_DMA/* + wdmamode*/)) {
2345 return;
2346 }
2347 }
2348#endif
2349
2350 KdPrint2((PRINT_PREFIX "try PIO%d on unknown controller\n", apiomode));
2351 if(!AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode)) {
2352 KdPrint2((PRINT_PREFIX "fall to PIO on unknown controller\n"));
2353 LunExt->TransferMode = ATA_PIO;
2354 }
2355 return;
2356} // end AtapiDmaInit()
reg_size
static const unsigned char reg_size[]
Definition: amd64_sup.c:21
GetStatus
#define GetStatus(BaseIoAddress, Status)
Definition: atapi.h:328
ok
#define ok(value,...)
Definition: atltest.h:57
CYRIX_35
#define CYRIX_35
Definition: bm_devs_decl.h:720
ATPOLD
#define ATPOLD
Definition: bm_devs_decl.h:634
ALIOLD
#define ALIOLD
Definition: bm_devs_decl.h:636
ATA_ACARD_ID
#define ATA_ACARD_ID
Definition: bm_devs_decl.h:111
ICH4_FIX
#define ICH4_FIX
Definition: bm_devs_decl.h:690
ATA_ISCH
#define ATA_ISCH
Definition: bm_devs_decl.h:311
CYRIX_3x
#define CYRIX_3x
Definition: bm_devs_decl.h:718
ATA_NETCELL_ID
#define ATA_NETCELL_ID
Definition: bm_devs_decl.h:352
ATA_I82371FB
#define ATA_I82371FB
Definition: bm_devs_decl.h:186
ATA_MARVELL_ID
#define ATA_MARVELL_ID
Definition: bm_devs_decl.h:327
ATA_CYPRESS_ID
#define ATA_CYPRESS_ID
Definition: bm_devs_decl.h:171
ATA_NATIONAL_ID
#define ATA_NATIONAL_ID
Definition: bm_devs_decl.h:349
SetPciConfig4
#define SetPciConfig4(offs, op)
Definition: bsmaster.h:1688
BM_STATUS_DRIVE_0_DMA
#define BM_STATUS_DRIVE_0_DMA
Definition: bsmaster.h:146
BM_STATUS_DRIVE_1_DMA
#define BM_STATUS_DRIVE_1_DMA
Definition: bsmaster.h:147
GetDmaStatus
#define GetDmaStatus(de, c)
Definition: bsmaster.h:1711
DMA_MODE_BM
#define DMA_MODE_BM
Definition: bsmaster.h:1707
idx
unsigned int idx
Definition: utils.c:41
mask
GLenum GLint GLuint mask
Definition: glext.h:6028
mode
GLenum mode
Definition: glext.h:6217
offset
GLintptr offset
Definition: glext.h:5920
IDE_STATUS_ERROR
#define IDE_STATUS_ERROR
Definition: hwide.h:110
ATA_PIO
#define ATA_PIO
Definition: hwide.h:161
IDE_STATUS_IDLE
#define IDE_STATUS_IDLE
Definition: hwide.h:118
reg
static int reg
Definition: i386-dis.c:1290
hpt_timing
VOID NTAPI hpt_timing(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG dev, IN CHAR mode)
Definition: id_dma.cpp:2536
via82c_timing
VOID NTAPI via82c_timing(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG dev, IN CHAR mode)
Definition: id_dma.cpp:2681
AtaSetTransferMode
BOOLEAN NTAPI AtaSetTransferMode(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PHW_LU_EXTENSION LunExt, IN ULONG mode)
Definition: id_dma.cpp:892
promise_timing
VOID NTAPI promise_timing(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG dev, IN CHAR mode)
Definition: id_dma.cpp:2391
UniataIsSATARangeAvailable
__inline BOOLEAN UniataIsSATARangeAvailable(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG lChannel)
Definition: id_sata.h:91
_HW_CHANNEL::last_cdev
ULONG last_cdev
Definition: bsmaster.h:1023
_HW_DEVICE_EXTENSION::BusMaster
BOOLEAN BusMaster
Definition: bsmaster.h:1263
_HW_LU_EXTENSION
Definition: atapi.c:163
_HW_LU_EXTENSION::DeviceFlags
ULONG DeviceFlags
Definition: bsmaster.h:1164
_HW_LU_EXTENSION::TransferMode
UCHAR TransferMode
Definition: bsmaster.h:1171
_HW_LU_EXTENSION::IdentifyData
IDENTIFY_DATA2 IdentifyData
Definition: bsmaster.h:1162
_HW_LU_EXTENSION::LimitedTransferMode
UCHAR LimitedTransferMode
Definition: bsmaster.h:1172
_HW_LU_EXTENSION::OrigTransferMode
UCHAR OrigTransferMode
Definition: bsmaster.h:1173
PULONG
uint32_t * PULONG
Definition: typedefs.h:59
IDENTIFY_CABLE_ID_VALID
#define IDENTIFY_CABLE_ID_VALID
Definition: atapi.h:844
ATA_WDMA0
#define ATA_WDMA0
Definition: atapi.h:323
ATA_DMA
#define ATA_DMA
Definition: atapi.h:316
ATA_PIO4
#define ATA_PIO4
Definition: atapi.h:313
ATAPI_DEVICE
#define ATAPI_DEVICE(chan, dev)
Definition: atapi.h:1624
ATA_WDMA2
#define ATA_WDMA2
Definition: atapi.h:325
UniataIsIdle
UCHAR DDKFASTAPI UniataIsIdle(IN struct _HW_DEVICE_EXTENSION *deviceExtension, IN UCHAR Status)
Definition: id_ata.cpp:742
SelectDrive
UCHAR DDKFASTAPI SelectDrive(IN struct _HW_CHANNEL *chan, IN ULONG DeviceNumber)
ATA_UDMA3
#define ATA_UDMA3
Definition: atapi.h:331
ATA_WDMA
#define ATA_WDMA
Definition: atapi.h:322
ATA_UDMA
#define ATA_UDMA
Definition: atapi.h:327
ATA_UDMA0
#define ATA_UDMA0
Definition: atapi.h:328
ata_is_sata
__inline BOOLEAN ata_is_sata(PIDENTIFY_DATA ident)
Definition: atapi.h:1636
ATA_PIO0
#define ATA_PIO0
Definition: atapi.h:309
ATA_PIO3
#define ATA_PIO3
Definition: atapi.h:312
timing
static int timing
Definition: xmllint.c:163
WCHAR
__wchar_t WCHAR
Definition: xmlstorage.h:180
CHAR
char CHAR
Definition: xmlstorage.h:175

Referenced by AtapiDmaInit__(), and AtapiDmaReinit().

◆ AtapiDmaInit__()

VOID NTAPI AtapiDmaInit__ ( IN PHW_DEVICE_EXTENSION  deviceExtension,
IN PHW_LU_EXTENSION  LunExt 
)

Definition at line 857 of file id_dma.cpp.

861{
862 if(LunExt->IdentifyData.SupportDma ||
863 (LunExt->IdentifyData.AtapiDMA.DMASupport && (LunExt->DeviceFlags & DFLAGS_ATAPI_DEVICE))) {
864 KdPrint2((PRINT_PREFIX
865 "AtapiDmaInit__: Set (U)DMA on Device %d\n", LunExt->Lun));
866/* for(i=AtaUmode(&(LunExt->IdentifyData)); i>=0; i--) {
867 AtapiDmaInit(deviceExtension, ldev & 1, ldev >> 1,
868 (CHAR)AtaPioMode(&(LunExt->IdentifyData)),
869 (CHAR)AtaWmode(&(LunExt->IdentifyData)),
870 UDMA_MODE0+(CHAR)i );
871 }
872 for(i=AtaWmode(&(LunExt->IdentifyData)); i>=0; i--) {
873 AtapiDmaInit(deviceExtension, ldev & 1, ldev >> 1,
874 (CHAR)AtaPioMode(&(LunExt->IdentifyData)),
875 (CHAR)AtaWmode(&(LunExt->IdentifyData)),
876 UDMA_MODE0+(CHAR)i );
877 }*/
878 AtapiDmaInit(deviceExtension, LunExt->Lun, LunExt->chan->lChannel,
879 (CHAR)AtaPioMode(&(LunExt->IdentifyData)),
880 (CHAR)AtaWmode(&(LunExt->IdentifyData)),
881 (CHAR)AtaUmode(&(LunExt->IdentifyData)) );
882 } else {
883 KdPrint2((PRINT_PREFIX
884 "AtapiDmaInit__: Set PIO on Device %d\n", LunExt->Lun));
885 AtapiDmaInit(deviceExtension, LunExt->Lun, LunExt->chan->lChannel,
886 (CHAR)AtaPioMode(&(LunExt->IdentifyData)), -1, -1);
887 }
888} // end AtapiDmaInit__()
DFLAGS_ATAPI_DEVICE
#define DFLAGS_ATAPI_DEVICE
Definition: atapi.h:41
AtapiDmaInit
VOID NTAPI AtapiDmaInit(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN SCHAR apiomode, IN SCHAR wdmamode, IN SCHAR udmamode)
Definition: id_dma.cpp:975
AtaWmode
LONG NTAPI AtaWmode(PIDENTIFY_DATA2 ident)
Definition: id_ata.cpp:1241
AtaPioMode
LONG NTAPI AtaPioMode(PIDENTIFY_DATA2 ident)
Definition: id_ata.cpp:1220
AtaUmode
LONG NTAPI AtaUmode(PIDENTIFY_DATA2 ident)
Definition: id_ata.cpp:1254

Referenced by AtapiDmaReinit(), AtapiHwInitialize__(), and AtapiStartIo__().

◆ AtapiDmaPioSync()

BOOLEAN NTAPI AtapiDmaPioSync ( PVOID  HwDeviceExtension,
PSCSI_REQUEST_BLOCK  Srb,
PUCHAR  data,
ULONG  count 
)

Definition at line 467 of file id_dma.cpp.

473{
474#ifndef USE_OWN_DMA
475 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
476 ULONG dma_base;
477 PUCHAR DmaBuffer;
478 ULONG dma_count;
479 ULONG len;
480 PATA_REQ AtaReq;
481
482 // This must never be called after DMA operation !!!
483 KdPrint2((PRINT_PREFIX "AtapiDmaPioSync: data %#x, len %#x\n", data, count));
484
485 if(!Srb) {
486 KdPrint2((PRINT_PREFIX "AtapiDmaPioSync: !Srb\n" ));
487 return FALSE;
488 }
489
490 AtaReq = (PATA_REQ)(Srb->SrbExtension);
491
492 // do nothing on PCI (This can be changed. We cannot guarantee,
493 // that CommonBuffer will always point to User's buffer,
494 // however, this usually happens on PCI-32)
495 if(deviceExtension->OrigAdapterInterfaceType == PCIBus) {
496 return TRUE;
497 }
498 // do nothing for DMA
499 if(AtaReq->Flags & REQ_FLAG_DMA_OPERATION) {
500 return TRUE;
501 }
502
503 if(!data) {
504 KdPrint2((PRINT_PREFIX "AtapiDmaPioSync: !data\n" ));
505 return FALSE;
506 }
507
508 while(count) {
509 dma_base = AtapiVirtToPhysAddr(HwDeviceExtension, Srb, data, &dma_count);
510 if(!dma_base) {
511 KdPrint2((PRINT_PREFIX "AtapiDmaPioSync: !dma_base for data %#x\n", data));
512 return FALSE;
513 }
514 DmaBuffer = (PUCHAR)ScsiPortGetVirtualAddress(HwDeviceExtension,
515 ScsiPortConvertUlongToPhysicalAddress(dma_base));
516 if(!DmaBuffer) {
517 KdPrint2((PRINT_PREFIX "AtapiDmaPioSync: !DmaBuffer for dma_base %#x\n", dma_base));
518 return FALSE;
519 }
520 len = min(dma_count, count);
521 memcpy(DmaBuffer, data, len);
522 count -= len;
523 data += len;
524 }
525#endif //USE_OWN_DMA
526
527 return TRUE;
528} // end AtapiDmaPioSync()
ScsiPortConvertUlongToPhysicalAddress
SCSI_PHYSICAL_ADDRESS NTAPI ScsiPortConvertUlongToPhysicalAddress(IN ULONG_PTR UlongAddress)
Definition: scsiport.c:529
ScsiPortGetVirtualAddress
PVOID NTAPI ScsiPortGetVirtualAddress(IN PVOID HwDeviceExtension, IN SCSI_PHYSICAL_ADDRESS PhysicalAddress)
Definition: scsiport.c:821
REQ_FLAG_DMA_OPERATION
#define REQ_FLAG_DMA_OPERATION
Definition: bsmaster.h:932
count
GLuint GLuint GLsizei count
Definition: gl.h:1545
data
GLint GLenum GLsizei GLsizei GLsizei GLint GLsizei const GLvoid * data
Definition: gl.h:1950
len
GLenum GLsizei len
Definition: glext.h:6722
PCIBus
@ PCIBus
Definition: hwresource.cpp:142
memcpy
#define memcpy(s1, s2, n)
Definition: mkisofs.h:878
DmaBuffer
@ DmaBuffer
Definition: strmini.h:276
_HW_DEVICE_EXTENSION::OrigAdapterInterfaceType
INTERFACE_TYPE OrigAdapterInterfaceType
Definition: bsmaster.h:1315

Referenced by AtapiInterrupt__().

◆ AtapiDmaReinit()

VOID NTAPI AtapiDmaReinit ( IN PHW_DEVICE_EXTENSION  deviceExtension,
IN PHW_LU_EXTENSION  LunExt,
IN PATA_REQ  AtaReq 
)

(LunExt->DeviceFlags & DFLAGS_FORCE_DOWNRATE) &&

Definition at line 754 of file id_dma.cpp.

759{
760 SCHAR apiomode;
761
762 if((deviceExtension->HwFlags & UNIATA_AHCI) &&
763 !(LunExt->DeviceFlags & DFLAGS_ATAPI_DEVICE)) {
764 // skip unnecessary checks
765 KdPrint2((PRINT_PREFIX "AtapiDmaReinit: ahci, nothing to do for HDD\n"));
766 return;
767 }
768
769 apiomode = (CHAR)AtaPioMode(&(LunExt->IdentifyData));
770
771 if(!(AtaReq->Flags & REQ_FLAG_DMA_OPERATION)) {
772 KdPrint2((PRINT_PREFIX
773 "AtapiDmaReinit: !(AtaReq->Flags & REQ_FLAG_DMA_OPERATION), fall to PIO on Device %d\n", LunExt->Lun));
774 goto limit_pio;
775 }
776 if(deviceExtension->HwFlags & UNIATA_AHCI) {
777 if(!AtaReq->ahci.ahci_base64) {
778 KdPrint2((PRINT_PREFIX
779 "AtapiDmaReinit: no AHCI PRD, fatal on Device %d\n", LunExt->Lun));
780 goto exit;
781 }
782 } else
783 if(!AtaReq->ata.dma_base) {
784 KdPrint2((PRINT_PREFIX
785 "AtapiDmaReinit: no PRD, fall to PIO on Device %d\n", LunExt->Lun));
786 goto limit_pio;
787 }
788
789 if((deviceExtension->HbaCtrlFlags & HBAFLAGS_DMA_DISABLED_LBA48) &&
790 (AtaReq->lba >= (LONGLONG)ATA_MAX_LBA28) &&
791 (LunExt->TransferMode > ATA_PIO5) ) {
792 KdPrint2((PRINT_PREFIX
793 "AtapiDmaReinit: FORCE_DOWNRATE on Device %d for LBA48\n", LunExt->Lun));
794 goto limit_lba48;
795 }
796
797
798 if(AtaReq->Flags & REQ_FLAG_FORCE_DOWNRATE) {
799 KdPrint2((PRINT_PREFIX
800 "AtapiDmaReinit: FORCE_DOWNRATE on Device %d\n", LunExt->Lun));
801 if(AtaReq->lba >= (LONGLONG)ATA_MAX_LBA28) {
802limit_lba48:
803 LunExt->DeviceFlags |= REQ_FLAG_FORCE_DOWNRATE_LBA48;
804limit_pio:
805 // do not make extra work if we already use PIO
806 if(/*LunExt->TransferMode >= ATA_DMA*/
807 (LunExt->TransferMode > ATA_PIO5) && (LunExt->TransferMode != ATA_PIO0+apiomode)
808 ) {
809 KdPrint2((PRINT_PREFIX
810 "AtapiDmaReinit: set PIO mode on Device %d (%x -> %x)\n", LunExt->Lun, LunExt->TransferMode, ATA_PIO0+apiomode));
811 AtapiDmaInit(deviceExtension, LunExt->Lun, LunExt->chan->lChannel,
812 apiomode,
813 -1,
814 -1 );
815 } else
816 if(LunExt->LimitedTransferMode < LunExt->TransferMode) {
817 KdPrint2((PRINT_PREFIX
818 "AtapiDmaReinit: set PIO mode on Device %d (%x -> %x) (2)\n", LunExt->Lun, LunExt->TransferMode, LunExt->LimitedTransferMode));
819 AtapiDmaInit(deviceExtension, LunExt->Lun, LunExt->chan->lChannel,
820 LunExt->LimitedTransferMode-ATA_PIO0,
821 -1,
822 -1 );
823 }
824
825 } else {
826 KdPrint2((PRINT_PREFIX
827 "AtapiDmaReinit: set MAX mode on Device %d\n", LunExt->Lun));
828 AtapiDmaInit(deviceExtension, LunExt->Lun, LunExt->chan->lChannel,
829 apiomode,
830 min( retry_Wdma[AtaReq->retry],
831 (CHAR)AtaWmode(&(LunExt->IdentifyData)) ),
832 min( retry_Udma[AtaReq->retry],
833 (CHAR)AtaUmode(&(LunExt->IdentifyData)) ) );
834 }
835// LunExt->DeviceFlags &= ~DFLAGS_FORCE_DOWNRATE;
836 } else
837 if(
838 (LunExt->LimitedTransferMode >
839 LunExt->TransferMode) ||
840 (LunExt->DeviceFlags & DFLAGS_REINIT_DMA) ||
841 ((deviceExtension->HwFlags & UNIATA_CHAN_TIMINGS) && ((ULONG)LunExt->Lun != LunExt->chan->last_cdev))) {
842 // restore IO mode
843 KdPrint2((PRINT_PREFIX
844 "AtapiDmaReinit: restore IO mode on Device %d, last dev %d\n", LunExt->Lun, LunExt->chan->last_cdev));
845 AtapiDmaInit__(deviceExtension, LunExt);
846 } else {
847 KdPrint2((PRINT_PREFIX
848 "AtapiDmaReinit: LimitedTransferMode == TransferMode = %x (%x), Device %d, last dev %d\n", LunExt->TransferMode, LunExt->DeviceFlags, LunExt->Lun, LunExt->chan->last_cdev));
849 }
850
851exit:
852 return;
853} // end AtapiDmaReinit()
CHAR
#define CHAR(Char)
UNIATA_CHAN_TIMINGS
#define UNIATA_CHAN_TIMINGS
Definition: bm_devs_decl.h:631
REQ_FLAG_FORCE_DOWNRATE
#define REQ_FLAG_FORCE_DOWNRATE
Definition: bsmaster.h:931
ATA_MAX_LBA28
#define ATA_MAX_LBA28
Definition: bsmaster.h:95
REQ_FLAG_FORCE_DOWNRATE_LBA48
#define REQ_FLAG_FORCE_DOWNRATE_LBA48
Definition: bsmaster.h:937
HBAFLAGS_DMA_DISABLED_LBA48
#define HBAFLAGS_DMA_DISABLED_LBA48
Definition: bsmaster.h:1359
AtapiDmaInit__
VOID NTAPI AtapiDmaInit__(IN PHW_DEVICE_EXTENSION deviceExtension, IN PHW_LU_EXTENSION LunExt)
Definition: id_dma.cpp:857
retry_Udma
static const CHAR retry_Udma[MAX_RETRIES+1]
Definition: id_dma.cpp:54
retry_Wdma
static const CHAR retry_Wdma[MAX_RETRIES+1]
Definition: id_dma.cpp:53
exit
#define exit(n)
Definition: config.h:202
SCHAR
signed char SCHAR
Definition: sqltypes.h:14
LONGLONG
int64_t LONGLONG
Definition: typedefs.h:68
ATA_PIO5
#define ATA_PIO5
Definition: atapi.h:314
DFLAGS_REINIT_DMA
#define DFLAGS_REINIT_DMA
Definition: atapi.h:252

Referenced by AtapiSendCommand(), and IdeReadWrite().

◆ AtapiDmaSetup()

BOOLEAN NTAPI AtapiDmaSetup ( IN PVOID  HwDeviceExtension,
IN ULONG  DeviceNumber,
IN ULONG  lChannel,
IN PSCSI_REQUEST_BLOCK  Srb,
IN PUCHAR  data,
IN ULONG  count 
)

Definition at line 247 of file id_dma.cpp.

255{
256 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
257 ULONG dma_count, dma_base, dma_baseu;
258 ULONG dma_count0, dma_base0;
259 ULONG i;
260 PHW_CHANNEL chan = &(deviceExtension->chan[lChannel]);
261 PATA_REQ AtaReq = (PATA_REQ)(Srb->SrbExtension);
262 BOOLEAN use_DB_IO = FALSE;
263 BOOLEAN use_AHCI = (deviceExtension->HwFlags & UNIATA_AHCI) ? TRUE : FALSE;
264 ULONG orig_count = count;
265 ULONG max_entries = use_AHCI ? ATA_AHCI_DMA_ENTRIES : ATA_DMA_ENTRIES;
266 //ULONG max_frag = use_AHCI ? (0x3fffff+1) : (4096); // DEBUG, replace 4096 for proper chipset-specific value
267 ULONG max_frag = deviceExtension->DmaSegmentLength;
268 ULONG seg_align = deviceExtension->DmaSegmentAlignmentMask;
269
270 if(AtaReq->dma_entries) {
271 AtaReq->Flags |= REQ_FLAG_DMA_OPERATION;
272 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: already setup, %d entries\n", AtaReq->dma_entries));
273 return TRUE;
274 }
275 AtaReq->ata.dma_base = 0;
276 AtaReq->Flags &= ~REQ_FLAG_DMA_OPERATION;
277
278 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: mode %#x, data %x, count %x, lCh %x, dev %x\n",
279 chan->lun[DeviceNumber]->TransferMode,
280 data, count, lChannel, DeviceNumber ));
281 if(chan->lun[DeviceNumber]->TransferMode < ATA_DMA) {
282 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: Not DMA mode, assume this is just preparation\n" ));
283 //return FALSE;
284 }
285 //KdPrint2((PRINT_PREFIX " checkpoint 1\n" ));
286 if(!count) {
287 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: count=0\n" ));
288 return FALSE;
289 }
290 //KdPrint2((PRINT_PREFIX " checkpoint 2\n" ));
291 if(count > deviceExtension->MaximumDmaTransferLength) {
292 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: deviceExtension->MaximumDmaTransferLength > count\n" ));
293 return FALSE;
294 }
295 //KdPrint2((PRINT_PREFIX " checkpoint 3\n" ));
296 if((ULONG_PTR)data & deviceExtension->AlignmentMask) {
297 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: unaligned data: %#x (%#x)\n", data, deviceExtension->AlignmentMask));
298 return FALSE;
299 }
300
301 //KdPrint2((PRINT_PREFIX " checkpoint 4\n" ));
302 if(use_AHCI) {
303 KdPrint2((PRINT_PREFIX " get Phys(AHCI_CMD=%x)\n", AtaReq->ahci.ahci_cmd_ptr ));
304 dma_base = AtapiVirtToPhysAddr(HwDeviceExtension, NULL, (PUCHAR)(AtaReq->ahci.ahci_cmd_ptr), &i, &dma_baseu);
305 AtaReq->ahci.ahci_base64 = 0; // clear before setup
306 } else {
307 KdPrint2((PRINT_PREFIX " get Phys(PRD=%x)\n", &(AtaReq->dma_tab) ));
308 dma_base = AtapiVirtToPhysAddr(HwDeviceExtension, NULL, (PUCHAR)&(AtaReq->dma_tab) /*chan->dma_tab*/, &i, &dma_baseu);
309 }
310 if(dma_baseu && i) {
311 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: SRB built-in PRD above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base));
312 if(!deviceExtension->Host64) {
313 dma_base = chan->DB_PRD_PhAddr;
314 AtaReq->Flags |= REQ_FLAG_DMA_DBUF_PRD;
315 i = 1;
316 }
317 } else
318 if(!dma_base || !i || ((LONG)(dma_base) == -1)) {
319 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: No BASE\n" ));
320 return FALSE;
321 }
322 AtaReq->ata.dma_base = dma_base; // aliased to AtaReq->ahci.ahci_base64
323
324 KdPrint2((PRINT_PREFIX " get Phys(data[0]=%x)\n", data ));
325 dma_base = AtapiVirtToPhysAddr(HwDeviceExtension, Srb, data, &dma_count, &dma_baseu);
326 if(dma_baseu && dma_count) {
327 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: 1st block of buffer above 4Gb: %8.8x%8.8x cnt=%x\n", dma_baseu, dma_base, dma_count));
328 if(!deviceExtension->Host64) {
329retry_DB_IO:
330 use_DB_IO = TRUE;
331 dma_base = chan->DB_IO_PhAddr;
332 data = (PUCHAR)(chan->DB_IO);
333 } else {
334 AtaReq->ahci.ahci_base64 = (ULONGLONG)dma_base | ((ULONGLONG)dma_baseu << 32);
335 }
336 } else
337 if(!dma_count || ((LONG)(dma_base) == -1)) {
338 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: No 1st block\n" ));
339 //AtaReq->dma_base = NULL;
340 AtaReq->ahci.ahci_base64 = NULL;
341 return FALSE;
342 }
343
344 dma_count = min(count, (PAGE_SIZE - ((ULONG_PTR)data & PAGE_MASK)));
345 data += dma_count;
346 count -= dma_count;
347 i = 0;
348
349 dma_count0 = dma_count;
350 dma_base0 = dma_base;
351
352 while (count) {
353/* KdPrint2((PRINT_PREFIX " segments %#x+%#x == %#x && %#x+%#x <= %#x\n",
354 dma_base0, dma_count0, dma_base,
355 dma_count0, dma_count, max_frag));*/
356 if(dma_base0+dma_count0 == dma_base &&
357 dma_count0+dma_count <= max_frag) {
358 // 'i' should be always > 0 here
359 // for BM we cannot cross 64k boundary
360 if(dma_base & seg_align) {
361 //KdPrint2((PRINT_PREFIX " merge segments\n" ));
362 ASSERT(i);
363 //BrutePoint();
364 i--;
365 dma_base = dma_base0;
366 dma_count += dma_count0;
367 }
368 }
369 if(use_AHCI) {
370 AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].base = dma_base;
371 AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].baseu = dma_baseu;
372 AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].Reserved1 = 0;
373 *((PULONG)&(AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].DBC_ULONG)) = ((dma_count-1) & 0x3fffff);
374/* AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].Reserved2 = 0;
375 AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].I = 0;*/
376 KdPrint2((PRINT_PREFIX " ph data[%d]=%x:%x (%x)\n", i, dma_baseu, dma_base, AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].DBC));
377 } else {
378 AtaReq->dma_tab[i].base = dma_base;
379 AtaReq->dma_tab[i].count = (dma_count & 0xffff);
380 }
381 dma_count0 = dma_count;
382 dma_base0 = dma_base;
383 i++;
384 if (i >= max_entries) {
385 KdPrint2((PRINT_PREFIX "too many segments in DMA table\n" ));
386 //AtaReq->dma_base = NULL;
387 AtaReq->ahci.ahci_base64 = NULL;
388 return FALSE;
389 }
390 KdPrint2((PRINT_PREFIX " get Phys(data[n=%d+%x]=%x)\n", i, dma_count0, data ));
391 dma_base = AtapiVirtToPhysAddr(HwDeviceExtension, Srb, data, &dma_count, &dma_baseu);
392 if(dma_baseu && dma_count) {
393 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: block of buffer above 4Gb: %8.8x%8.8x, cnt=%x\n", dma_baseu, dma_base, dma_count));
394 if(!deviceExtension->Host64) {
395 if(use_DB_IO) {
396 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: *ERROR* special buffer above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base));
397 return FALSE;
398 }
399 count = orig_count;
400 goto retry_DB_IO;
401 }
402 } else
403 if(!dma_count || !dma_base || ((LONG)(dma_base) == -1)) {
404 //AtaReq->dma_base = NULL;
405 AtaReq->ahci.ahci_base64 = 0;
406 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: No NEXT block\n" ));
407 return FALSE;
408 }
409
410 dma_count = min(count, PAGE_SIZE);
411 data += min(count, PAGE_SIZE);
412 count -= min(count, PAGE_SIZE);
413 }
414 KdPrint2((PRINT_PREFIX " set TERM\n" ));
415/* KdPrint2((PRINT_PREFIX " segments %#x+%#x == %#x && #x+%#x <= %#x\n",
416 dma_base0, dma_count0, dma_base,
417 dma_count0, dma_count, max_frag));*/
418 if(dma_base0+dma_count0 == dma_base &&
419 dma_count0+dma_count <= max_frag) {
420 // 'i' should be always > 0 here
421 if(dma_base & seg_align) {
422 //KdPrint2((PRINT_PREFIX " merge segments\n" ));
423 //BrutePoint();
424 ASSERT(i);
425 i--;
426 dma_base = dma_base0;
427 dma_count += dma_count0;
428 }
429 }
430 if(use_AHCI) {
431 AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].base = dma_base;
432 AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].baseu = dma_baseu;
433 AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].Reserved1 = 0;
434 //AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].DBC = ((dma_count-1) & 0x3fffff);
435 //AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].Reserved2 = 0;
436 *((PULONG)&(AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].DBC_ULONG)) = ((dma_count-1) & 0x3fffff);
437 //AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].I = 1; // interrupt when ready
438 KdPrint2((PRINT_PREFIX " ph data[%d]=%x:%x (%x)\n", i, dma_baseu, dma_base, AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].DBC));
439 if(((ULONG_PTR)&(AtaReq->ahci.ahci_cmd_ptr->prd_tab) & ~PAGE_MASK) != ((ULONG_PTR)&(AtaReq->ahci.ahci_cmd_ptr->prd_tab[i]) & ~PAGE_MASK)) {
440 KdPrint2((PRINT_PREFIX "PRD table crosses page boundary! %x vs %x\n",
441 &AtaReq->ahci.ahci_cmd_ptr->prd_tab, &(AtaReq->ahci.ahci_cmd_ptr->prd_tab[i]) ));
442 //AtaReq->Flags |= REQ_FLAG_DMA_DBUF_PRD;
443 }
444 } else {
445 AtaReq->dma_tab[i].base = dma_base;
446 AtaReq->dma_tab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
447 if(((ULONG_PTR)&(AtaReq->dma_tab) & ~PAGE_MASK) != ((ULONG_PTR)&(AtaReq->dma_tab[i]) & ~PAGE_MASK)) {
448 KdPrint2((PRINT_PREFIX "DMA table crosses page boundary! %x vs %x\n",
449 &AtaReq->dma_tab, &(AtaReq->dma_tab[i]) ));
450 //AtaReq->Flags |= REQ_FLAG_DMA_DBUF_PRD;
451 }
452 }
453 AtaReq->dma_entries = i+1;
454
455 if(use_DB_IO) {
456 AtaReq->Flags |= REQ_FLAG_DMA_DBUF;
457 }
458 AtaReq->Flags |= REQ_FLAG_DMA_OPERATION;
459
460 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: OK\n" ));
461 return TRUE;
462
463} // end AtapiDmaSetup()
ATA_DMA_EOT
#define ATA_DMA_EOT
Definition: bsmaster.h:101
ATA_AHCI_DMA_ENTRIES
#define ATA_AHCI_DMA_ENTRIES
Definition: bsmaster.h:749
ATA_DMA_ENTRIES
#define ATA_DMA_ENTRIES
Definition: bsmaster.h:100
ULONG_PTR
#define ULONG_PTR
Definition: config.h:101
PAGE_SIZE
#define PAGE_SIZE
Definition: env_spec_w32.h:49
PAGE_MASK
#define PAGE_MASK
Definition: tools.h:88
BM_DMA_ENTRY::count
ULONG count
Definition: bsmaster.h:131
BM_DMA_ENTRY::base
ULONG base
Definition: bsmaster.h:130
_HW_DEVICE_EXTENSION::DmaSegmentLength
ULONG DmaSegmentLength
Definition: bsmaster.h:1319
_HW_DEVICE_EXTENSION::AlignmentMask
ULONG AlignmentMask
Definition: bsmaster.h:1318
_HW_DEVICE_EXTENSION::DmaSegmentAlignmentMask
ULONG DmaSegmentAlignmentMask
Definition: bsmaster.h:1320
ULONG_PTR
uint32_t ULONG_PTR
Definition: typedefs.h:65
_ATA_REQ::dma_entries
ULONG dma_entries
Definition: bsmaster.h:897

Referenced by AtapiSendCommand(), IdeReadWrite(), IdeSendCommand(), UniataAhciSendPIOCommand(), and UniataAhciSendPIOCommandDirect().

◆ AtapiDmaStart()

VOID NTAPI AtapiDmaStart ( IN PVOID  HwDeviceExtension,
IN ULONG  DeviceNumber,
IN ULONG  lChannel,
IN PSCSI_REQUEST_BLOCK  Srb 
)

Definition at line 588 of file id_dma.cpp.

594{
595 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
596 //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM = deviceExtension->BaseIoAddressBM[lChannel];
597 PATA_REQ AtaReq = (PATA_REQ)(Srb->SrbExtension);
598 PHW_CHANNEL chan = &deviceExtension->chan[lChannel];
599
600 ULONG VendorID = deviceExtension->DevID & 0xffff;
601 ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
602// UCHAR statusByte2;
603/*
604 GetStatus(chan, statusByte2);
605 KdPrint2((PRINT_PREFIX "AtapiDmaStart: %s on %#x:%#x\n",
606 (Srb->SrbFlags & SRB_FLAGS_DATA_IN) ? "read" : "write",
607 lChannel, DeviceNumber ));
608*/
609 if(!AtaReq->ata.dma_base) {
610 KdPrint2((PRINT_PREFIX "AtapiDmaStart: *** !AtaReq->ata.dma_base\n"));
611 return;
612 }
613 KdPrint2((PRINT_PREFIX "AtapiDmaStart: lchan=%d\n", lChannel));
614
615/*
616// GetStatus(chan, statusByte2);
617 if(AtaReq->Flags & REQ_FLAG_DMA_DBUF_PRD) {
618 KdPrint2((PRINT_PREFIX " DBUF_PRD\n"));
619 ASSERT(FALSE);
620 if(deviceExtension->HwFlags & UNIATA_AHCI) {
621 RtlCopyMemory(chan->DB_PRD, AtaReq->ahci.ahci_cmd_ptr, sizeof(AtaReq->ahci_cmd0));
622 } else {
623 RtlCopyMemory(chan->DB_PRD, &(AtaReq->dma_tab), sizeof(AtaReq->dma_tab));
624 }
625 }
626 if(!(Srb->SrbFlags & SRB_FLAGS_DATA_IN) &&
627 (AtaReq->Flags & REQ_FLAG_DMA_DBUF)) {
628 KdPrint2((PRINT_PREFIX " DBUF (Write)\n"));
629 ASSERT(FALSE);
630 RtlCopyMemory(chan->DB_IO, AtaReq->DataBuffer,
631 Srb->DataTransferLength);
632 }
633*/
634 // set flag
635 chan->ChannelCtrlFlags |= CTRFLAGS_DMA_ACTIVE;
636
637 switch(VendorID) {
638 case ATA_PROMISE_ID:
639 if(ChipType == PRNEW) {
640 ULONG Channel = deviceExtension->Channel + lChannel;
641
642 if(chan->ChannelCtrlFlags & CTRFLAGS_LBA48) {
643 AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),(Channel ? 0x24 : 0x20),
644 ((Srb->SrbFlags & SRB_FLAGS_DATA_IN) ? 0x05000000 : 0x06000000) | (Srb->DataTransferLength >> 1)
645 );
646 }
647/*
648 } else
649 if(deviceExtension->MemIo) {
650 // begin transaction
651 AtapiWritePort4(chan,
652 IDX_BM_Command,
653 (AtapiReadPort4(chan,
654 IDX_BM_Command) & ~0x000000c0) |
655 ((Srb->SrbFlags & SRB_FLAGS_DATA_IN) ? 0x00000080 : 0x000000c0) );
656 return;
657*/
658 }
659 break;
660 }
661
662 // set pointer to Pointer Table
663 AtapiWritePort4(chan, IDX_BM_PRD_Table,
664 AtaReq->ata.dma_base
665 );
666 // set transfer direction
667 AtapiWritePort1(chan, IDX_BM_Command,
668 (Srb->SrbFlags & SRB_FLAGS_DATA_IN) ? BM_COMMAND_READ : BM_COMMAND_WRITE);
669 // clear Error & Intr bits (writeing 1 clears bits)
670 // set DMA capability bit
671 AtapiWritePort1(chan, IDX_BM_Status,
672 AtapiReadPort1(chan, IDX_BM_Status) |
673 (BM_STATUS_INTR | BM_STATUS_ERR) /*|
674 (DeviceNumber ? BM_STATUS_DRIVE_1_DMA : BM_STATUS_DRIVE_0_DMA)*/);
675 // begin transaction
676 AtapiWritePort1(chan, IDX_BM_Command,
677 AtapiReadPort1(chan, IDX_BM_Command) |
678 BM_COMMAND_START_STOP);
679 return;
680
681} // end AtapiDmaStart()
BM_COMMAND_READ
#define BM_COMMAND_READ
Definition: bsmaster.h:154
IDX_BM_PRD_Table
#define IDX_BM_PRD_Table
Definition: bsmaster.h:171
BM_COMMAND_WRITE
#define BM_COMMAND_WRITE
Definition: bsmaster.h:153
CTRFLAGS_DMA_ACTIVE
#define CTRFLAGS_DMA_ACTIVE
Definition: bsmaster.h:1131

Referenced by AtapiInterrupt__(), AtapiSendCommand(), IdeReadWrite(), and IdeSendCommand().

◆ AtapiFindDev()

ULONG NTAPI AtapiFindDev ( IN PVOID  HwDeviceExtension,
IN BUS_DATA_TYPE  BusDataType,
IN ULONG  BusNumber,
IN ULONG  SlotNumber,
IN ULONG  dev_id,
IN ULONG  RevID 
)

Definition at line 871 of file id_probe.cpp.

879{
880 PCI_COMMON_CONFIG pciData;
881 ULONG funcNumber;
882 ULONG busDataRead;
883
884 ULONG VendorID;
885 ULONG DeviceID;
886 PCI_SLOT_NUMBER slotData;
887
888 slotData.u.AsULONG = SlotNumber;
889 // walk through all Function Numbers
890 for(funcNumber = 0; funcNumber < PCI_MAX_FUNCTION; funcNumber++) {
891
892 slotData.u.bits.FunctionNumber = funcNumber;
893 if(slotData.u.AsULONG == SlotNumber)
894 continue;
895
896 busDataRead = HalGetBusData(
897 //busDataRead = ScsiPortGetBusData(HwDeviceExtension,
898 PCIConfiguration,
899 BusNumber,
900 slotData.u.AsULONG,
901 &pciData,
902 PCI_COMMON_HDR_LENGTH);
903
904 if (busDataRead < (ULONG)PCI_COMMON_HDR_LENGTH) {
905 continue;
906 }
907
908 VendorID = pciData.VendorID;
909 DeviceID = pciData.DeviceID;
910
911 if(dev_id != (VendorID | (DeviceID << 16)) )
912 continue;
913 if(RevID >= pciData.RevisionID)
914 return 1;
915 }
916 return 0;
917} // end AtapiFindDev()
_PCI_SLOT_NUMBER
Definition: iotypes.h:3489
_PCI_SLOT_NUMBER::u
union _PCI_SLOT_NUMBER::@4026 u
_PCI_SLOT_NUMBER::AsULONG
ULONG AsULONG
Definition: iotypes.h:3496
_PCI_SLOT_NUMBER::bits
struct _PCI_SLOT_NUMBER::@4026::@4027 bits
SlotNumber
_In_ WDFIORESREQLIST _In_ ULONG SlotNumber
Definition: wdfresource.h:68
BusNumber
_In_opt_ PUNICODE_STRING _In_ PDRIVER_OBJECT _In_ PDEVICE_OBJECT _In_ INTERFACE_TYPE _In_ ULONG BusNumber
Definition: halfuncs.h:160
PCI_MAX_FUNCTION
#define PCI_MAX_FUNCTION
Definition: iotypes.h:3599

◆ AtapiFindListedDev()

ULONG NTAPI AtapiFindListedDev ( PBUSMASTER_CONTROLLER_INFORMATION_BASE  BusMasterAdapters,
ULONG  lim,
IN PVOID  HwDeviceExtension,
IN ULONG  BusNumber,
IN ULONG  SlotNumber,
OUT PCI_SLOT_NUMBER *  _slotData 
)

Referenced by UniataChipDetect(), and UniataChipDetectChannels().

◆ AtapiGetIoRange()

ULONGIO_PTR NTAPI AtapiGetIoRange ( IN PVOID  HwDeviceExtension,
IN PPORT_CONFIGURATION_INFORMATION  ConfigInfo,
IN PPCI_COMMON_CONFIG  pciData,
IN ULONG  SystemIoBusNumber,
IN ULONG  rid,
IN ULONG  offset,
IN ULONG  length 
)

Definition at line 153 of file id_probe.cpp.

162{
163 ULONGIO_PTR io_start = 0;
164 KdPrint2((PRINT_PREFIX " AtapiGetIoRange:\n"));
165
166 if(ConfigInfo->NumberOfAccessRanges <= rid)
167 return 0;
168
169 KdPrint2((PRINT_PREFIX " AtapiGetIoRange: rid %#x, start %#x, offs %#x, len %#x, mem %#x\n",
170 rid,
171 ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[rid].RangeStart),
172 offset,
173 length,
174 (*ConfigInfo->AccessRanges)[rid].RangeInMemory
175 ));
176
177 if(!(*ConfigInfo->AccessRanges)[rid].RangeInMemory) {
178 io_start = (pciData->u.type0.BaseAddresses[rid] & ~0x07/*PCI_ADDRESS_IOMASK*/) + offset;
179 // if(pciData->u.type0.BaseAddresses[rid] != 0) ;)
180 if(io_start > offset) {
181 if(/*(WinVer_Id() <= WinVer_NT) &&*/ offset && rid == 4) {
182 // MS atapi.sys does so for BusMaster controllers
183 (*ConfigInfo->AccessRanges)[rid+1].RangeStart =
184 ScsiPortConvertUlongToPhysicalAddress(io_start);
185 (*ConfigInfo->AccessRanges)[rid+1].RangeLength = length;
186 } else {
187 (*ConfigInfo->AccessRanges)[rid].RangeStart =
188 ScsiPortConvertUlongToPhysicalAddress(io_start);
189 (*ConfigInfo->AccessRanges)[rid].RangeLength = length;
190 }
191 if((pciData->u.type0.BaseAddresses[rid] & PCI_ADDRESS_IO_SPACE)) {
192 (*ConfigInfo->AccessRanges)[rid].RangeInMemory = FALSE;
193 } else {
194 KdPrint2((PRINT_PREFIX " AtapiGetIoRange: adjust mem 0 -> 1\n"));
195 (*ConfigInfo->AccessRanges)[rid].RangeInMemory = TRUE;
196 }
197 } else {
198 io_start = 0;
199 }
200 }
201
202 if((*ConfigInfo->AccessRanges)[rid].RangeInMemory) {
203 if(offset) {
204 KdPrint2((PRINT_PREFIX " AtapiGetIoRange: can't map memory range with offset\n"));
205 return 0;
206 }
207 io_start =
208 // Get the system physical address for this IO range.
209 ((ULONG_PTR)ScsiPortGetDeviceBase(HwDeviceExtension,
210 PCIBus /*ConfigInfo->AdapterInterfaceType*/,
211 SystemIoBusNumber /*ConfigInfo->SystemIoBusNumber*/,
212 ScsiPortConvertUlongToPhysicalAddress(
213 (ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[rid].RangeStart) &
214 ~0x07/*PCI_ADDRESS_IOMASK*/) + offset
215 ),
216 length,
217 (BOOLEAN)!(*ConfigInfo->AccessRanges)[rid].RangeInMemory)
218 );
219
220 KdPrint2((PRINT_PREFIX " AtapiGetIoRange: %#x\n", io_start));
221 // if(io_start > offset) {
222 return io_start;
223 // }
224 }
225
226 KdPrint2((PRINT_PREFIX " AtapiGetIoRange: (2) %#x\n", io_start));
227 return io_start;
228
229} // end AtapiGetIoRange()
ScsiPortGetDeviceBase
PVOID NTAPI ScsiPortGetDeviceBase(IN PVOID HwDeviceExtension, IN INTERFACE_TYPE BusType, IN ULONG SystemIoBusNumber, IN SCSI_PHYSICAL_ADDRESS IoAddress, IN ULONG NumberOfBytes, IN BOOLEAN InIoSpace)
Definition: scsiport.c:571
ScsiPortConvertPhysicalAddressToUlong
#define ScsiPortConvertPhysicalAddressToUlong(Address)
Definition: srb.h:957
length
GLuint GLsizei GLsizei * length
Definition: glext.h:6040
BOOLEAN
#define BOOLEAN
Definition: pedump.c:73
PCI_ADDRESS_IO_SPACE
#define PCI_ADDRESS_IO_SPACE
Definition: iotypes.h:4230

Referenced by UniataAhciDetect(), UniataChipDetect(), and UniataFindBusMasterController().

◆ AtapiInterrupt2()

BOOLEAN NTAPI AtapiInterrupt2 ( IN PKINTERRUPT  Interrupt,
IN PVOID  HwDeviceExtension 
)

Definition at line 4192 of file id_ata.cpp.

4196{
4197 // This ISR is intended to catch interrupts when we are already in other ISR instance
4198 // for the same device. This may happen when we have multiple channels,
4199 // especially on SMP machines
4200
4201 PISR2_DEVICE_EXTENSION Isr2DeviceExtension = (PISR2_DEVICE_EXTENSION)Isr2HwDeviceExtension;
4202 PHW_DEVICE_EXTENSION deviceExtension = Isr2DeviceExtension->HwDeviceExtension;
4203 ULONG c;
4204 BOOLEAN status = FALSE;
4205 ULONG c_count = 0;
4206 ULONG i_res;
4207 ULONG hIS;
4208 ULONG checked;
4209
4210 // we should never get here for ISA/MCA
4211 if(!BMList[deviceExtension->DevIndex].Isr2Enable) {
4212 KdPrint2((PRINT_PREFIX "AtapiInterrupt2: NOT ACTIVE cntrlr %#x chan %#x\n",deviceExtension->DevIndex, deviceExtension->Channel));
4213 return FALSE;
4214 }
4215
4216 if(deviceExtension->HwFlags & UNIATA_AHCI) {
4217 // AHCI may generate state change notification, never skip this check
4218 hIS = UniataAhciReadHostPort4(deviceExtension, IDX_AHCI_IS);
4219 KdPrint2((PRINT_PREFIX "AtapiInterrupt2: AHCI: hIS=%x cntrlr %#x chan %#x\n",hIS, deviceExtension->DevIndex, deviceExtension->Channel));
4220 if(!hIS) {
4221 return FALSE;
4222 }
4223 // assume all non-interrupted ports to be already checked
4224 checked = ~hIS;
4225 // assume all not implemented ports to be already checked
4226 checked |= ~deviceExtension->AHCI_PI;
4227
4228 } else {
4229 checked = 0; // assume all ports are not checked
4230 }
4231 if(!deviceExtension->ExpectingInterrupt) {
4232 KdPrint2((PRINT_PREFIX "AtapiInterrupt2: !deviceExtension->ExpectingInterrupt\n"));
4233 deviceExtension->ExpectingInterrupt++;
4234 return FALSE;
4235 }
4236 //deviceExtension->ExpectingInterrupt = 0;
4237
4238 for(c=0; c<deviceExtension->NumberChannels; c++) {
4239 KdPrint2((PRINT_PREFIX "AtapiInterrupt2: cntrlr %#x chan %#x\n",deviceExtension->DevIndex, c));
4240
4241 if((checked>>c) & 0x01)
4242 continue;
4243
4244 checked |= (ULONG)1 << c;
4245
4246 if(CrNtInterlockedExchangeAdd(&(deviceExtension->chan[c].DisableIntr), 0)) {
4247 KdPrint2((PRINT_PREFIX "AtapiInterrupt2: disabled INTR\n"));
4248 continue;
4249 }
4250
4251 if((ULONG)CrNtInterlockedCompareExchange(CRNT_ILK_PTYPE &(deviceExtension->chan[c].CheckIntr),
4252 CRNT_ILK_TYPE CHECK_INTR_CHECK,
4253 CRNT_ILK_TYPE CHECK_INTR_IDLE) != CHECK_INTR_IDLE)
4254 {
4255 KdPrint2((PRINT_PREFIX "AtapiInterrupt2: !CHECK_INTR_IDLE\n"));
4256 // hunt on unexpected intr (Some devices generate double interrupts,
4257 // some controllers (at least CMD649) interrupt twice with small delay.
4258 // If interrupts are disabled, they queue interrupt and re-issue it later,
4259 // when we do not expect it.
4260 continue;
4261 }
4262
4263 c_count++;
4264 if((i_res = AtapiCheckInterrupt__(deviceExtension, (UCHAR)c))) {
4265
4266 KdPrint2((PRINT_PREFIX "AtapiInterrupt2: intr\n"));
4267 if(i_res == INTERRUPT_REASON_UNEXPECTED) {
4268 KdPrint2((PRINT_PREFIX "AtapiInterrupt2: Catch unexpected\n"));
4269 InterlockedExchange(&(deviceExtension->chan[c].CheckIntr), CHECK_INTR_IDLE);
4270 return TRUE;
4271 }
4272
4273 status = TRUE;
4274 InterlockedExchange(&(deviceExtension->chan[c].CheckIntr), CHECK_INTR_DETECTED);
4275 } else {
4276 InterlockedExchange(&(deviceExtension->chan[c].CheckIntr), CHECK_INTR_IDLE);
4277 }
4278 }
4279 KdPrint2((PRINT_PREFIX "AtapiInterrupt2: status %d, c_count %d\n", status, c_count));
4280 if(status && (c_count != deviceExtension->NumberChannels)) {
4281 // there is an active ISR/DPC for one channel, but
4282 // we have an interrupt from another one
4283 // Lets inform current ISR/DPC about new interrupt
4284 InterlockedExchange(&(deviceExtension->ReCheckIntr), CHECK_INTR_DETECTED);
4285 } else {
4286 status = FALSE;
4287 }
4288 KdPrint2((PRINT_PREFIX "AtapiInterrupt2: return %d\n", status));
4289 return status;
4290
4291} // end AtapiInterrupt2()
InterlockedExchange
#define InterlockedExchange
Definition: armddk.h:54
CHECK_INTR_CHECK
#define CHECK_INTR_CHECK
Definition: bsmaster.h:1068
IDX_AHCI_IS
#define IDX_AHCI_IS
Definition: bsmaster.h:272
PISR2_DEVICE_EXTENSION
struct _ISR2_DEVICE_EXTENSION * PISR2_DEVICE_EXTENSION
CHECK_INTR_IDLE
#define CHECK_INTR_IDLE
Definition: bsmaster.h:1069
CHECK_INTR_DETECTED
#define CHECK_INTR_DETECTED
Definition: bsmaster.h:1067
BMList
PBUSMASTER_CONTROLLER_INFORMATION BMList
Definition: id_probe.cpp:53
CRNT_ILK_PTYPE
#define CRNT_ILK_PTYPE
Definition: config.h:104
CRNT_ILK_TYPE
#define CRNT_ILK_TYPE
Definition: config.h:103
AtapiCheckInterrupt__
BOOLEAN NTAPI AtapiCheckInterrupt__(IN PVOID HwDeviceExtension, IN UCHAR c)
Definition: id_ata.cpp:4512
UniataAhciReadHostPort4
#define UniataAhciReadHostPort4(deviceExtension, io_port_ndx)
Definition: id_sata.h:313
_BUSMASTER_CONTROLLER_INFORMATION::Isr2Enable
BOOLEAN Isr2Enable
Definition: bm_devs_decl.h:95
_HW_CHANNEL::CheckIntr
LONG CheckIntr
Definition: bsmaster.h:1062
_HW_CHANNEL::DisableIntr
LONG DisableIntr
Definition: bsmaster.h:1061
_HW_DEVICE_EXTENSION::ExpectingInterrupt
BOOLEAN ExpectingInterrupt
Definition: atapi.c:99
_HW_DEVICE_EXTENSION::ReCheckIntr
LONG ReCheckIntr
Definition: bsmaster.h:1311
_HW_DEVICE_EXTENSION::DevIndex
ULONG DevIndex
Definition: bsmaster.h:1292
_ISR2_DEVICE_EXTENSION
Definition: bsmaster.h:1350
_ISR2_DEVICE_EXTENSION::HwDeviceExtension
PHW_DEVICE_EXTENSION HwDeviceExtension
Definition: bsmaster.h:1351
status
Definition: ps.c:97
INTERRUPT_REASON_UNEXPECTED
#define INTERRUPT_REASON_UNEXPECTED
Definition: atapi.h:1280

Referenced by UniataConnectIntr2().

◆ AtapiReadBuffer2()

VOID DDKFASTAPI AtapiReadBuffer2 ( IN PHW_CHANNEL  chan,
IN ULONGIO_PTR  _port,
IN PVOID  Buffer,
IN ULONG  Count,
IN ULONG  Timing 
)

◆ AtapiReadBuffer4()

VOID DDKFASTAPI AtapiReadBuffer4 ( IN PHW_CHANNEL  chan,
IN ULONGIO_PTR  _port,
IN PVOID  Buffer,
IN ULONG  Count,
IN ULONG  Timing 
)

◆ AtapiReadChipConfig()

BOOLEAN NTAPI AtapiReadChipConfig ( IN PVOID  HwDeviceExtension,
IN ULONG  DeviceNumber,
IN ULONG  channel 
)

Definition at line 1782 of file id_init.cpp.

1787{
1788 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
1789 PHW_CHANNEL chan;
1790 ULONG tmp32;
1791 ULONG c; // logical channel (for Compatible Mode controllers)
1792 ULONG i;
1793
1794 KdPrint2((PRINT_PREFIX "AtapiReadChipConfig: devExt %#x\n", deviceExtension ));
1795 ASSERT(deviceExtension);
1796
1797 if(channel != CHAN_NOT_SPECIFIED) {
1798 c = channel - deviceExtension->Channel; // logical channel (for Compatible Mode controllers)
1799 } else {
1800 c = CHAN_NOT_SPECIFIED;
1801 }
1802
1803 KdPrint2((PRINT_PREFIX "AtapiReadChipConfig: dev %#x, ph chan %d\n", DeviceNumber, channel ));
1804
1805 if(channel == CHAN_NOT_SPECIFIED) {
1806 if(AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"ForceSimplex", FALSE)) {
1807 deviceExtension->simplexOnly = TRUE;
1808 }
1809 deviceExtension->opt_AtapiDmaZeroTransfer = FALSE;
1810 deviceExtension->opt_AtapiDmaControlCmd = FALSE;
1811 deviceExtension->opt_AtapiDmaRawRead = g_opt_AtapiDmaRawRead;
1812 deviceExtension->opt_AtapiDmaReadWrite = TRUE;
1813 }
1814
1815 if(c == CHAN_NOT_SPECIFIED) {
1816 KdPrint2((PRINT_PREFIX "MaxTransferMode (base): %#x\n", deviceExtension->MaxTransferMode));
1817 for(c=0; c<deviceExtension->NumberChannels; c++) {
1818 chan = &deviceExtension->chan[c];
1819 chan->MaxTransferMode = deviceExtension->MaxTransferMode;
1820 tmp32 = AtapiRegCheckDevValue(deviceExtension, channel, DEVNUM_NOT_SPECIFIED, L"MaxTransferMode", chan->MaxTransferMode);
1821 if(tmp32 != 0xffffffff) {
1822 KdPrint2((PRINT_PREFIX "MaxTransferMode (overriden): %#x\n", chan->MaxTransferMode));
1823 chan->MaxTransferMode = tmp32;
1824 }
1825 tmp32 = AtapiRegCheckDevValue(deviceExtension, c, DEVNUM_NOT_SPECIFIED, L"Force80pin", FALSE);
1826 chan->Force80pin = tmp32 ? TRUE : FALSE;
1827 if(chan->Force80pin) {
1828 KdPrint2((PRINT_PREFIX "Force80pin on chip\n"));
1829 deviceExtension->HwFlags |= UNIATA_NO80CHK;
1830 }
1831
1832 //UniAtaReadLunConfig(deviceExtension, c, 0);
1833 //UniAtaReadLunConfig(deviceExtension, c, 1);
1834 }
1835
1836 deviceExtension->opt_AtapiDmaZeroTransfer =
1837 AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"AtapiDmaZeroTransfer", deviceExtension->opt_AtapiDmaZeroTransfer) ?
1838 TRUE : FALSE;
1839
1840 deviceExtension->opt_AtapiDmaControlCmd =
1841 AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"AtapiDmaControlCmd", deviceExtension->opt_AtapiDmaControlCmd) ?
1842 TRUE : FALSE;
1843
1844 deviceExtension->opt_AtapiDmaRawRead =
1845 AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"AtapiDmaRawRead", deviceExtension->opt_AtapiDmaRawRead) ?
1846 TRUE : FALSE;
1847
1848 deviceExtension->opt_AtapiDmaReadWrite =
1849 AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"AtapiDmaReadWrite", deviceExtension->opt_AtapiDmaReadWrite) ?
1850 TRUE : FALSE;
1851
1852 } else {
1853 chan = &deviceExtension->chan[c];
1854 chan->MaxTransferMode = deviceExtension->MaxTransferMode;
1855 tmp32 = AtapiRegCheckDevValue(deviceExtension, c, DEVNUM_NOT_SPECIFIED, L"MaxTransferMode", chan->MaxTransferMode);
1856 if(tmp32 != 0xffffffff) {
1857 KdPrint2((PRINT_PREFIX "MaxTransferMode (overriden): %#x\n", chan->MaxTransferMode));
1858 chan->MaxTransferMode = tmp32;
1859 }
1860 tmp32 = AtapiRegCheckDevValue(deviceExtension, c, DEVNUM_NOT_SPECIFIED, L"ReorderEnable", TRUE);
1861 chan->UseReorder = tmp32 ? TRUE : FALSE;
1862
1863 tmp32 = AtapiRegCheckDevValue(deviceExtension, c, DEVNUM_NOT_SPECIFIED, L"Force80pin", FALSE);
1864 chan->Force80pin = tmp32 ? TRUE : FALSE;
1865 if(chan->Force80pin) {
1866 KdPrint2((PRINT_PREFIX "Force80pin on channel\n"));
1867 }
1868
1869 for(i=0; i<deviceExtension->NumberLuns; i++) {
1870 UniAtaReadLunConfig(deviceExtension, channel, i);
1871 }
1872 }
1873
1874 return TRUE;
1875} // end AtapiReadChipConfig()
g_opt_AtapiDmaRawRead
BOOLEAN g_opt_AtapiDmaRawRead
Definition: id_ata.cpp:100
UniAtaReadLunConfig
VOID NTAPI UniAtaReadLunConfig(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG channel, IN ULONG DeviceNumber)
Definition: id_init.cpp:1680
L
#define L(x)
Definition: ntvdm.h:50
_HW_CHANNEL::UseReorder
BOOLEAN UseReorder
Definition: bsmaster.h:1041
_HW_DEVICE_EXTENSION::opt_AtapiDmaReadWrite
BOOLEAN opt_AtapiDmaReadWrite
Definition: bsmaster.h:1339
_HW_DEVICE_EXTENSION::opt_AtapiDmaRawRead
BOOLEAN opt_AtapiDmaRawRead
Definition: bsmaster.h:1338
_HW_DEVICE_EXTENSION::simplexOnly
BOOLEAN simplexOnly
Definition: bsmaster.h:1299
_HW_DEVICE_EXTENSION::opt_AtapiDmaControlCmd
BOOLEAN opt_AtapiDmaControlCmd
Definition: bsmaster.h:1337
_HW_DEVICE_EXTENSION::NumberLuns
ULONG NumberLuns
Definition: bsmaster.h:1250
_HW_DEVICE_EXTENSION::opt_AtapiDmaZeroTransfer
BOOLEAN opt_AtapiDmaZeroTransfer
Definition: bsmaster.h:1336
AtapiRegCheckDevValue
ULONG NTAPI AtapiRegCheckDevValue(IN PVOID HwDeviceExtension, IN ULONG chan, IN ULONG dev, IN PCWSTR Name, IN ULONG Default)
Definition: id_ata.cpp:11365
DEVNUM_NOT_SPECIFIED
#define DEVNUM_NOT_SPECIFIED
Definition: atapi.h:1483

Referenced by AtapiFindIsaController(), and UniataFindBusMasterController().

◆ AtapiReadPort1()

UCHAR DDKFASTAPI AtapiReadPort1 ( IN PHW_CHANNEL  chan,
IN ULONGIO_PTR  port 
)

Referenced by AtapiCheckInterrupt__(), AtapiChipInit(), AtapiDmaDone(), AtapiDmaInit(), AtapiDmaStart(), AtapiFindIsaController(), AtapiHwInitialize__(), AtapiInterrupt__(), AtapiResetController__(), AtapiSendCommand(), AtapiSoftReset(), CheckDevice(), FindDevices(), IdeMediaStatus(), IdeReadWrite(), IdeSendCommand(), IssueIdentify(), MapError(), SetDriveParameters(), UniataAnybodyHome(), UniataFindBusMasterController(), and UniataSnapAtaRegs().

◆ AtapiReadPort2()

USHORT DDKFASTAPI AtapiReadPort2 ( IN PHW_CHANNEL  chan,
IN ULONGIO_PTR  port 
)

Referenced by AtapiSuckPort2(), and AtapiSuckPortBuffer2().

◆ AtapiReadPort4()

ULONG DDKFASTAPI AtapiReadPort4 ( IN PHW_CHANNEL  chan,
IN ULONGIO_PTR  port 
)

Referenced by AtapiCheckInterrupt__(), AtapiChipInit(), UniataAhciStart(), UniataAhciStatus(), UniataAhciStop(), UniataAhciStopFR(), UniataAhciWaitCommandReady(), and UniataSataReadPort4().

◆ AtapiReadPortEx1()

UCHAR DDKFASTAPI AtapiReadPortEx1 ( IN PHW_CHANNEL  chan,
IN ULONGIO_PTR  port,
IN ULONG  offs 
)

Referenced by AtapiCheckInterrupt__(), AtapiChipInit(), AtapiDmaInit(), AtapiResetController__(), and UniataChipDetect().

◆ AtapiReadPortEx4()

ULONG DDKFASTAPI AtapiReadPortEx4 ( IN PHW_CHANNEL  chan,
IN ULONGIO_PTR  port,
IN ULONG  offs 
)

Referenced by AtapiCheckInterrupt__(), AtapiChipInit(), AtapiResetController__(), UniataAhciReadChannelPort4(), and UniataSataReadPort4().

◆ AtapiSetupLunPtrs()

VOID NTAPI AtapiSetupLunPtrs ( IN PHW_CHANNEL  chan,
IN PHW_DEVICE_EXTENSION  deviceExtension,
IN ULONG  c 
)

Definition at line 2846 of file id_init.cpp.

2851{
2852 ULONG i;
2853
2854 KdPrint2((PRINT_PREFIX "AtapiSetupLunPtrs for channel %d of %d, %d luns \n", c, deviceExtension->NumberChannels, deviceExtension->NumberLuns));
2855
2856 if(!deviceExtension->NumberLuns) {
2857 KdPrint2((PRINT_PREFIX "Achtung !deviceExtension->NumberLuns \n"));
2858 deviceExtension->NumberLuns = IDE_MAX_LUN_PER_CHAN;
2859 }
2860 KdPrint2((PRINT_PREFIX " Chan %#x\n", chan));
2861 chan->DeviceExtension = deviceExtension;
2862 chan->lChannel = c;
2863 chan->NumberLuns = deviceExtension->NumberLuns;
2864 for(i=0; i<deviceExtension->NumberLuns; i++) {
2865 chan->lun[i] = &(deviceExtension->lun[c*deviceExtension->NumberLuns+i]);
2866 KdPrint2((PRINT_PREFIX " Lun %#x\n", i));
2867 KdPrint2((PRINT_PREFIX " Lun ptr %#x\n", chan->lun[i]));
2868 }
2869 chan->AltRegMap = deviceExtension->AltRegMap;
2870 chan->NextDpcChan = -1;
2871 chan->last_devsel = -1;
2872 for(i=0; i<deviceExtension->NumberLuns; i++) {
2873 chan->lun[i]->DeviceExtension = deviceExtension;
2874 chan->lun[i]->chan = chan;
2875 chan->lun[i]->Lun = i;
2876 }
2877 if((deviceExtension->HwFlags & UNIATA_AHCI) &&
2878 deviceExtension->AhciInternalAtaReq0 &&
2879 deviceExtension->AhciInternalSrb0) {
2880 chan->AhciInternalAtaReq = &(deviceExtension->AhciInternalAtaReq0[c]);
2881 chan->AhciInternalSrb = &(deviceExtension->AhciInternalSrb0[c]);
2882 UniataAhciSetupCmdPtr(chan->AhciInternalAtaReq);
2883 chan->AhciInternalSrb->SrbExtension = chan->AhciInternalAtaReq;
2884 chan->AhciInternalAtaReq->Srb = chan->AhciInternalSrb;
2885 }
2886 return;
2887} // end AtapiSetupLunPtrs()
IDE_MAX_LUN_PER_CHAN
#define IDE_MAX_LUN_PER_CHAN
Definition: bm_devs_decl.h:46
UniataAhciSetupCmdPtr
VOID UniataAhciSetupCmdPtr(IN OUT PATA_REQ AtaReq)
Definition: id_sata.cpp:2611

Referenced by AtapiFindIsaController(), UniataAhciInit(), UniataChipDetect(), and UniataFindBusMasterController().

◆ AtapiWriteBuffer2()

VOID DDKFASTAPI AtapiWriteBuffer2 ( IN PHW_CHANNEL  chan,
IN ULONGIO_PTR  _port,
IN PVOID  Buffer,
IN ULONG  Count,
IN ULONG  Timing 
)

◆ AtapiWriteBuffer4()

VOID DDKFASTAPI AtapiWriteBuffer4 ( IN PHW_CHANNEL  chan,
IN ULONGIO_PTR  _port,
IN PVOID  Buffer,
IN ULONG  Count,
IN ULONG  Timing 
)

◆ AtapiWritePort1()

VOID DDKFASTAPI AtapiWritePort1 ( IN PHW_CHANNEL  chan,
IN ULONGIO_PTR  port,
IN UCHAR  data 
)

Referenced by AtaCommand48(), AtapiCheckInterrupt__(), AtapiChipInit(), AtapiDisableInterrupts(), AtapiDmaDone(), AtapiDmaStart(), AtapiEnableInterrupts(), AtapiFindIsaController(), AtapiHardReset(), AtapiSendCommand(), AtapiSoftReset(), IdeSendCommand(), IssueIdentify(), SelectDrive(), and UniataAnybodyHome().

◆ AtapiWritePort2()

VOID DDKFASTAPI AtapiWritePort2 ( IN PHW_CHANNEL  chan,
IN ULONGIO_PTR  port,
IN USHORT  data 
)

Referenced by AtapiChipInit().

◆ AtapiWritePort4()

VOID DDKFASTAPI AtapiWritePort4 ( IN PHW_CHANNEL  chan,
IN ULONGIO_PTR  port,
IN ULONG  data 
)

Referenced by AtapiCheckInterrupt__(), AtapiChipInit(), AtapiDmaStart(), UniataAhciStatus(), UniataSataReadPort4(), and UniataSataWritePort4().

◆ AtapiWritePortEx1()

VOID DDKFASTAPI AtapiWritePortEx1 ( IN PHW_CHANNEL  chan,
IN ULONGIO_PTR  port,
IN ULONG  offs,
IN UCHAR  data 
)

Referenced by AtapiCheckInterrupt__(), AtapiChipInit(), AtapiDmaInit(), and AtapiResetController__().

◆ AtapiWritePortEx4()

VOID DDKFASTAPI AtapiWritePortEx4 ( IN PHW_CHANNEL  chan,
IN ULONGIO_PTR  port,
IN ULONG  offs,
IN ULONG  data 
)

Referenced by AtapiCheckInterrupt__(), AtapiChipInit(), AtapiDmaDone(), AtapiDmaInit(), AtapiDmaStart(), AtapiResetController__(), cyrix_timing(), UniataAhciWriteChannelPort4(), and UniataSataWritePort4().

◆ ScsiPortGetBusDataByOffset()

ULONG NTAPI ScsiPortGetBusDataByOffset ( IN PVOID  HwDeviceExtension,
IN BUS_DATA_TYPE  BusDataType,
IN ULONG  BusNumber,
IN ULONG  SlotNumber,
IN PVOID  Buffer,
IN ULONG  Offset,
IN ULONG  Length 
)

Definition at line 741 of file id_probe.cpp.

750{
751 UCHAR tmp[256];
752 ULONG busDataRead;
753
754 if(Offset+Length > 256)
755 return 0;
756
757 busDataRead = HalGetBusData(
758 //ScsiPortGetBusData(HwDeviceExtension,
759 BusDataType,
760 BusNumber,
761 SlotNumber,
762 &tmp,
763 Offset+Length);
764 if(busDataRead < Offset+Length) {
765 if(busDataRead < Offset)
766 return 0;
767 return (Offset+Length-busDataRead);
768 }
769 RtlCopyMemory(Buffer, tmp+Offset, Length);
770 return Length;
771} // end ScsiPortGetBusDataByOffset()
Buffer
Definition: bufpool.h:45
Offset
_In_ ULONG _In_ ULONG Offset
Definition: ntddpcm.h:101
Length
_In_ ULONG _In_ ULONG _In_ ULONG Length
Definition: ntddpcm.h:102

◆ UniataAllocateLunExt()

BOOLEAN NTAPI UniataAllocateLunExt ( PHW_DEVICE_EXTENSION  deviceExtension,
ULONG  NewNumberChannels 
)

Definition at line 2891 of file id_init.cpp.

2895{
2896 PHW_LU_EXTENSION old_luns = NULL;
2897 PHW_CHANNEL old_chans = NULL;
2898
2899 KdPrint2((PRINT_PREFIX "allocate %d Luns for %d channels\n", deviceExtension->NumberLuns, deviceExtension->NumberChannels));
2900
2901 old_luns = deviceExtension->lun;
2902 old_chans = deviceExtension->chan;
2903
2904 if(old_luns || old_chans) {
2905 if(NewNumberChannels == UNIATA_ALLOCATE_NEW_LUNS) {
2906 KdPrint2((PRINT_PREFIX "already allocated!\n"));
2907 return FALSE;
2908 }
2909 }
2910
2911 if(!deviceExtension->NumberLuns) {
2912 KdPrint2((PRINT_PREFIX "default NumberLuns=2\n"));
2913 deviceExtension->NumberLuns = 2;
2914 }
2915
2916 if(deviceExtension->HwFlags & UNIATA_AHCI) {
2917 if(!deviceExtension->AhciInternalAtaReq0) {
2918 deviceExtension->AhciInternalAtaReq0 = (PATA_REQ)ExAllocatePool(NonPagedPool, sizeof(ATA_REQ)*deviceExtension->NumberChannels);
2919 if (!deviceExtension->AhciInternalAtaReq0) {
2920 KdPrint2((PRINT_PREFIX "!deviceExtension->AhciInternalAtaReq0 => SP_RETURN_ERROR\n"));
2921 return FALSE;
2922 }
2923 RtlZeroMemory(deviceExtension->AhciInternalAtaReq0, sizeof(ATA_REQ)*deviceExtension->NumberChannels);
2924 }
2925 if(!deviceExtension->AhciInternalSrb0) {
2926 deviceExtension->AhciInternalSrb0 = (PSCSI_REQUEST_BLOCK)ExAllocatePool(NonPagedPool, sizeof(SCSI_REQUEST_BLOCK)*deviceExtension->NumberChannels);
2927 if (!deviceExtension->AhciInternalSrb0) {
2928 KdPrint2((PRINT_PREFIX "!deviceExtension->AhciInternalSrb0 => SP_RETURN_ERROR\n"));
2929 UniataFreeLunExt(deviceExtension);
2930 return FALSE;
2931 }
2932 RtlZeroMemory(deviceExtension->AhciInternalSrb0, sizeof(SCSI_REQUEST_BLOCK)*deviceExtension->NumberChannels);
2933 }
2934 }
2935
2936 deviceExtension->lun = (PHW_LU_EXTENSION)ExAllocatePool(NonPagedPool, sizeof(HW_LU_EXTENSION) * (deviceExtension->NumberChannels+1) * deviceExtension->NumberLuns);
2937 if (!deviceExtension->lun) {
2938 KdPrint2((PRINT_PREFIX "!deviceExtension->lun => SP_RETURN_ERROR\n"));
2939 UniataFreeLunExt(deviceExtension);
2940 return FALSE;
2941 }
2942 RtlZeroMemory(deviceExtension->lun, sizeof(HW_LU_EXTENSION) * (deviceExtension->NumberChannels+1) * deviceExtension->NumberLuns);
2943
2944 deviceExtension->chan = (PHW_CHANNEL)ExAllocatePool(NonPagedPool, sizeof(HW_CHANNEL) * (deviceExtension->NumberChannels+1));
2945 if (!deviceExtension->chan) {
2946 UniataFreeLunExt(deviceExtension);
2947 KdPrint2((PRINT_PREFIX "!deviceExtension->chan => SP_RETURN_ERROR\n"));
2948 return FALSE;
2949 }
2950 RtlZeroMemory(deviceExtension->chan, sizeof(HW_CHANNEL) * (deviceExtension->NumberChannels+1));
2951 return TRUE;
2952} // end UniataAllocateLunExt()
PHW_LU_EXTENSION
struct _HW_LU_EXTENSION * PHW_LU_EXTENSION
PHW_CHANNEL
struct _HW_CHANNEL * PHW_CHANNEL
UNIATA_ALLOCATE_NEW_LUNS
#define UNIATA_ALLOCATE_NEW_LUNS
Definition: bsmaster.h:1398
PSCSI_REQUEST_BLOCK
struct _SCSI_REQUEST_BLOCK * PSCSI_REQUEST_BLOCK
NonPagedPool
#define NonPagedPool
Definition: env_spec_w32.h:307
ExAllocatePool
#define ExAllocatePool(type, size)
Definition: fbtusb.h:44
UniataFreeLunExt
VOID NTAPI UniataFreeLunExt(PHW_DEVICE_EXTENSION deviceExtension)
Definition: id_init.cpp:2956
_HW_DEVICE_EXTENSION::AhciInternalSrb0
PSCSI_REQUEST_BLOCK AhciInternalSrb0
Definition: bsmaster.h:1334
_HW_DEVICE_EXTENSION::lun
PHW_LU_EXTENSION lun
Definition: bsmaster.h:1256
_HW_DEVICE_EXTENSION::AhciInternalAtaReq0
PATA_REQ AhciInternalAtaReq0
Definition: bsmaster.h:1333
_SCSI_REQUEST_BLOCK
Definition: srb.h:248
RtlZeroMemory
#define RtlZeroMemory(Destination, Length)
Definition: typedefs.h:262

Referenced by AtapiFindIsaController(), and UniataChipDetect().

◆ UniataChipDetect()

NTSTATUS NTAPI UniataChipDetect ( IN PVOID  HwDeviceExtension,
IN PPCI_COMMON_CONFIG  pciData,
IN ULONG  DeviceNumber,
IN OUT PPORT_CONFIGURATION_INFORMATION  ConfigInfo,
IN BOOLEAN *  simplexOnly 
)

Definition at line 339 of file id_init.cpp.

346{
347 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
348 ULONG slotNumber = deviceExtension->slotNumber;
349 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
350 ULONG VendorID = deviceExtension->DevID & 0xffff;
351 ULONG DeviceID = (deviceExtension->DevID >> 16) & 0xffff;
352 ULONG RevID = deviceExtension->RevID;
353 ULONG i, c;
354 BUSMASTER_CONTROLLER_INFORMATION_BASE* DevTypeInfo;
355 PHW_CHANNEL chan;
356 ULONG ChipType;
357 ULONG ChipFlags;
358 ULONG tmp32;
359 UCHAR tmp8;
360 ULONG_PTR BaseMemAddress;
361 ULONG_PTR BaseIoAddress1;
362 ULONG_PTR BaseIoAddress2;
363 ULONG_PTR BaseIoAddressBM;
364 BOOLEAN MemIo = FALSE;
365 BOOLEAN IsPata = FALSE;
366
367 KdPrint2((PRINT_PREFIX "UniataChipDetect:\n" ));
368 KdPrint2((PRINT_PREFIX "HwFlags: %#x\n", deviceExtension->HwFlags));
369
370 i = Ata_is_dev_listed((PBUSMASTER_CONTROLLER_INFORMATION_BASE)&BusMasterAdapters[0], VendorID, 0xffff, 0, NUM_BUSMASTER_ADAPTERS);
371
372 c = AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"ForceSimplex", 0);
373 if(c) {
374 *simplexOnly = TRUE;
375 }
376
377 // defaults
378 BaseIoAddressBM = pciData->u.type0.BaseAddresses[4] & ~0x07;
379 deviceExtension->MaxTransferMode = BaseIoAddressBM ? ATA_DMA : ATA_PIO4;
380 ConfigInfo->MaximumTransferLength = DEV_BSIZE*256;
381 deviceExtension->MaximumDmaTransferLength = ConfigInfo->MaximumTransferLength;
382 //deviceExtension->NumberOfPhysicalBreaks = min(deviceExtension->MaximumDmaTransferLength/PAGE_SIZE+1, ATA_DMA_ENTRIES);
383 deviceExtension->DmaSegmentLength = 0x10000;
384 deviceExtension->DmaSegmentAlignmentMask = 0xffff;
385
386 KdPrint2((PRINT_PREFIX "i: %#x\n", i));
387 if(i != BMLIST_TERMINATOR) {
388 DevTypeInfo = (PBUSMASTER_CONTROLLER_INFORMATION_BASE)&BusMasterAdapters[i];
389 } else {
390unknown_dev:
391 if(Ata_is_ahci_dev(pciData)) {
392 KdPrint2((PRINT_PREFIX " AHCI candidate"));
393
394 deviceExtension->NumberChannels = 0;
395 if(!UniataAhciDetect(HwDeviceExtension, pciData, ConfigInfo)) {
396 KdPrint2((PRINT_PREFIX " AHCI init failed - not detected\n"));
397 return STATUS_UNSUCCESSFUL;
398 }
399 KdPrint2((PRINT_PREFIX " unknown AHCI dev, addr %#x ", deviceExtension->BaseIoAHCI_0.Addr));
400 }
401 KdPrint2((PRINT_PREFIX " unknown dev, BM addr %#x ", BaseIoAddressBM));
402 DevTypeInfo = NULL;
403 KdPrint2((PRINT_PREFIX " MaxTransferMode %#x\n", deviceExtension->MaxTransferMode));
404
405 if(!UniataChipDetectChannels(HwDeviceExtension, pciData, DeviceNumber, ConfigInfo)) {
406 return STATUS_UNSUCCESSFUL;
407 }
408 if(!UniataAllocateLunExt(deviceExtension, UNIATA_ALLOCATE_NEW_LUNS)) {
409 return STATUS_UNSUCCESSFUL;
410 }
411 return STATUS_SUCCESS;
412 }
413
414 static BUSMASTER_CONTROLLER_INFORMATION_BASE const SiSAdapters[] = {
415 PCI_DEV_HW_SPEC_BM( 1183, 1039, 0x00, ATA_SA150, "SiS 1183 IDE" , SIS133NEW),
416 PCI_DEV_HW_SPEC_BM( 1182, 1039, 0x00, ATA_SA150, "SiS 1182" , SISSATA | UNIATA_SATA),
417 PCI_DEV_HW_SPEC_BM( 0183, 1039, 0x00, ATA_SA150, "SiS 183 RAID" , SISSATA | UNIATA_SATA),
418 PCI_DEV_HW_SPEC_BM( 0182, 1039, 0x00, ATA_SA150, "SiS 182" , SISSATA | UNIATA_SATA),
419 PCI_DEV_HW_SPEC_BM( 0181, 1039, 0x00, ATA_SA150, "SiS 181" , SISSATA | UNIATA_SATA),
420 PCI_DEV_HW_SPEC_BM( 0180, 1039, 0x00, ATA_SA150, "SiS 180" , SISSATA | UNIATA_SATA),
421 PCI_DEV_HW_SPEC_BM( 0965, 1039, 0x00, ATA_UDMA6, "SiS 965" , SIS133NEW ),
422 PCI_DEV_HW_SPEC_BM( 0964, 1039, 0x00, ATA_UDMA6, "SiS 964" , SIS133NEW ),
423 PCI_DEV_HW_SPEC_BM( 0963, 1039, 0x00, ATA_UDMA6, "SiS 963" , SIS133NEW ),
424 PCI_DEV_HW_SPEC_BM( 0962, 1039, 0x00, ATA_UDMA6, "SiS 962" , SIS133NEW ),
425
426 PCI_DEV_HW_SPEC_BM( 0745, 1039, 0x00, ATA_UDMA5, "SiS 745" , SIS100NEW ),
427 PCI_DEV_HW_SPEC_BM( 0735, 1039, 0x00, ATA_UDMA5, "SiS 735" , SIS100NEW ),
428 PCI_DEV_HW_SPEC_BM( 0733, 1039, 0x00, ATA_UDMA5, "SiS 733" , SIS100NEW ),
429 PCI_DEV_HW_SPEC_BM( 0730, 1039, 0x00, ATA_UDMA5, "SiS 730" , SIS100OLD ),
430
431 PCI_DEV_HW_SPEC_BM( 0646, 1039, 0x00, ATA_UDMA6, "SiS 645DX", SIS133NEW ),
432/* PCI_DEV_HW_SPEC_BM( 0645, 1039, 0x00, ATA_UDMA6, "SiS 645" , SIS133NEW ),*/
433/* PCI_DEV_HW_SPEC_BM( 0640, 1039, 0x00, ATA_UDMA4, "SiS 640" , SIS_SOUTH ),*/
434 PCI_DEV_HW_SPEC_BM( 0635, 1039, 0x00, ATA_UDMA5, "SiS 635" , SIS100NEW ),
435 PCI_DEV_HW_SPEC_BM( 0633, 1039, 0x00, ATA_UDMA5, "SiS 633" , SIS100NEW ),
436 PCI_DEV_HW_SPEC_BM( 0630, 1039, 0x30, ATA_UDMA5, "SiS 630S" , SIS100OLD ),
437 PCI_DEV_HW_SPEC_BM( 0630, 1039, 0x00, ATA_UDMA4, "SiS 630" , SIS66 ),
438 PCI_DEV_HW_SPEC_BM( 0620, 1039, 0x00, ATA_UDMA4, "SiS 620" , SIS66 ),
439
440 PCI_DEV_HW_SPEC_BM( 0550, 1039, 0x00, ATA_UDMA5, "SiS 550" , SIS66 ),
441 PCI_DEV_HW_SPEC_BM( 0540, 1039, 0x00, ATA_UDMA4, "SiS 540" , SIS66 ),
442 PCI_DEV_HW_SPEC_BM( 0530, 1039, 0x00, ATA_UDMA4, "SiS 530" , SIS66 ),
443
444// PCI_DEV_HW_SPEC_BM( 0008, 1039, 0x04, ATA_UDMA6, "SiS 962L" , SIS133OLD ), // ???
445// PCI_DEV_HW_SPEC_BM( 0008, 1039, 0x00, ATA_UDMA6, "SiS 961" , SIS133OLD ),
446
447 PCI_DEV_HW_SPEC_BM( 5517, 1039, 0x00, ATA_UDMA5, "SiS 961" , SIS100NEW | SIS_BASE ),
448 PCI_DEV_HW_SPEC_BM( 5518, 1039, 0x00, ATA_UDMA6, "SiS 962/3", SIS133NEW | SIS_BASE ),
449 PCI_DEV_HW_SPEC_BM( 5513, 1039, 0xc2, ATA_UDMA2, "SiS 5513" , SIS33 | SIS_BASE ),
450 PCI_DEV_HW_SPEC_BM( 5513, 1039, 0x00, ATA_WDMA2, "SiS 5513" , SIS33 | SIS_BASE ),
451 PCI_DEV_HW_SPEC_BM( 0601, 1039, 0x00, ATA_UDMA2, "SiS 5513" , SIS33 | SIS_BASE ),
452 PCI_DEV_HW_SPEC_BM( ffff, ffff, 0xff, BMLIST_TERMINATOR , NULL , BMLIST_TERMINATOR )
453 };
454
455 static BUSMASTER_CONTROLLER_INFORMATION_BASE const ViaAdapters[] = {
456 PCI_DEV_HW_SPEC_BM( 0586, 1106, 0x41, ATA_UDMA2, "VIA 82C586B", VIA33 | 0x00 ),
457 PCI_DEV_HW_SPEC_BM( 0586, 1106, 0x40, ATA_UDMA2, "VIA 82C586B", VIA33 | VIAPRQ ),
458 PCI_DEV_HW_SPEC_BM( 0586, 1106, 0x02, ATA_UDMA2, "VIA 82C586B", VIA33 | 0x00 ),
459 PCI_DEV_HW_SPEC_BM( 0586, 1106, 0x00, ATA_WDMA2, "VIA 82C586" , VIA33 | 0x00 ),
460 PCI_DEV_HW_SPEC_BM( 0596, 1106, 0x12, ATA_UDMA4, "VIA 82C596B", VIA66 | VIACLK ),
461 PCI_DEV_HW_SPEC_BM( 0596, 1106, 0x00, ATA_UDMA2, "VIA 82C596" , VIA33 | 0x00 ),
462 PCI_DEV_HW_SPEC_BM( 0686, 1106, 0x40, ATA_UDMA5, "VIA 82C686B", VIA100 | VIABUG ),
463 PCI_DEV_HW_SPEC_BM( 0686, 1106, 0x10, ATA_UDMA4, "VIA 82C686A", VIA66 | VIACLK ),
464 PCI_DEV_HW_SPEC_BM( 0686, 1106, 0x00, ATA_UDMA2, "VIA 82C686" , VIA33 | 0x00 ),
465 PCI_DEV_HW_SPEC_BM( 8231, 1106, 0x00, ATA_UDMA5, "VIA 8231" , VIA100 | VIABUG ),
466 PCI_DEV_HW_SPEC_BM( 3074, 1106, 0x00, ATA_UDMA5, "VIA 8233" , VIA100 | 0x00 ),
467 PCI_DEV_HW_SPEC_BM( 3109, 1106, 0x00, ATA_UDMA5, "VIA 8233C" , VIA100 | 0x00 ),
468 PCI_DEV_HW_SPEC_BM( 3147, 1106, 0x00, ATA_UDMA6, "VIA 8233A" , VIA133 | 0x00 ),
469 PCI_DEV_HW_SPEC_BM( 3177, 1106, 0x00, ATA_UDMA6, "VIA 8235" , VIA133 | 0x00 ),
470 PCI_DEV_HW_SPEC_BM( 3227, 1106, 0x00, ATA_UDMA6, "VIA 8237" , VIA133 | 0x00 ),
471 PCI_DEV_HW_SPEC_BM( 0591, 1106, 0x00, ATA_UDMA6, "VIA 8237A" , VIA133 | 0x00 ),
472 // presence of AHCI controller means something about isa-mapped part
473 PCI_DEV_HW_SPEC_BM( 5337, 1106, 0x00, ATA_UDMA6, "VIA 8237S" , VIA133 | 0x00 ),
474 PCI_DEV_HW_SPEC_BM( 5372, 1106, 0x00, ATA_UDMA6, "VIA 8237" , VIA133 | 0x00 ),
475 PCI_DEV_HW_SPEC_BM( 7372, 1106, 0x00, ATA_UDMA6, "VIA 8237" , VIA133 | 0x00 ),
476 PCI_DEV_HW_SPEC_BM( 3349, 1106, 0x00, ATA_UDMA6, "VIA 8251" , VIA133 | 0x00 ),
477 PCI_DEV_HW_SPEC_BM( 8324, 1106, 0x00, ATA_SA150, "VIA CX700" , VIANEW | VIASATA),
478 PCI_DEV_HW_SPEC_BM( 8353, 1106, 0x00, ATA_SA150, "VIA VX800" , VIANEW | VIASATA),
479 PCI_DEV_HW_SPEC_BM( 8409, 1106, 0x00, ATA_UDMA6, "VIA VX855" , VIA133 | 0x00 ),
480 PCI_DEV_HW_SPEC_BM( 8410, 1106, 0x00, ATA_SA300, "VIA VX900" , VIANEW | VIASATA),
481 PCI_DEV_HW_SPEC_BM( ffff, ffff, 0xff, BMLIST_TERMINATOR , NULL , BMLIST_TERMINATOR )
482 };
483
484 static BUSMASTER_CONTROLLER_INFORMATION_BASE const ViaSouthAdapters[] = {
485 PCI_DEV_HW_SPEC_BM( 3112, 1106, 0x00, ATA_MODE_NOT_SPEC, "VIA 8361", VIASOUTH ),
486 PCI_DEV_HW_SPEC_BM( 0305, 1106, 0x00, ATA_MODE_NOT_SPEC, "VIA 8363", VIASOUTH ),
487 PCI_DEV_HW_SPEC_BM( 0391, 1106, 0x00, ATA_MODE_NOT_SPEC, "VIA 8371", VIASOUTH ),
488 PCI_DEV_HW_SPEC_BM( 3102, 1106, 0x00, ATA_MODE_NOT_SPEC, "VIA 8662", VIASOUTH ),
489 PCI_DEV_HW_SPEC_BM( ffff, ffff, 0xff, BMLIST_TERMINATOR, NULL , BMLIST_TERMINATOR )
490 };
491
492 KdPrint2((PRINT_PREFIX "VendorID/DeviceID/Rev %#x/%#x/%#x\n", VendorID, DeviceID, RevID));
493
494 switch(VendorID) {
495
496 case ATA_SIS_ID:
497 /*
498 We shall get here for all SIS controllers, even unlisted.
499 Then perform bus scan to find SIS bridge and decide what to do with controller
500 */
501 KdPrint2((PRINT_PREFIX "ATA_SIS_ID\n"));
502 DevTypeInfo = (BUSMASTER_CONTROLLER_INFORMATION_BASE*)&SiSAdapters[0];
503 i = AtapiFindListedDev(DevTypeInfo, -1, HwDeviceExtension, SystemIoBusNumber, PCISLOTNUM_NOT_SPECIFIED, NULL);
504 if(i != BMLIST_TERMINATOR) {
505 deviceExtension->FullDevName = SiSAdapters[i].FullDevName;
506 }
507 goto for_ugly_chips;
508
509 case ATA_VIA_ID:
510 KdPrint2((PRINT_PREFIX "ATA_VIA_ID\n"));
511 // New chips have own DeviceId
512 if(deviceExtension->DevID != ATA_VIA82C571 &&
513 deviceExtension->DevID != ATA_VIACX700IDE &&
514 deviceExtension->DevID != ATA_VIASATAIDE &&
515 deviceExtension->DevID != ATA_VIASATAIDE2 &&
516 deviceExtension->DevID != ATA_VIASATAIDE3) {
517 KdPrint2((PRINT_PREFIX "Via new\n"));
518 break;
519 }
520 KdPrint2((PRINT_PREFIX "Via-old-style %x\n", deviceExtension->DevID));
521 // Traditionally, chips have same DeviceId, we can distinguish between them
522 // only by ISA Bridge DeviceId
523 DevTypeInfo = (BUSMASTER_CONTROLLER_INFORMATION_BASE*)&ViaSouthAdapters[0];
524 i = AtapiFindListedDev(DevTypeInfo, -1, HwDeviceExtension, SystemIoBusNumber,
525 PCISLOTNUM_NOT_SPECIFIED/*slotNumber*/, NULL);
526/* if(i == BMLIST_TERMINATOR) {
527 i = AtapiFindListedDev(DevTypeInfo, -1, HwDeviceExtension, SystemIoBusNumber, PCISLOTNUM_NOT_SPECIFIED, NULL);
528 }*/
529 if(i != BMLIST_TERMINATOR) {
530 KdPrint2((PRINT_PREFIX "VIASOUTH\n"));
531 deviceExtension->HwFlags |= VIASOUTH;
532 }
533 DevTypeInfo = (BUSMASTER_CONTROLLER_INFORMATION_BASE*)&ViaAdapters[0];
534 i = AtapiFindListedDev(DevTypeInfo, -1, HwDeviceExtension, SystemIoBusNumber,
535 PCISLOTNUM_NOT_SPECIFIED/*slotNumber*/, NULL);
536 if(i != BMLIST_TERMINATOR) {
537 deviceExtension->FullDevName = ViaAdapters[i].FullDevName;
538 }
539 goto for_ugly_chips;
540
541 default:
542
543 // do nothing
544 break;
545
546#if 0
547 KdPrint2((PRINT_PREFIX "Default\n"));
548
549 deviceExtension->MaxTransferMode = deviceExtension->BaseIoAddressBM_0 ? ATA_DMA : ATA_PIO4;
550 /* do extra chipset specific setups */
551 switch(deviceExtension->DevID) {
552
553 //case ATA_CYPRESS_ID:
554 case 0xc6931080: /* 82c693 ATA controller */
555 deviceExtension->MaxTransferMode = ATA_WDMA2;
556 break;
557
558 case 0x000116ca: /* Cenatek Rocket Drive controller */
559 deviceExtension->MaxTransferMode = ATA_WDMA2;
560 break;
561
562/* case ATA_CYRIX_ID:
563 DevTypeInfo = &CyrixAdapters[0];
564 break;*/
565 case 0x01021078: /* Cyrix 5530 ATA33 controller */
566 deviceExtension->MaxTransferMode = ATA_UDMA2;
567 break;
568
569 case 0x06401039: /* CMD 640 known bad, no DMA */
570 case 0x06011039:
571 *simplexOnly = TRUE;
572
573 /* FALLTHROUGH */
574
575 case 0x10001042: /* RZ 100x known bad, no DMA */
576 case 0x10011042:
577
578 if(deviceExtension->BaseIoAddressBM_0)
579 ScsiPortFreeDeviceBase(HwDeviceExtension,
580 deviceExtension->BaseIoAddressBM_0);
581
582 UniataInitIoResEx(&deviceExtension->BaseIoAddressBM_0, 0, FALSE, FALSE);
583 deviceExtension->BusMaster = DMA_MODE_NONE;
584 deviceExtension->MaxTransferMode = ATA_PIO4;
585 break;
586
587 case 0x81721283: /* IT8172 IDE controller */
588 deviceExtension->MaxTransferMode = ATA_UDMA2;
589 *simplexOnly = TRUE;
590 break;
591
592 default:
593 return STATUS_NOT_FOUND;
594 }
595 return STATUS_SUCCESS;
596#endif
597 }
598
599 i = Ata_is_dev_listed(DevTypeInfo, VendorID, DeviceID, RevID, -1);
600for_ugly_chips:
601 KdPrint2((PRINT_PREFIX "i: %#x\n", i));
602 if(i == BMLIST_TERMINATOR) {
603 goto unknown_dev;
604 //return STATUS_NOT_FOUND;
605 }
606 deviceExtension->MaxTransferMode = DevTypeInfo[i].MaxTransferMode;
607 deviceExtension->HwFlags |= DevTypeInfo[i].RaidFlags;
608
609 KdPrint2((PRINT_PREFIX "HwFlags: %#x\n", deviceExtension->HwFlags));
610
611 tmp32 = AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"HwFlagsOverride", deviceExtension->HwFlags);
612 KdPrint2((PRINT_PREFIX "HwFlagsOverride: %#x\n", tmp32));
613 deviceExtension->HwFlags = tmp32;
614
615 tmp32 = AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"HwFlagsAdd", 0);
616 KdPrint2((PRINT_PREFIX "HwFlagsAdd: %#x\n", tmp32));
617 deviceExtension->HwFlags |= tmp32;
618
619 KdPrint2((PRINT_PREFIX "HwFlags (final): %#x\n", deviceExtension->HwFlags));
620 if(deviceExtension->HwFlags & UNIATA_SIMPLEX_ONLY) {
621 KdPrint2((PRINT_PREFIX "UNIATA_SIMPLEX_ONLY\n" ));
622 *simplexOnly = TRUE;
623 }
624
625 KdPrint2((PRINT_PREFIX "MaxTransferMode: %#x\n", deviceExtension->MaxTransferMode));
626 tmp32 = AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"MaxTransferMode", deviceExtension->MaxTransferMode);
627 if(tmp32 != 0xffffffff) {
628 KdPrint2((PRINT_PREFIX "MaxTransferMode (overriden): %#x\n", deviceExtension->MaxTransferMode));
629 deviceExtension->MaxTransferMode = tmp32;
630 }
631
632 if(deviceExtension->MaxTransferMode >= ATA_SA150) {
633 KdPrint2((PRINT_PREFIX "setting UNIATA_SATA flag\n"));
634 deviceExtension->HwFlags |= UNIATA_SATA;
635 }
636
637/*
638 ConfigInfo->MaximumTransferLength = DEV_BSIZE*256;
639 deviceExtension->MaximumDmaTransferLength = ConfigInfo->MaximumTransferLength;
640*/
641 ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
642 ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
643
644 /* for even more ugly AHCI-capable chips */
645 if(ChipFlags & UNIATA_AHCI) {
646 /*
647 Seems, some chips may have inoperable/alternative BAR5 in SATA mode
648 This can be detected via PCI SubClass
649 */
650 switch(VendorID) {
651 case ATA_NVIDIA_ID:
652 case ATA_ATI_ID:
653 KdPrint2((PRINT_PREFIX "ATA_xxx_ID check AHCI subclass\n"));
654 if((pciData)->SubClass == PCI_DEV_SUBCLASS_IDE) {
655 KdPrint2((PRINT_PREFIX "Non-AHCI mode\n"));
656 ChipFlags &= ~UNIATA_AHCI;
657 deviceExtension->HwFlags &= ~UNIATA_AHCI;
658 }
659 break;
660 default:
661 if(!ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[5].RangeStart)) {
662 KdPrint2((PRINT_PREFIX "No BAR5, try BM\n"));
663 ChipFlags &= ~UNIATA_AHCI;
664 deviceExtension->HwFlags &= ~UNIATA_AHCI;
665 }
666 break;
667 }
668 }
669
670 if(ChipFlags & UNIATA_AHCI) {
671
672 deviceExtension->NumberChannels = 0;
673 if(!UniataAhciDetect(HwDeviceExtension, pciData, ConfigInfo)) {
674 KdPrint2((PRINT_PREFIX " AHCI detect failed\n"));
675 return STATUS_UNSUCCESSFUL;
676 }
677
678 } else
679 if(!UniataChipDetectChannels(HwDeviceExtension, pciData, DeviceNumber, ConfigInfo)) {
680 return STATUS_UNSUCCESSFUL;
681 }
682 // UniataAhciDetect() sets proper number of channels
683 if(!UniataAllocateLunExt(deviceExtension, UNIATA_ALLOCATE_NEW_LUNS)) {
684 return STATUS_UNSUCCESSFUL;
685 }
686
687 switch(VendorID) {
688 case ATA_ACER_LABS_ID:
689 if(ChipFlags & UNIATA_SATA) {
690 deviceExtension->AltRegMap = TRUE; // inform generic resource allocator
691 BaseIoAddress1 = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
692 0, 0, 0x10);
693 BaseIoAddress2 = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
694 1, 0, 0x10);
695 BaseIoAddressBM = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
696 4, 0, deviceExtension->NumberChannels*sizeof(IDE_BUSMASTER_REGISTERS));
697 for(c=0; c<deviceExtension->NumberChannels; c++) {
698 //ULONG unit01 = (c & 1);
699 ULONG unit10 = (c & 2);
700 chan = &deviceExtension->chan[c];
701
702 for (i=0; i<=IDX_IO1_SZ; i++) {
703 UniataInitIoRes(chan, IDX_IO1+i, BaseIoAddress1 + i + (unit10 ? 8 : 0), FALSE, FALSE);
704 }
705 UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseIoAddress2 + 2 + (unit10 ? 4 : 0), FALSE, FALSE);
706 UniataInitSyncBaseIO(chan);
707
708 for (i=0; i<=IDX_BM_IO_SZ; i++) {
709 UniataInitIoRes(chan, IDX_BM_IO+i, BaseIoAddressBM + i + (c * sizeof(IDE_BUSMASTER_REGISTERS)), FALSE, FALSE);
710 }
711
712 // SATA not supported yet
713
714 //chan->RegTranslation[IDX_BM_Command] = BaseMemAddress + 0x260 + offs7;
715 //chan->RegTranslation[IDX_BM_PRD_Table] = BaseMemAddress + 0x244 + offs7;
716 //chan->RegTranslation[IDX_BM_DeviceSpecific0] = BaseMemAddress + (c << 2);
717
718 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
719 }
720 }
721 break;
722 case ATA_NVIDIA_ID:
723 if(ChipFlags & UNIATA_SATA) {
724 KdPrint2((PRINT_PREFIX "NVIDIA SATA\n"));
725 BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
726 5, 0, ((ChipFlags & NV4OFF) ? 0x400 : 0) + 0x40*2);
727 KdPrint2((PRINT_PREFIX "BaseMemAddress %x\n", BaseMemAddress));
728 if(!BaseMemAddress) {
729 return STATUS_UNSUCCESSFUL;
730 }
731 if((*ConfigInfo->AccessRanges)[5].RangeInMemory) {
732 KdPrint2((PRINT_PREFIX "MemIo\n"));
733 MemIo = TRUE;
734 }
735 UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE);
736 for(c=0; c<deviceExtension->NumberChannels; c++) {
737 chan = &deviceExtension->chan[c];
738
739 UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + (c << 6), MemIo, FALSE);
740 UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 4 + (c << 6), MemIo, FALSE);
741 UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 8 + (c << 6), MemIo, FALSE);
742
743 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
744 }
745 }
746 break;
747 case ATA_PROMISE_ID:
748
749 if(ChipType != PRMIO) {
750 break;
751 }
752 if(!pciData) {
753 break;
754 }
755 deviceExtension->AltRegMap = TRUE; // inform generic resource allocator
756
757 /* BAR4 -> res1 */
758 BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
759 4, 0, 0x4000);
760 KdPrint2((PRINT_PREFIX "BaseMemAddress[4] %x\n", BaseMemAddress));
761 if(!BaseMemAddress) {
762 return STATUS_UNSUCCESSFUL;
763 }
764 if((*ConfigInfo->AccessRanges)[4].RangeInMemory) {
765 KdPrint2((PRINT_PREFIX "MemIo\n"));
766 MemIo = TRUE;
767 }
768 UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE);
769
770 /* BAR3 -> res2 */
771 BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
772 3, 0, 0xd0000);
773 KdPrint2((PRINT_PREFIX "BaseMemAddress[3] %x\n", BaseMemAddress));
774 if(!BaseMemAddress) {
775 return STATUS_UNSUCCESSFUL;
776 }
777 if((*ConfigInfo->AccessRanges)[3].RangeInMemory) {
778 KdPrint2((PRINT_PREFIX "MemIo\n"));
779 MemIo = TRUE;
780 }
781 UniataInitIoResEx(&deviceExtension->BaseIoAddressBM_0, BaseMemAddress, MemIo, FALSE);
782
783 if(!(ChipFlags & UNIATA_SATA)) {
784 UCHAR reg48;
785
786 reg48 = AtapiReadPortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x48);
787 deviceExtension->NumberChannels = ((reg48 & 0x01) ? 1 : 0) +
788 ((reg48 & 0x02) ? 1 : 0) +
789 2;
790 KdPrint2((PRINT_PREFIX "Channels -> %d\n", deviceExtension->NumberChannels));
791 }
792
793 for(c=0; c<deviceExtension->NumberChannels; c++) {
794
795 /* res2-based */
796 ULONG offs8, offs7;
797
798 chan = &deviceExtension->chan[c];
799
800 offs8 = c << 8;
801 offs7 = c << 7;
802
803 for (i=0; i<=IDX_IO1_SZ; i++) {
804 UniataInitIoRes(chan, IDX_IO1+i, BaseMemAddress + 0x200 + (i << 2) + offs8, MemIo, FALSE);
805 }
806 UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseMemAddress + 0x238 + offs7, MemIo, FALSE);
807
808 UniataInitSyncBaseIO(chan);
809
810 UniataInitIoRes(chan, IDX_BM_Command, BaseMemAddress + 0x260 + offs7, MemIo, FALSE);
811 UniataInitIoRes(chan, IDX_BM_PRD_Table, BaseMemAddress + 0x244 + offs7, MemIo, FALSE);
812 UniataInitIoRes(chan, IDX_BM_DeviceSpecific0, BaseMemAddress + (c << 2), MemIo, FALSE);
813
814 if((ChipFlags & PRSATA) ||
815 ((ChipFlags & PRCMBO) && c<2)) {
816 KdPrint2((PRINT_PREFIX "Promise SATA\n"));
817
818 UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + 0x400 + offs7, MemIo, FALSE);
819 UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 0x404 + offs7, MemIo, FALSE);
820 UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 0x408 + offs7, MemIo, FALSE);
821
822 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
823 } else {
824 KdPrint2((PRINT_PREFIX "Promise PATA\n"));
825 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA6);
826 }
827 }
828 break;
829
830 case ATA_ATI_ID:
831 KdPrint2((PRINT_PREFIX "ATI\n"));
832 if(ChipType == ATI700) {
833 KdPrint2((PRINT_PREFIX "ATI700\n"));
834 if(!(ChipFlags & UNIATA_AHCI)) {
835 KdPrint2((PRINT_PREFIX "IXP700 PATA\n"));
836 chan = &deviceExtension->chan[0];
837 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA5);
838 }
839 break;
840 }
841 /* FALLTHROUGH */
842 case ATA_SILICON_IMAGE_ID: {
843
844 if(ChipFlags & SIIBUG) {
845 }
846 if(ChipType != SIIMIO) {
847 break;
848 }
849 if(!pciData) {
850 break;
851 }
852
853 if(VendorID == ATA_SILICON_IMAGE_ID) {
854 KdPrint2((PRINT_PREFIX "New SII\n"));
855 } else {
856 KdPrint2((PRINT_PREFIX "ATI SATA\n"));
857 }
858 //if(deviceExtension->HwFlags & SII4CH) {
859 deviceExtension->AltRegMap = TRUE; // inform generic resource allocator
860 //}
861 BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
862 5, 0, 0x800);
863 KdPrint2((PRINT_PREFIX "BaseMemAddress %x\n", BaseMemAddress));
864 if(!BaseMemAddress) {
865 return STATUS_UNSUCCESSFUL;
866 }
867 if((*ConfigInfo->AccessRanges)[5].RangeInMemory) {
868 KdPrint2((PRINT_PREFIX "MemIo\n"));
869 MemIo = TRUE;
870 }
871 UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE);
872
873 for(c=0; c<deviceExtension->NumberChannels; c++) {
874 ULONG unit01 = (c & 1);
875 ULONG unit10 = (c & 2);
876
877 chan = &deviceExtension->chan[c];
878
879 if(deviceExtension->AltRegMap) {
880 for (i=0; i<=IDX_IO1_SZ; i++) {
881 UniataInitIoRes(chan, IDX_IO1+i, BaseMemAddress + 0x80 + i + (unit01 << 6) + (unit10 << 8), MemIo, FALSE);
882 }
883 UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseMemAddress + 0x8a + (unit01 << 6) + (unit10 << 8), MemIo, FALSE);
884 UniataInitSyncBaseIO(chan);
885
886 UniataInitIoRes(chan, IDX_BM_Command, BaseMemAddress + 0x00 + (unit01 << 3) + (unit10 << 8), MemIo, FALSE);
887 UniataInitIoRes(chan, IDX_BM_Status, BaseMemAddress + 0x02 + (unit01 << 3) + (unit10 << 8), MemIo, FALSE);
888 UniataInitIoRes(chan, IDX_BM_PRD_Table, BaseMemAddress + 0x04 + (unit01 << 3) + (unit10 << 8), MemIo, FALSE);
889 UniataInitIoRes(chan, IDX_BM_DeviceSpecific0, BaseMemAddress + 0x10 + (unit01 << 3) + (unit10 << 8), MemIo, FALSE);
890 UniataInitIoRes(chan, IDX_BM_DeviceSpecific1, BaseMemAddress + 0x40 + (unit01 << 2) + (unit10 << 8), MemIo, FALSE);
891 }
892
893 if(chan->MaxTransferMode < ATA_SA150) {
894 // do nothing for PATA part
895 KdPrint2((PRINT_PREFIX "No SATA regs for PATA part\n"));
896 } else
897 if(ChipFlags & UNIATA_SATA) {
898 UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + 0x104 + (unit01 << 7) + (unit10 << 8), MemIo, FALSE);
899 UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 0x108 + (unit01 << 2) + (unit10 << 8), MemIo, FALSE);
900 UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 0x100 + (unit01 << 2) + (unit10 << 8), MemIo, FALSE);
901
902 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
903 }
904 }
905 break; }
906
907 case ATA_SERVERWORKS_ID: {
908
909 if(ChipType != SWKSMIO) {
910 break;
911 }
912 if(!pciData) {
913 break;
914 }
915
916 KdPrint2((PRINT_PREFIX "ServerWorks\n"));
917
918 deviceExtension->AltRegMap = TRUE; // inform generic resource allocator
919 BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
920 5, 0, 0x400);
921 KdPrint2((PRINT_PREFIX "BaseMemAddress %x\n", BaseMemAddress));
922 if(!BaseMemAddress) {
923 return STATUS_UNSUCCESSFUL;
924 }
925 if((*ConfigInfo->AccessRanges)[5].RangeInMemory) {
926 KdPrint2((PRINT_PREFIX "MemIo\n"));
927 MemIo = TRUE;
928 }
929 UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE);
930
931 for(c=0; c<deviceExtension->NumberChannels; c++) {
932 ULONG offs = c*0x100;
933
934 chan = &deviceExtension->chan[c];
935 for (i=0; i<=IDX_IO1_SZ; i++) {
936 UniataInitIoRes(chan, IDX_IO1+i, BaseMemAddress + offs + i*4, MemIo, FALSE);
937 }
938 UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseMemAddress + offs + 0x20, MemIo, FALSE);
939 UniataInitSyncBaseIO(chan);
940
941 UniataInitIoRes(chan, IDX_BM_Command, BaseMemAddress + offs + 0x30, MemIo, FALSE);
942 UniataInitIoRes(chan, IDX_BM_Status, BaseMemAddress + offs + 0x32, MemIo, FALSE);
943 UniataInitIoRes(chan, IDX_BM_PRD_Table, BaseMemAddress + offs + 0x34, MemIo, FALSE);
944
945 UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + offs + 0x40, MemIo, FALSE);
946 UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + offs + 0x44, MemIo, FALSE);
947 UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + offs + 0x48, MemIo, FALSE);
948
949 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
950 }
951 break; }
952
953 case ATA_SIS_ID: {
954 //if(ChipType != SIS_SOUTH) {}
955 BOOLEAN SIS_182=FALSE;
956
957 if(!(ChipFlags & SIS_BASE)) {
958 KdPrint2((PRINT_PREFIX "Found SIS_SOUTH\n"));
959 //PrintNtConsole("Found SIS_SOUTH\n");
960 break;
961 }
962 // Make some additional checks
963 KdPrint2((PRINT_PREFIX "ChipType == SIS_BASE\n"));
964 ChangePciConfig1(0x57, (a & 0x7f));
965 GetPciConfig4(0x00, tmp32);
966 if(tmp32 == ATA_SIS5518) {
967 ChipType = SIS133NEW;
968 deviceExtension->HwFlags = (deviceExtension->HwFlags & ~CHIPTYPE_MASK) | SIS133NEW;
969 deviceExtension->MaxTransferMode = ATA_UDMA6;
970 KdPrint2((PRINT_PREFIX "UniataChipDetect: SiS 962/963 DMA %#x controller\n", deviceExtension->MaxTransferMode));
971 //PrintNtConsole("UniataChipDetect: SiS 962/963 DMA %#x controller\n", deviceExtension->MaxTransferMode);
972 // Restore device ID
973 ChangePciConfig1(0x57, (a | 0x80));
974 } else {
975 static BUSMASTER_CONTROLLER_INFORMATION_BASE const SiSSouthAdapters[] = {
976 PCI_DEV_HW_SPEC_BM( 0008, 1039, 0x10, ATA_MODE_NOT_SPEC, "SiS 961", 0 ),
977// PCI_DEV_HW_SPEC_BM( 0008, 1039, 0x00, ATA_MODE_NOT_SPEC, "SiS 961", 0 ),
978 PCI_DEV_HW_SPEC_BM( ffff, ffff, 0xff, ATA_MODE_NOT_SPEC, NULL , -1 )
979 };
980 // Save settings
981 GetPciConfig1(0x4a, tmp8);
982 ChangePciConfig1(0x4a, (a | 0x10));
983 if(tmp32 == ATA_SIS5513 ||
984 tmp32 == ATA_SIS5517) {
985 i = AtapiFindListedDev((BUSMASTER_CONTROLLER_INFORMATION_BASE*)&SiSSouthAdapters[0],
986 -1, HwDeviceExtension, SystemIoBusNumber, PCISLOTNUM_NOT_SPECIFIED, NULL);
987 if(i != BMLIST_TERMINATOR) {
988 KdPrint2((PRINT_PREFIX "SIS South\n"));
989 deviceExtension->HwFlags = (deviceExtension->HwFlags & ~CHIPTYPE_MASK) | SIS133OLD;
990 deviceExtension->MaxTransferMode = ATA_UDMA6;
991 //deviceExtension->MaxTransferMode = SiSSouthAdapters[i].MaxTransferMode;
992 if(SiSSouthAdapters[i].RaidFlags & UNIATA_SATA) {
993 KdPrint2((PRINT_PREFIX "SIS South SATA\n"));
994 deviceExtension->HwFlags |= UNIATA_SATA;
995 if(SiSSouthAdapters[i].nDeviceId == 0x1182 ||
996 SiSSouthAdapters[i].nDeviceId == 0x1183) {
997 KdPrint2((PRINT_PREFIX "SIS_182\n"));
998 SIS_182 = TRUE;
999 }
1000 }
1001 } else {
1002 // SiS-South not found
1003 if(tmp32 == ATA_SIS5517) {
1004 deviceExtension->HwFlags = (deviceExtension->HwFlags & ~CHIPTYPE_MASK) | SIS100NEW;
1005 deviceExtension->MaxTransferMode = ATA_UDMA5;
1006 } else {
1007 // generic SiS33
1008 KdPrint2((PRINT_PREFIX "Generic SiS DMA\n"));
1009 }
1010 }
1011 }
1012 // Restore settings
1013 SetPciConfig1(0x4a, tmp8);
1014 KdPrint2((PRINT_PREFIX "UniataChipDetect: SiS 961 DMA %#x controller\n", deviceExtension->MaxTransferMode));
1015 //PrintNtConsole("UniataChipDetect: SiS 961 DMA %#x controller\n", deviceExtension->MaxTransferMode);
1016 if(deviceExtension->HwFlags & UNIATA_SATA) {
1017 KdPrint2((PRINT_PREFIX "SiS SATA\n"));
1018
1019 BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
1020 5, 0, 0x400);
1021 KdPrint2((PRINT_PREFIX "BaseMemAddress %x\n", BaseMemAddress));
1022 if(BaseMemAddress) {
1023 if((*ConfigInfo->AccessRanges)[5].RangeInMemory) {
1024 KdPrint2((PRINT_PREFIX "MemIo\n"));
1025 MemIo = TRUE;
1026 }
1027 UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE);
1028
1029 for(c=0; c<deviceExtension->NumberChannels; c++) {
1030 ULONG offs = c << (SIS_182 ? 5 : 6);
1031
1032 chan = &deviceExtension->chan[c];
1033 UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + 0 + offs, MemIo, FALSE);
1034 UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 4 + offs, MemIo, FALSE);
1035 UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 8 + offs, MemIo, FALSE);
1036
1037 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
1038 }
1039 }
1040 }
1041 }
1042 //ChangePciConfig1(0x57, (a | 0x80));
1043 break; }
1044
1045 case ATA_VIA_ID: {
1046
1047 if(ChipFlags & VIASATA) {
1048 /* 2 SATA without SATA registers on first channel + 1 PATA on second */
1049 // do nothing, generic PATA INIT
1050 KdPrint2((PRINT_PREFIX "VIA SATA without SATA regs\n"));
1051 break;
1052 }
1053 if(ChipFlags & UNIATA_SATA) {
1054
1055 ULONG IoSize = 0;
1056 BaseMemAddress = 0;
1057
1058 switch(DeviceID) {
1059 case 0x3149: // VIA 6420
1060 KdPrint2((PRINT_PREFIX "VIA 6420\n"));
1061 IoSize = 0x80;
1062 break;
1063 case 0x3249: // VIA 6421
1064 KdPrint2((PRINT_PREFIX "VIA 6421\n"));
1065 IoSize = 0x40;
1066 break;
1067 }
1068 if(IoSize) {
1069 KdPrint2((PRINT_PREFIX "IoSize %x\n", IoSize));
1070 /*deviceExtension->*/BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
1071 5, 0, IoSize * deviceExtension->NumberChannels);
1072 if(BaseMemAddress && (*ConfigInfo->AccessRanges)[5].RangeInMemory) {
1073 KdPrint2((PRINT_PREFIX "MemIo\n"));
1074 MemIo = TRUE;
1075 }
1076 UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE);
1077 }
1078 if(/*deviceExtension->*/BaseMemAddress) {
1079 KdPrint2((PRINT_PREFIX "UniataChipDetect: BAR5 %x\n", /*deviceExtension->*/BaseMemAddress));
1080 if(ChipFlags & VIABAR) {
1081
1082 ULONG BaseIoAddressBM_0;
1083 ULONG BaseIo;
1084
1085 KdPrint2((PRINT_PREFIX "UniataChipDetect: VIABAR\n"));
1086 /*deviceExtension->*/BaseIoAddressBM_0 = /*(PIDE_BUSMASTER_REGISTERS)*/
1087 AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber, 4, 0,
1088 sizeof(IDE_BUSMASTER_REGISTERS)*deviceExtension->NumberChannels);
1089 deviceExtension->AltRegMap = TRUE; // inform generic resource allocator
1090 for(c=0; c<deviceExtension->NumberChannels; c++) {
1091
1092 chan = &deviceExtension->chan[c];
1093
1094 BaseIo = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber, c, 0, /*0x80*/ sizeof(IDE_REGISTERS_1) + sizeof(IDE_REGISTERS_2)*2);
1095
1096 for (i=0; i<=IDX_IO1_SZ; i++) {
1097 UniataInitIoRes(chan, IDX_IO1+i, BaseIo + i, FALSE, FALSE);
1098 }
1099 UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseIo + sizeof(IDE_REGISTERS_1) + 2, FALSE, FALSE);
1100 UniataInitSyncBaseIO(chan);
1101
1102 for (i=0; i<=IDX_BM_IO_SZ; i++) {
1103 UniataInitIoRes(chan, IDX_BM_IO+i, BaseIoAddressBM_0 + sizeof(IDE_BUSMASTER_REGISTERS)*c + i, FALSE, FALSE);
1104 }
1105
1106 }
1107 }
1108 for(c=0; c<deviceExtension->NumberChannels; c++) {
1109 chan = &deviceExtension->chan[c];
1110 if((ChipFlags & VIABAR) && (c==2)) {
1111 // Do not setup SATA registers for PATA part
1112 for (i=0; i<=IDX_SATA_IO_SZ; i++) {
1113 UniataInitIoRes(chan, IDX_SATA_IO+i, 0, FALSE, FALSE);
1114 }
1115 break;
1116 }
1117 UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + (c * IoSize), MemIo, FALSE);
1118 UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 4 + (c * IoSize), MemIo, FALSE);
1119 UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 8 + (c * IoSize), MemIo, FALSE);
1120
1121 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
1122 }
1123
1124 }
1125 }
1126 break; }
1127 case ATA_INTEL_ID: {
1128
1129 if(!(ChipFlags & UNIATA_SATA)) {
1130 break;
1131 }
1132
1133 /* the intel 31244 needs special care if in DPA mode */
1134 if(DeviceID == 3200 && // Intel 31244
1135 pciData->SubClass != PCI_DEV_SUBCLASS_IDE) {
1136
1137 KdPrint2((PRINT_PREFIX "UniataChipDetect: Intel 31244, DPA mode\n"));
1138 BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
1139 0, 0, 0x0c00);
1140 if(!BaseMemAddress) {
1141 return STATUS_UNSUCCESSFUL;
1142 }
1143 if((*ConfigInfo->AccessRanges)[0].RangeInMemory) {
1144 KdPrint2((PRINT_PREFIX "MemIo\n"));
1145 MemIo = TRUE;
1146 }
1147 deviceExtension->AltRegMap = TRUE; // inform generic resource allocator
1148 UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE);
1149
1150 for(c=0; c<deviceExtension->NumberChannels; c++) {
1151 ULONG offs = 0x200 + c*0x200;
1152
1153 chan = &deviceExtension->chan[c];
1154 for (i=0; i<=IDX_IO1_SZ; i++) {
1155 UniataInitIoRes(chan, IDX_BM_IO+i, BaseMemAddress + i*4 + offs, MemIo, FALSE);
1156 }
1157
1158 UniataInitSyncBaseIO(chan);
1159
1160 UniataInitIoRes(chan, IDX_IO1_o_Command, BaseMemAddress + 0x1d + offs, MemIo, FALSE);
1161 UniataInitIoRes(chan, IDX_IO1_o_Feature, BaseMemAddress + 0x06 + offs, MemIo, FALSE);
1162 UniataInitIoRes(chan, IDX_IO2_o_Control, BaseMemAddress + 0x29 + offs, MemIo, FALSE);
1163
1164 UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseMemAddress + 0x28 + offs, MemIo, FALSE);
1165
1166 UniataInitIoRes(chan, IDX_BM_Command, BaseMemAddress + 0x70 + offs, MemIo, FALSE);
1167 UniataInitIoRes(chan, IDX_BM_Status, BaseMemAddress + 0x72 + offs, MemIo, FALSE);
1168 UniataInitIoRes(chan, IDX_BM_PRD_Table, BaseMemAddress + 0x74 + offs, MemIo, FALSE);
1169
1170 UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + 0x100 + offs, MemIo, FALSE);
1171 UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 0x104 + offs, MemIo, FALSE);
1172 UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 0x108 + offs, MemIo, FALSE);
1173
1174 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
1175 }
1176
1177 break;
1178 }
1179 if(deviceExtension->MaxTransferMode >= ATA_SA150) {
1180
1181 BOOLEAN OrigAHCI = FALSE;
1182
1183 GetPciConfig1(0x90, tmp8);
1184 KdPrint2((PRINT_PREFIX "Intel chip config: %x\n", tmp8));
1185 /* SATA parts can be either compat or AHCI */
1186 MemIo = FALSE;
1187 if(ChipFlags & UNIATA_AHCI) {
1188 OrigAHCI = TRUE;
1189 if(tmp8 & 0xc0) {
1190 //KdPrint2((PRINT_PREFIX "AHCI not supported yet\n"));
1191 //return FALSE;
1192 KdPrint2((PRINT_PREFIX "try run AHCI\n"));
1193 if(ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[5].RangeStart)) {
1194 break;
1195 }
1196 KdPrint2((PRINT_PREFIX "No BAR5, try BM\n"));
1197 deviceExtension->HwFlags &= ~UNIATA_AHCI;
1198 }
1199 BaseIoAddressBM = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
1200 4, 0, sizeof(IDE_BUSMASTER_REGISTERS));
1201 if(BaseIoAddressBM) {
1202 KdPrint2((PRINT_PREFIX "Intel BM check at %x\n", BaseIoAddressBM));
1203 /* check if we really have valid BM registers */
1204 if((*ConfigInfo->AccessRanges)[4].RangeInMemory) {
1205 KdPrint2((PRINT_PREFIX "MemIo[4]\n"));
1206 MemIo = TRUE;
1207 }
1208 UniataInitIoResEx(&deviceExtension->BaseIoAddressBM_0, BaseIoAddressBM, MemIo, FALSE);
1209
1210 tmp8 = AtapiReadPortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),IDX_BM_Status);
1211 KdPrint2((PRINT_PREFIX "BM status: %x\n", tmp8));
1212 /* cleanup */
1213 ScsiPortFreeDeviceBase(HwDeviceExtension, (PCHAR)(ULONG_PTR)BaseIoAddressBM);
1214 UniataInitIoResEx(&deviceExtension->BaseIoAddressBM_0, 0, 0, FALSE);
1215
1216 if(tmp8 == 0xff) {
1217 KdPrint2((PRINT_PREFIX "invalid BM status, keep AHCI mode\n"));
1218 break;
1219 }
1220 }
1221 KdPrint2((PRINT_PREFIX "Compatible mode, reallocate LUNs\n"));
1222 deviceExtension->NumberLuns = 2; // we may be in Legacy mode
1223 if(!UniataAllocateLunExt(deviceExtension, 2)) {
1224 KdPrint2((PRINT_PREFIX "can't re-allocate Luns\n"));
1225 return STATUS_UNSUCCESSFUL;
1226 }
1227 }
1228 deviceExtension->HwFlags &= ~UNIATA_AHCI;
1229
1230 MemIo = FALSE;
1231 /* if BAR(5) is IO it should point to SATA interface registers */
1232 if(OrigAHCI) {
1233 /* Skip BAR(5) in compatible mode */
1234 KdPrint2((PRINT_PREFIX "Ignore BAR5 on compatible\n"));
1235 BaseMemAddress = 0;
1236 } else
1237 if(deviceExtension->DevID == 0x28288086 &&
1238 pciData->u.type0.SubVendorID == 0x106b) {
1239 /* Skip BAR(5) on ICH8M Apples, system locks up on access. */
1240 KdPrint2((PRINT_PREFIX "Ignore BAR5 on ICH8M Apples\n"));
1241 BaseMemAddress = 0;
1242 } else {
1243 BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
1244 5, 0, 0x10);
1245 if(BaseMemAddress && (*ConfigInfo->AccessRanges)[5].RangeInMemory) {
1246 KdPrint2((PRINT_PREFIX "MemIo[5]\n"));
1247 MemIo = TRUE;
1248 }
1249 }
1250 UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE);
1251
1252 for(c=0; c<deviceExtension->NumberChannels; c++) {
1253 chan = &deviceExtension->chan[c];
1254 AtapiSetupLunPtrs(chan, deviceExtension, c);
1255 IsPata = FALSE;
1256 if(ChipFlags & ICH5) {
1257 KdPrint2((PRINT_PREFIX "ICH5\n"));
1258 if ((tmp8 & 0x04) == 0) {
1259 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
1260 } else if ((tmp8 & 0x02) == 0) {
1261 if(c != 0) {
1262 IsPata = TRUE;
1263 //chan->ChannelCtrlFlags |= CTRFLAGS_PATA;
1264 }
1265 } else if ((tmp8 & 0x02) != 0) {
1266 if(c != 1) {
1267 IsPata = TRUE;
1268 //chan->ChannelCtrlFlags |= CTRFLAGS_PATA;
1269 }
1270 }
1271 } else
1272 if(ChipFlags & I6CH2) {
1273 KdPrint2((PRINT_PREFIX "I6CH2\n"));
1274 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
1275 } else {
1276 KdPrint2((PRINT_PREFIX "other Intel\n"));
1277 switch(tmp8 & 0x03) {
1278 case 2:
1279 if(c!=0) {
1280 // PATA
1281 IsPata = TRUE;
1282 }
1283 break;
1284 case 1:
1285 if(c!=1) {
1286 // PATA
1287 IsPata = TRUE;
1288 }
1289 break;
1290 }
1291 }
1292
1293 if(IsPata) {
1294 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA5);
1295 KdPrint2((PRINT_PREFIX "PATA part\n"));
1296 } else {
1297
1298 if(!(ChipFlags & ICH7) && BaseMemAddress) {
1299 KdPrint2((PRINT_PREFIX "BaseMemAddress[5] -> indexed\n"));
1300 UniataInitIoRes(chan, IDX_INDEXED_ADDR, BaseMemAddress + 0, MemIo, FALSE);
1301 UniataInitIoRes(chan, IDX_INDEXED_DATA, BaseMemAddress + 4, MemIo, FALSE);
1302 }
1303 if((ChipFlags & ICH5) || BaseMemAddress) {
1304
1305 KdPrint2((PRINT_PREFIX "io proc()\n"));
1306 // Rather interesting way of register access...
1307 ChipType = INTEL_IDX;
1308 deviceExtension->HwFlags &= ~CHIPTYPE_MASK;
1309 deviceExtension->HwFlags |= ChipType;
1310
1311 if(ChipFlags & ICH7) {
1312 KdPrint2((PRINT_PREFIX "ICH7 way\n"));
1313 }
1314 UniataInitIoRes(chan, IDX_SATA_SStatus, 0x200*c + 0, FALSE, TRUE); // this is fake non-zero value
1315 UniataInitIoRes(chan, IDX_SATA_SError, 0x200*c + 2, FALSE, TRUE);
1316 UniataInitIoRes(chan, IDX_SATA_SControl, 0x200*c + 1, FALSE, TRUE);
1317 }
1318 }
1319
1320 } // end for()
1321
1322 // rest of INIT staff is in AtapiChipInit()
1323
1324 } // ATA_SA150
1325 break; }
1326 case ATA_CYRIX_ID:
1327 /* Cyrix 5530 ATA33 controller */
1328 if(deviceExtension->DevID == 0x01021078) {
1329 ConfigInfo->AlignmentMask = 0x0f;
1330 deviceExtension->MaximumDmaTransferLength = 63*1024;
1331 }
1332 break;
1333 case ATA_JMICRON_ID:
1334 /* New JMicron PATA/SATA controllers */
1335 GetPciConfig1(0xdf, tmp8);
1336 if(tmp8 & 0x40) {
1337 KdPrint((" Check JMicron AHCI\n"));
1338 if(Ata_is_ahci_dev(pciData)) {
1339 ChipFlags |= UNIATA_AHCI;
1340 deviceExtension->HwFlags |= UNIATA_AHCI;
1341 } else {
1342 KdPrint((" JMicron PATA/SATA\n"));
1343 }
1344 } else {
1345#if 0 // do not touch, see Linux sources
1346 /* set controller configuration to a combined setup we support */
1347 SetPciConfig4(0x40, 0x80c0a131);
1348 SetPciConfig4(0x80, 0x01200000);
1349#endif
1350 //GetPciConfig1(0x40, tmp32);
1351 KdPrint((" JMicron Combined\n"));
1352 //return STATUS_NOT_FOUND;
1353 }
1354 break;
1355 }
1356
1357 return STATUS_SUCCESS;
1358
1359} // end UniataChipDetect()
BusMasterAdapters
BUSMASTER_CONTROLLER_INFORMATION_BASE const BusMasterAdapters[]
Definition: bm_devs.h:40
UNIATA_SIMPLEX_ONLY
#define UNIATA_SIMPLEX_ONLY
Definition: bm_devs_decl.h:624
ATA_VIACX700IDE
#define ATA_VIACX700IDE
Definition: bm_devs_decl.h:595
NUM_BUSMASTER_ADAPTERS
#define NUM_BUSMASTER_ADAPTERS
Definition: bm_devs_decl.h:742
ATA_SIS5518
#define ATA_SIS5518
Definition: bm_devs_decl.h:526
SWKSMIO
#define SWKSMIO
Definition: bm_devs_decl.h:661
ATA_VIASATAIDE
#define ATA_VIASATAIDE
Definition: bm_devs_decl.h:597
PBUSMASTER_CONTROLLER_INFORMATION_BASE
struct _BUSMASTER_CONTROLLER_INFORMATION_BASE * PBUSMASTER_CONTROLLER_INFORMATION_BASE
Ata_is_dev_listed
__inline ULONG Ata_is_dev_listed(IN PBUSMASTER_CONTROLLER_INFORMATION_BASE BusMasterAdapters, ULONG VendorId, ULONG DeviceId, ULONG RevId, ULONG lim)
Definition: bm_devs_decl.h:753
ATA_VIA82C571
#define ATA_VIA82C571
Definition: bm_devs_decl.h:572
ATA_VIASATAIDE2
#define ATA_VIASATAIDE2
Definition: bm_devs_decl.h:599
PCI_DEV_HW_SPEC_BM
#define PCI_DEV_HW_SPEC_BM(idhi, idlo, rev, mode, name, flags)
Definition: bm_devs_decl.h:734
ATA_SIS5517
#define ATA_SIS5517
Definition: bm_devs_decl.h:525
VIANEW
#define VIANEW
Definition: bm_devs_decl.h:701
PRCMBO
#define PRCMBO
Definition: bm_devs_decl.h:653
SIIBUG
#define SIIBUG
Definition: bm_devs_decl.h:672
PRSATA
#define PRSATA
Definition: bm_devs_decl.h:652
VIA33
#define VIA33
Definition: bm_devs_decl.h:702
ATA_SIS5513
#define ATA_SIS5513
Definition: bm_devs_decl.h:524
VIA66
#define VIA66
Definition: bm_devs_decl.h:703
VIASOUTH
#define VIASOUTH
Definition: bm_devs_decl.h:712
Ata_is_ahci_dev
#define Ata_is_ahci_dev(pciData)
Definition: bm_devs_decl.h:781
SIS_BASE
#define SIS_BASE
Definition: bm_devs_decl.h:684
BMLIST_TERMINATOR
#define BMLIST_TERMINATOR
Definition: bm_devs_decl.h:738
ATA_VIASATAIDE3
#define ATA_VIASATAIDE3
Definition: bm_devs_decl.h:601
VIA100
#define VIA100
Definition: bm_devs_decl.h:704
ScsiPortFreeDeviceBase
VOID NTAPI ScsiPortFreeDeviceBase(IN PVOID HwDeviceExtension, IN PVOID MappedAddress)
Definition: scsiport.c:549
IDX_INDEXED_ADDR
#define IDX_INDEXED_ADDR
Definition: bsmaster.h:466
IDX_BM_IO
#define IDX_BM_IO
Definition: bsmaster.h:163
AtapiFindListedDev
ULONG NTAPI AtapiFindListedDev(PBUSMASTER_CONTROLLER_INFORMATION_BASE BusMasterAdapters, ULONG lim, IN PVOID HwDeviceExtension, IN ULONG BusNumber, IN ULONG SlotNumber, OUT PCI_SLOT_NUMBER *_slotData)
IDX_SATA_SControl
#define IDX_SATA_SControl
Definition: bsmaster.h:459
IDX_SATA_IO_SZ
#define IDX_SATA_IO_SZ
Definition: bsmaster.h:455
DMA_MODE_NONE
#define DMA_MODE_NONE
Definition: bsmaster.h:1706
IDX_SATA_IO
#define IDX_SATA_IO
Definition: bsmaster.h:453
IDX_INDEXED_DATA
#define IDX_INDEXED_DATA
Definition: bsmaster.h:467
IDX_BM_IO_SZ
#define IDX_BM_IO_SZ
Definition: bsmaster.h:165
AtapiGetIoRange
ULONGIO_PTR NTAPI AtapiGetIoRange(IN PVOID HwDeviceExtension, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN PPCI_COMMON_CONFIG pciData, IN ULONG SystemIoBusNumber, IN ULONG rid, IN ULONG offset, IN ULONG length)
Definition: id_probe.cpp:153
PCI_DEV_SUBCLASS_IDE
#define PCI_DEV_SUBCLASS_IDE
Definition: bsmaster.h:119
PCISLOTNUM_NOT_SPECIFIED
#define PCISLOTNUM_NOT_SPECIFIED
Definition: bsmaster.h:1452
IDX_SATA_SStatus
#define IDX_SATA_SStatus
Definition: bsmaster.h:457
KdPrint
#define KdPrint(x)
Definition: env_spec_w32.h:288
IDX_IO1_o_Feature
#define IDX_IO1_o_Feature
Definition: hwide.h:54
IDX_IO1_o_Command
#define IDX_IO1_o_Command
Definition: hwide.h:60
IDX_IO2_o_Control
#define IDX_IO2_o_Control
Definition: hwide.h:62
UniataAllocateLunExt
BOOLEAN NTAPI UniataAllocateLunExt(PHW_DEVICE_EXTENSION deviceExtension, ULONG NewNumberChannels)
Definition: id_init.cpp:2891
UniataInitIoRes
VOID UniataInitIoRes(IN PHW_CHANNEL chan, IN ULONG idx, IN ULONG addr, IN BOOLEAN MemIo, IN BOOLEAN Proc)
Definition: id_init.cpp:2812
AtapiSetupLunPtrs
VOID NTAPI AtapiSetupLunPtrs(IN PHW_CHANNEL chan, IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG c)
Definition: id_init.cpp:2846
UniataChipDetectChannels
BOOLEAN NTAPI UniataChipDetectChannels(IN PVOID HwDeviceExtension, IN PPCI_COMMON_CONFIG pciData, IN ULONG DeviceNumber, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo)
Definition: id_init.cpp:58
UniataInitIoResEx
VOID UniataInitIoResEx(IN PIORES IoRes, IN ULONG addr, IN BOOLEAN MemIo, IN BOOLEAN Proc)
Definition: id_init.cpp:2829
UniataInitSyncBaseIO
VOID NTAPI UniataInitSyncBaseIO(IN PHW_CHANNEL chan)
Definition: id_init.cpp:2802
UniataAhciDetect
BOOLEAN NTAPI UniataAhciDetect(IN PVOID HwDeviceExtension, IN PPCI_COMMON_CONFIG pciData, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo)
Definition: id_sata.cpp:890
STATUS_SUCCESS
#define STATUS_SUCCESS
Definition: shellext.h:65
STATUS_NOT_FOUND
#define STATUS_NOT_FOUND
Definition: shellext.h:72
_BUSMASTER_CONTROLLER_INFORMATION_BASE
Definition: bm_devs_decl.h:65
_BUSMASTER_CONTROLLER_INFORMATION_BASE::FullDevName
PVEN_STR FullDevName
Definition: bm_devs_decl.h:71
_BUSMASTER_CONTROLLER_INFORMATION_BASE::RaidFlags
ULONG RaidFlags
Definition: bm_devs_decl.h:70
_BUSMASTER_CONTROLLER_INFORMATION_BASE::MaxTransferMode
ULONG MaxTransferMode
Definition: bm_devs_decl.h:69
_HW_DEVICE_EXTENSION::AltRegMap
BOOLEAN AltRegMap
Definition: bsmaster.h:1301
_HW_DEVICE_EXTENSION::FullDevName
PCCH FullDevName
Definition: bsmaster.h:1341
_IDE_BUSMASTER_REGISTERS
Definition: bsmaster.h:134
_IDE_REGISTERS_1
Definition: atapi.h:16
_IDE_REGISTERS_2
Definition: atapi.h:26
PCHAR
char * PCHAR
Definition: typedefs.h:51
STATUS_UNSUCCESSFUL
#define STATUS_UNSUCCESSFUL
Definition: udferr_usr.h:132
ATA_MODE_NOT_SPEC
#define ATA_MODE_NOT_SPEC
Definition: atapi.h:341
IDX_IO2_AltStatus
#define IDX_IO2_AltStatus
Definition: atapi.h:225
ATA_UDMA4
#define ATA_UDMA4
Definition: atapi.h:332
IDX_IO1
#define IDX_IO1
Definition: atapi.h:194
IDX_IO1_SZ
#define IDX_IO1_SZ
Definition: atapi.h:195

Referenced by UniataFindBusMasterController().

◆ UniataChipDetectChannels()

BOOLEAN NTAPI UniataChipDetectChannels ( IN PVOID  HwDeviceExtension,
IN PPCI_COMMON_CONFIG  pciData,
IN ULONG  DeviceNumber,
IN PPORT_CONFIGURATION_INFORMATION  ConfigInfo 
)

Definition at line 58 of file id_init.cpp.

64{
65 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
66 //ULONG slotNumber = deviceExtension->slotNumber;
67 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
68 ULONG VendorID = deviceExtension->DevID & 0xffff;
69 //ULONG DeviceID = (deviceExtension->DevID >> 16) & 0xffff;
70 //ULONG RevID = deviceExtension->RevID;
71 ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
72 ULONG ChipFlags= deviceExtension->HwFlags & CHIPFLAG_MASK;
73 ULONG i,n;
74
75 KdPrint2((PRINT_PREFIX "UniataChipDetectChannels:\n" ));
76
77 deviceExtension->AHCI_PI_mask = 0;
78
79 if(ChipFlags & (UNIATA_SATA | UNIATA_AHCI)) {
80 if(!deviceExtension->NumberChannels) {
81 KdPrint2((PRINT_PREFIX "uninitialized SATA/AHCI port number -> 1\n"));
82 deviceExtension->NumberChannels = 1;
83 }
84 if(AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"IgnoreAhciPM", 1 /* DEBUG */)) {
85 KdPrint2((PRINT_PREFIX "SATA/AHCI w/o PM, max luns 1 or 2\n"));
86 deviceExtension->NumberLuns = 2; // we may be in Legacy mode
87 //chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
88 } else {
89 KdPrint2((PRINT_PREFIX "SATA/AHCI -> possible PM, max luns %d\n", SATA_MAX_PM_UNITS));
90 deviceExtension->NumberLuns = SATA_MAX_PM_UNITS;
91 //deviceExtension->NumberLuns = 1;
92 }
93 }
94 if(deviceExtension->MasterDev) {
95 KdPrint2((PRINT_PREFIX "MasterDev -> 1 chan\n"));
96 deviceExtension->NumberChannels = 1;
97 }
98 for(n=0; n<deviceExtension->NumberChannels; n++) {
99 if(AtapiRegCheckDevValue(deviceExtension, n, DEVNUM_NOT_SPECIFIED, L"Exclude", 0)) {
100 KdPrint2((PRINT_PREFIX "Channel %d excluded\n", n));
101 deviceExtension->AHCI_PI_mask &= ~((ULONG)1 << n);
102 } else {
103 deviceExtension->AHCI_PI_mask |= ((ULONG)1 << n);
104 }
105 }
106 KdPrint2((PRINT_PREFIX "PortMask %#x\n", deviceExtension->AHCI_PI_mask));
107 deviceExtension->AHCI_PI_mask =
108 AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"PortMask", (ULONG)0xffffffff >> (32-deviceExtension->NumberChannels) );
109 KdPrint2((PRINT_PREFIX "Force PortMask %#x\n", deviceExtension->AHCI_PI_mask));
110
111 for(i=deviceExtension->AHCI_PI_mask, n=0; i; n++, i=i>>1);
112 KdPrint2((PRINT_PREFIX "mask -> %d chans\n", n));
113
114 switch(VendorID) {
115 case ATA_ACER_LABS_ID:
116 switch(deviceExtension->DevID) {
117 case 0x528710b9:
118 case 0x528810b9:
119 deviceExtension->NumberChannels = 4;
120 KdPrint2((PRINT_PREFIX "Acer 4 chan\n"));
121 }
122 break;
123 case ATA_PROMISE_ID:
124
125 if(ChipType != PRMIO) {
126 break;
127 }
128 if(!(ChipFlags & UNIATA_SATA)) {
129 deviceExtension->NumberChannels = 4;
130 KdPrint2((PRINT_PREFIX "Promise up to 4 chan\n"));
131 } else
132 if(ChipFlags & PRCMBO) {
133 deviceExtension->NumberChannels = 3;
134 KdPrint2((PRINT_PREFIX "Promise 3 chan\n"));
135 } else {
136 deviceExtension->NumberChannels = 4;
137 KdPrint2((PRINT_PREFIX "Promise 4 chan\n"));
138 }
139 break;
140 case ATA_MARVELL_ID:
141 KdPrint2((PRINT_PREFIX "Marvell\n"));
142 /* AHCI part has own DevID-based workaround */
143 switch(deviceExtension->DevID) {
144 case 0x610111ab:
145 /* 88SX6101 only have 1 PATA channel */
146 if(BMList[deviceExtension->DevIndex].channel) {
147 KdPrint2((PRINT_PREFIX "88SX6101/11 has no 2nd PATA chan\n"));
148 return FALSE;
149 }
150 deviceExtension->NumberChannels = 1;
151 KdPrint2((PRINT_PREFIX "88SX6101 PATA 1 chan\n"));
152 break;
153 }
154 break;
155 case ATA_ATI_ID:
156 KdPrint2((PRINT_PREFIX "ATI\n"));
157 switch(deviceExtension->DevID) {
158 case ATA_ATI_IXP600:
159 KdPrint2((PRINT_PREFIX " IXP600\n"));
160 /* IXP600 only have 1 PATA channel */
161 if(BMList[deviceExtension->DevIndex].channel) {
162 KdPrint2((PRINT_PREFIX "New ATI no 2nd PATA chan\n"));
163 return FALSE;
164 }
165 deviceExtension->NumberChannels = 1;
166 KdPrint2((PRINT_PREFIX "New ATI PATA 1 chan\n"));
167 break;
168
169 case ATA_ATI_IXP700: {
170 UCHAR satacfg = 0;
171 PCI_SLOT_NUMBER slotData;
172 ULONG j, slotNumber;
173
174 KdPrint2((PRINT_PREFIX " IXP700\n"));
175 /*
176 * When "combined mode" is enabled, an additional PATA channel is
177 * emulated with two SATA ports and appears on this device.
178 * This mode can only be detected via SMB controller.
179 */
180 j = AtapiFindListedDev((BUSMASTER_CONTROLLER_INFORMATION_BASE*)&AtiSouthAdapters[0], -1, HwDeviceExtension, SystemIoBusNumber, PCISLOTNUM_NOT_SPECIFIED, &slotData);
181 if(j != BMLIST_TERMINATOR) {
182 slotNumber = slotData.u.AsULONG;
183
184 GetPciConfig1(0xad, satacfg);
185 KdPrint(("SATA controller %s (%s%s channel)\n",
186 (satacfg & 0x01) == 0 ? "disabled" : "enabled",
187 (satacfg & 0x08) == 0 ? "" : "combined mode, ",
188 (satacfg & 0x10) == 0 ? "primary" : "secondary"));
189 /*
190 * If SATA controller is enabled but combined mode is disabled,
191 * we have only one PATA channel. Ignore a non-existent channel.
192 */
193 if ((satacfg & 0x09) == 0x01) {
194 if(BMList[deviceExtension->DevIndex].channel) {
195 KdPrint2((PRINT_PREFIX "New ATI no 2nd PATA chan\n"));
196 return FALSE;
197 }
198 deviceExtension->NumberChannels = 1;
199 KdPrint2((PRINT_PREFIX "New ATI PATA 1 chan\n"));
200 break;
201 } else {
202 KdPrint2((PRINT_PREFIX "New ATI 2 chan\n"));
203 deviceExtension->NumberChannels = 2;
204 /*
205 if (BMList[deviceExtension->DevIndex].channel != ((satacfg & 0x10) >> 4)) {
206 ;
207 }
208 */
209
210 }
211 }
212
213 break; }
214 }
215 /* FALLTHROUGH */
216 case ATA_SILICON_IMAGE_ID:
217
218 if(ChipFlags & SIIBUG) {
219 /* work around errata in early chips */
220 deviceExtension->DmaSegmentLength = 15 * DEV_BSIZE;
221 deviceExtension->DmaSegmentAlignmentMask = 8192-1;
222 }
223 if(ChipType != SIIMIO) {
224 break;
225 }
226 if(!pciData) {
227 break;
228 }
229
230 if(VendorID == ATA_SILICON_IMAGE_ID) {
231 KdPrint2((PRINT_PREFIX "New SII\n"));
232 } else {
233 KdPrint2((PRINT_PREFIX "ATI SATA\n"));
234 }
235 if(deviceExtension->HwFlags & SII4CH) {
236 deviceExtension->NumberChannels = 4;
237 KdPrint2((PRINT_PREFIX "4 chan\n"));
238 }
239 break;
240 case ATA_VIA_ID:
241 if(/*(deviceExtension->DevID == 0x32491106) &&
242 ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[5].RangeStart)*/
243 deviceExtension->HwFlags & VIABAR) {
244 deviceExtension->NumberChannels = 3;
245 KdPrint2((PRINT_PREFIX "VIA 3 chan\n"));
246 }
247 if(ChipFlags & VIASATA) {
248 /* 2 SATA without SATA registers on first channel + 1 PATA on second */
249 // do nothing, generic PATA INIT
250 KdPrint2((PRINT_PREFIX "VIA SATA without SATA regs -> no PM\n"));
251 deviceExtension->NumberLuns = 1;
252 }
253 break;
254 case ATA_ITE_ID:
255 /* ITE ATA133 controller */
256 if(deviceExtension->DevID == 0x82131283) {
257 if(BMList[deviceExtension->DevIndex].channel) {
258 KdPrint2((PRINT_PREFIX "New ITE has no 2nd PATA chan\n"));
259 return FALSE;
260 }
261 deviceExtension->NumberChannels = 1;
262 KdPrint2((PRINT_PREFIX "New ITE PATA 1 chan\n"));
263 }
264 break;
265#if 0
266 case ATA_INTEL_ID:
267 /* New Intel PATA controllers */
268 if(g_opt_VirtualMachine != VM_VBOX &&
269 /*deviceExtension->DevID == 0x27df8086 ||
270 deviceExtension->DevID == 0x269e8086 ||
271 deviceExtension->DevID == ATA_I82801HBM*/
272 ChipFlags & I1CH) {
273 if(BMList[deviceExtension->DevIndex].channel) {
274 KdPrint2((PRINT_PREFIX "New Intel PATA has no 2nd chan\n"));
275 return FALSE;
276 }
277 deviceExtension->NumberChannels = 1;
278 KdPrint2((PRINT_PREFIX "New Intel PATA 1 chan\n"));
279 }
280 break;
281#endif // this code is removed from newer FreeBSD
282#if 0
283 case ATA_JMICRON_ID:
284 /* New JMicron PATA controllers */
285 if(deviceExtension->DevID == ATA_JMB361 ||
286 deviceExtension->DevID == ATA_JMB363 ||
287 deviceExtension->DevID == ATA_JMB365 ||
288 deviceExtension->DevID == ATA_JMB366 ||
289 deviceExtension->DevID == ATA_JMB368) {
290
291 ULONG tmp32, port_mask;
292
293 port_mask = BMList[deviceExtension->DevIndex].channel;
294
295 GetPciConfig4(0x40, tmp32);
296
297 deviceExtension->NumberChannels = 2;
298 //KdPrint2((PRINT_PREFIX "New JMicron PATA 1 chan\n"));
299 }
300 break;
301#endif // this code is unnecessary since port mapping is implemented
302 case ATA_CYRIX_ID:
303 if(ChipType == CYRIX_OLD) {
304 UCHAR tmp8;
305 ULONG slotNumber;
306 slotNumber = deviceExtension->slotNumber;
307 KdPrint2((PRINT_PREFIX "Cyrix slot %#x\n", slotNumber));
308 GetPciConfig1(0x60, tmp8);
309 if(tmp8 & (1 << BMList[deviceExtension->DevIndex].channel)) {
310 KdPrint2((PRINT_PREFIX "Old Cyrix chan %d ok\n", BMList[deviceExtension->DevIndex].channel));
311 } else {
312 KdPrint2((PRINT_PREFIX "Old Cyrix no chan %d\n", BMList[deviceExtension->DevIndex].channel));
313 return FALSE;
314 }
315 }
316 break;
317 } // end switch(VendorID)
318
319 i = AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"NumberChannels", n);
320 if(!i) {
321 i = n;
322 }
323 KdPrint2((PRINT_PREFIX "reg -> %d chans\n", n));
324
325 deviceExtension->NumberChannels = min(i, deviceExtension->NumberChannels);
326 if(!deviceExtension->NumberChannels) {
327 KdPrint2((PRINT_PREFIX "all channels blocked\n", n));
328 return FALSE;
329 }
330 deviceExtension->AHCI_PI_mask &= (ULONG)0xffffffff >> (32-deviceExtension->NumberChannels);
331 KdPrint2((PRINT_PREFIX "Final PortMask %#x\n", deviceExtension->AHCI_PI_mask));
332
333 return TRUE;
334
335} // end UniataChipDetectChannels()
ATA_ATI_IXP600
#define ATA_ATI_IXP600
Definition: bm_devs_decl.h:154
ATA_ATI_IXP700
#define ATA_ATI_IXP700
Definition: bm_devs_decl.h:156
g_opt_VirtualMachine
ULONG g_opt_VirtualMachine
Definition: id_ata.cpp:105
SATA_MAX_PM_UNITS
#define SATA_MAX_PM_UNITS
Definition: bsmaster.h:110
VM_VBOX
#define VM_VBOX
Definition: bsmaster.h:1903
n
GLdouble n
Definition: glext.h:7729
j
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint GLint GLint j
Definition: glfuncs.h:250
AtiSouthAdapters
static BUSMASTER_CONTROLLER_INFORMATION_BASE const AtiSouthAdapters[]
Definition: id_init.cpp:50
_BUSMASTER_CONTROLLER_INFORMATION::channel
CHAR channel
Definition: bm_devs_decl.h:89
_HW_DEVICE_EXTENSION::AHCI_PI_mask
ULONG AHCI_PI_mask
Definition: bsmaster.h:1332

Referenced by UniataChipDetect().

◆ UniataClaimLegacyPCIIDE()

NTSTATUS NTAPI UniataClaimLegacyPCIIDE ( ULONG  i)

Definition at line 1939 of file id_probe.cpp.

1942{
1943 NTSTATUS status;
1944 PCM_RESOURCE_LIST resourceList = NULL;
1945 UNICODE_STRING devname;
1946#ifdef __REACTOS__
1947 PCM_RESOURCE_LIST oldResList = NULL;
1948#endif
1949
1950 KdPrint2((PRINT_PREFIX "UniataClaimLegacyPCIIDE:\n"));
1951
1952 if(BMList[i].PciIdeDevObj) {
1953 KdPrint2((PRINT_PREFIX "Already initialized\n"));
1954 return STATUS_UNSUCCESSFUL;
1955 }
1956
1957 RtlInitUnicodeString(&devname, L"\\Device\\uniata_PCIIDE");
1958 status = IoCreateDevice(SavedDriverObject, sizeof(PCIIDE_DEVICE_EXTENSION),
1959 /*NULL*/ &devname, FILE_DEVICE_UNKNOWN,
1960 0, FALSE, &(BMList[i].PciIdeDevObj));
1961
1962 if(!NT_SUCCESS(status)) {
1963 KdPrint2((PRINT_PREFIX "IoCreateDevice failed %#x\n", status));
1964 return status;
1965 }
1966
1967 resourceList = (PCM_RESOURCE_LIST) ExAllocatePool(PagedPool,
1968 sizeof(CM_RESOURCE_LIST));
1969
1970 if (!resourceList) {
1971 KdPrint2((PRINT_PREFIX "!resourceList\n"));
1972 status = STATUS_INSUFFICIENT_RESOURCES;
1973del_do:
1974 IoDeleteDevice(BMList[i].PciIdeDevObj);
1975 BMList[i].PciIdeDevObj = NULL;
1976#ifdef __REACTOS__
1977 if (oldResList)
1978 ExFreePool(oldResList);
1979#endif
1980 return status;
1981 }
1982
1983 RtlZeroMemory(
1984 resourceList,
1985 sizeof(CM_RESOURCE_LIST));
1986
1987#ifdef __REACTOS__
1988 oldResList = resourceList;
1989#endif
1990
1991 // IoReportDetectedDevice() should be used for WDM OSes
1992
1993 // TODO: check if resourceList is actually used inside HalAssignSlotResources()
1994 // Note: with empty resourceList call to HalAssignSlotResources() fails on some HW
1995 // e.g. Intel ICH4, but works with non-empty.
1996
1997 resourceList->Count = 1;
1998 resourceList->List[0].InterfaceType = PCIBus;
1999 resourceList->List[0].BusNumber = BMList[i].busNumber;
2000 // we do not report IO ranges since they are used/claimed by ISA part(s)
2001 resourceList->List[0].PartialResourceList.Count = 0;
2002
2003 RtlInitUnicodeString(&devname, L"PCIIDE");
2004 status = HalAssignSlotResources(&SavedRegPath,
2005 &devname,
2006 SavedDriverObject,
2007 BMList[i].PciIdeDevObj,
2008 PCIBus,
2009 BMList[i].busNumber,
2010 BMList[i].slotNumber,
2011 &resourceList);
2012
2013 if (!NT_SUCCESS(status)) {
2014 KdPrint2((PRINT_PREFIX "HalAssignSlotResources failed %#x\n", status));
2015 // this is always deallocated inside HalAssignSlotResources() implementation
2016 //ExFreePool(resourceList);
2017 goto del_do;
2018 }
2019
2020#ifdef __REACTOS__
2021 ExFreePool(resourceList);
2022 ExFreePool(oldResList);
2023#endif
2024
2025 KdPrint2((PRINT_PREFIX "ok %#x\n", status));
2026 BMList[i].ChanInitOk |= 0x80;
2027
2028 return status;
2029} // end UniataClaimLegacyPCIIDE()
NTSTATUS
LONG NTSTATUS
Definition: precomp.h:26
SavedRegPath
UNICODE_STRING SavedRegPath
Definition: id_ata.cpp:69
NT_SUCCESS
#define NT_SUCCESS(StatCode)
Definition: apphelp.c:32
HalAssignSlotResources
NTHALAPI NTSTATUS NTAPI HalAssignSlotResources(PUNICODE_STRING, PUNICODE_STRING, PDRIVER_OBJECT, PDEVICE_OBJECT, INTERFACE_TYPE, ULONG, ULONG, PCM_RESOURCE_LIST *)
ExFreePool
#define ExFreePool(addr)
Definition: env_spec_w32.h:352
PagedPool
#define PagedPool
Definition: env_spec_w32.h:308
PCM_RESOURCE_LIST
struct _CM_RESOURCE_LIST * PCM_RESOURCE_LIST
SavedDriverObject
PDRIVER_OBJECT SavedDriverObject
Definition: id_probe.cpp:69
BMList
PBUSMASTER_CONTROLLER_INFORMATION BMList
Definition: id_probe.cpp:53
RtlInitUnicodeString
NTSYSAPI VOID NTAPI RtlInitUnicodeString(PUNICODE_STRING DestinationString, PCWSTR SourceString)
IoCreateDevice
NTSTATUS NTAPI IoCreateDevice(IN PDRIVER_OBJECT DriverObject, IN ULONG DeviceExtensionSize, IN PUNICODE_STRING DeviceName, IN DEVICE_TYPE DeviceType, IN ULONG DeviceCharacteristics, IN BOOLEAN Exclusive, OUT PDEVICE_OBJECT *DeviceObject)
Definition: device.c:1031
IoDeleteDevice
VOID NTAPI IoDeleteDevice(IN PDEVICE_OBJECT DeviceObject)
Definition: device.c:1251
FILE_DEVICE_UNKNOWN
#define FILE_DEVICE_UNKNOWN
Definition: winioctl.h:140
_BUSMASTER_CONTROLLER_INFORMATION::ChanInitOk
UCHAR ChanInitOk
Definition: bm_devs_decl.h:94
_BUSMASTER_CONTROLLER_INFORMATION::PciIdeDevObj
PDEVICE_OBJECT PciIdeDevObj
Definition: bm_devs_decl.h:98
_BUSMASTER_CONTROLLER_INFORMATION::busNumber
ULONG busNumber
Definition: bm_devs_decl.h:88
_CM_FULL_RESOURCE_DESCRIPTOR::PartialResourceList
CM_PARTIAL_RESOURCE_LIST PartialResourceList
Definition: hwresource.cpp:160
_CM_FULL_RESOURCE_DESCRIPTOR::InterfaceType
INTERFACE_TYPE InterfaceType
Definition: hwresource.cpp:158
_CM_FULL_RESOURCE_DESCRIPTOR::BusNumber
ULONG BusNumber
Definition: hwresource.cpp:159
_CM_PARTIAL_RESOURCE_LIST::Count
ULONG Count
Definition: hwresource.cpp:118
_CM_RESOURCE_LIST
Definition: hwresource.cpp:163
_CM_RESOURCE_LIST::List
CM_FULL_RESOURCE_DESCRIPTOR List[1]
Definition: hwresource.cpp:165
_CM_RESOURCE_LIST::Count
ULONG Count
Definition: hwresource.cpp:164
_UNICODE_STRING
Definition: env_spec_w32.h:368
STATUS_INSUFFICIENT_RESOURCES
#define STATUS_INSUFFICIENT_RESOURCES
Definition: udferr_usr.h:158

Referenced by DriverEntry().

◆ UniataConnectIntr2()

NTSTATUS NTAPI UniataConnectIntr2 ( IN PVOID  HwDeviceExtension)

ForceSimplex

Definition at line 2050 of file id_probe.cpp.

2053{
2054 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
2055 ULONG i = deviceExtension->DevIndex;
2056 NTSTATUS status;
2057 PISR2_DEVICE_EXTENSION Isr2DevExt;
2058 WCHAR devname_str[33];
2059 UNICODE_STRING devname;
2060
2061 KdPrint2((PRINT_PREFIX "Init ISR:\n"));
2062
2063 /*
2064 We MUST register 2nd ISR for multichannel controllers even for UP systems.
2065 This is needed for cases when
2066 multichannel controller generate interrupt while we are still in its ISR for
2067 other channle's interrupt. New interrupt must be detected and queued for
2068 further processing. If we do not do this, system will not route this
2069 interrupt to main ISR (since it is busy) and we shall get to infinite loop
2070 looking for interrupt handler.
2071 */
2072
2073 if(!deviceExtension->MasterDev && (deviceExtension->NumberChannels > 1) && // do not touch MasterDev
2074 !deviceExtension->simplexOnly && /* // this is unnecessary on simplex controllers
2075 !BMList[i].Isr2DevObj*/ // handle re-init under w2k+
2077 /*(CPU_num > 1) && // unnecessary for UP systems*/
2078 TRUE) {
2079 // Ok, continue...
2080 KdPrint2((PRINT_PREFIX "Multichannel native mode, go...\n"));
2081#ifndef UNIATA_USE_XXableInterrupts
2082 // If we raise IRQL to TIMER value, other interrupt cannot occure on the same CPU
2083/* if(KeNumberProcessors < 2) {
2084 KdPrint2((PRINT_PREFIX "Unnecessary (?), UP machine\n"));
2085 //return STATUS_SUCCESS;
2086 }*/
2087#endif //UNIATA_USE_XXableInterrupts
2088 } else {
2089 KdPrint2((PRINT_PREFIX "Unnecessary\n"));
2090 return STATUS_SUCCESS;
2091 }
2092
2093 if(BMList[i].Isr2DevObj) {
2094 KdPrint2((PRINT_PREFIX "Already initialized [%d] %#x\n", i, BMList[i].Isr2DevObj));
2095 return STATUS_SUCCESS;
2096 }
2097
2098 KdPrint2((PRINT_PREFIX "Create DO\n"));
2099
2100 devname.Length =
2101 _snwprintf(devname_str, sizeof(devname_str)/sizeof(WCHAR)-1,
2102 L"\\Device\\uniata%d_2ch", i);
2103 devname_str[devname.Length] = 0;
2104 devname.Length *= sizeof(WCHAR);
2105 devname.MaximumLength = devname.Length;
2106 devname.Buffer = devname_str;
2107
2108 KdPrint2((PRINT_PREFIX "DO name: len(%d, %d), %S\n", devname.Length, devname.MaximumLength, devname.Buffer));
2109
2110 status = IoCreateDevice(SavedDriverObject, sizeof(ISR2_DEVICE_EXTENSION),
2111 /*NULL*/ &devname, FILE_DEVICE_UNKNOWN,
2112 0, FALSE, &(BMList[i].Isr2DevObj));
2113
2114 if(!NT_SUCCESS(status)) {
2115 KdPrint2((PRINT_PREFIX "IoCreateDevice failed %#x\n", status));
2116 return status;
2117 }
2118
2119 KdPrint2((PRINT_PREFIX "HalGetInterruptVector\n"));
2120 KdPrint2((PRINT_PREFIX " OrigAdapterInterfaceType=%d\n", deviceExtension->OrigAdapterInterfaceType));
2121 KdPrint2((PRINT_PREFIX " SystemIoBusNumber=%d\n", deviceExtension->SystemIoBusNumber));
2122 KdPrint2((PRINT_PREFIX " BusInterruptLevel=%d\n", deviceExtension->BusInterruptLevel));
2123 KdPrint2((PRINT_PREFIX " BusInterruptVector=%d\n", deviceExtension->BusInterruptVector));
2124 BMList[i].Isr2Vector = HalGetInterruptVector(
2125 deviceExtension->OrigAdapterInterfaceType,
2126 deviceExtension->SystemIoBusNumber,
2127 deviceExtension->BusInterruptLevel,
2128 deviceExtension->BusInterruptVector,
2129 &(BMList[i].Isr2Irql),
2130 &(BMList[i].Isr2Affinity));
2131
2132 Isr2DevExt = (PISR2_DEVICE_EXTENSION)(BMList[i].Isr2DevObj->DeviceExtension);
2133 Isr2DevExt->HwDeviceExtension = deviceExtension;
2134 Isr2DevExt->DevIndex = i;
2135
2136 KdPrint2((PRINT_PREFIX "isr2_de %#x\n", Isr2DevExt));
2137 KdPrint2((PRINT_PREFIX "isr2_vector %#x\n", BMList[i].Isr2Vector));
2138 KdPrint2((PRINT_PREFIX "isr2_irql %#x\n", BMList[i].Isr2Irql));
2139 KdPrint2((PRINT_PREFIX "isr2_affinity %#x\n", BMList[i].Isr2Affinity));
2140
2141// deviceExtension->QueueNewIrql = BMList[i].Isr2Irql;
2142
2143 KdPrint2((PRINT_PREFIX "IoConnectInterrupt\n"));
2144 status = IoConnectInterrupt(
2145 &(BMList[i].Isr2InterruptObject),
2146 AtapiInterrupt2,
2147 Isr2DevExt,
2148 NULL,
2149 BMList[i].Isr2Vector,
2150 BMList[i].Isr2Irql,
2151 BMList[i].Isr2Irql,
2152 (KINTERRUPT_MODE)(deviceExtension->InterruptMode),
2153 TRUE,
2154 BMList[i].Isr2Affinity,
2155 FALSE);
2156
2157 if(!NT_SUCCESS(status)) {
2158 KdPrint2((PRINT_PREFIX "IoConnectInterrupt failed\n"));
2159 IoDeleteDevice(BMList[i].Isr2DevObj);
2160 BMList[i].Isr2DevObj = NULL;
2161 BMList[i].Isr2InterruptObject = NULL;
2162 return status;
2163 }
2164
2165 //deviceExtension->Isr2DevObj = BMList[i].Isr2DevObj;
2166
2167 return status;
2168} // end UniataConnectIntr2()
AtapiInterrupt2
BOOLEAN NTAPI AtapiInterrupt2(IN PKINTERRUPT Interrupt, IN PVOID HwDeviceExtension)
Definition: id_ata.cpp:4192
HalGetInterruptVector
NTHALAPI ULONG NTAPI HalGetInterruptVector(INTERFACE_TYPE, ULONG, ULONG, ULONG, PKIRQL, PKAFFINITY)
_snwprintf
int _snwprintf(wchar_t *buffer, size_t count, const wchar_t *format,...)
IoConnectInterrupt
NTSTATUS NTAPI IoConnectInterrupt(OUT PKINTERRUPT *InterruptObject, IN PKSERVICE_ROUTINE ServiceRoutine, IN PVOID ServiceContext, IN PKSPIN_LOCK SpinLock, IN ULONG Vector, IN KIRQL Irql, IN KIRQL SynchronizeIrql, IN KINTERRUPT_MODE InterruptMode, IN BOOLEAN ShareVector, IN KAFFINITY ProcessorEnableMask, IN BOOLEAN FloatingSave)
Definition: irq.c:23
KINTERRUPT_MODE
enum _KINTERRUPT_MODE KINTERRUPT_MODE
_BUSMASTER_CONTROLLER_INFORMATION::Isr2Affinity
KAFFINITY Isr2Affinity
Definition: bm_devs_decl.h:101
_BUSMASTER_CONTROLLER_INFORMATION::Isr2InterruptObject
PKINTERRUPT Isr2InterruptObject
Definition: bm_devs_decl.h:103
_BUSMASTER_CONTROLLER_INFORMATION::Isr2Vector
ULONG Isr2Vector
Definition: bm_devs_decl.h:102
_BUSMASTER_CONTROLLER_INFORMATION::Isr2Irql
KIRQL Isr2Irql
Definition: bm_devs_decl.h:100
_BUSMASTER_CONTROLLER_INFORMATION::Isr2DevObj
PDEVICE_OBJECT Isr2DevObj
Definition: bm_devs_decl.h:97
_HW_DEVICE_EXTENSION::BusInterruptVector
ULONG BusInterruptVector
Definition: bsmaster.h:1244
_HW_DEVICE_EXTENSION::BusInterruptLevel
ULONG BusInterruptLevel
Definition: bsmaster.h:1242
_HW_DEVICE_EXTENSION::InterruptMode
ULONG InterruptMode
Definition: atapi.c:47
_ISR2_DEVICE_EXTENSION::DevIndex
ULONG DevIndex
Definition: bsmaster.h:1352
_UNICODE_STRING::Length
USHORT Length
Definition: env_spec_w32.h:369
_UNICODE_STRING::MaximumLength
USHORT MaximumLength
Definition: env_spec_w32.h:370
_UNICODE_STRING::Buffer
PWSTR Buffer
Definition: env_spec_w32.h:371

Referenced by AtapiAdapterControl().

◆ UniataDisconnectIntr2()

NTSTATUS NTAPI UniataDisconnectIntr2 ( IN PVOID  HwDeviceExtension)

Definition at line 2172 of file id_probe.cpp.

2175{
2176 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
2177 ULONG i = deviceExtension->DevIndex;
2178// NTSTATUS status;
2179
2180 KdPrint2((PRINT_PREFIX "Deinit ISR:\n"));
2181
2182 if(!BMList[i].Isr2DevObj) {
2183 KdPrint2((PRINT_PREFIX "Already uninitialized %#x\n"));
2184 return STATUS_SUCCESS;
2185 }
2186
2187 IoDisconnectInterrupt(BMList[i].Isr2InterruptObject);
2188
2189 BMList[i].Isr2InterruptObject = NULL;
2190
2191 IoDeleteDevice(BMList[i].Isr2DevObj);
2192
2193 BMList[i].Isr2DevObj = NULL;
2194 //deviceExtension->Isr2DevObj = NULL;
2195
2196 return STATUS_SUCCESS;
2197} // end UniataDisconnectIntr2()
IoDisconnectInterrupt
VOID NTAPI IoDisconnectInterrupt(PKINTERRUPT InterruptObject)
Definition: irq.c:142

Referenced by AtapiAdapterControl().

◆ UniataEnableIoPCI()

USHORT NTAPI UniataEnableIoPCI ( IN ULONG  busNumber,
IN ULONG  slotNumber,
IN OUT PPCI_COMMON_CONFIG  pciData 
)

Definition at line 95 of file id_probe.cpp.

100{
101 ULONG i;
102 ULONG busDataRead;
103 USHORT CmdOrig;
104
105 // Enable Busmastering, IO-space and Mem-space
106 // Note: write to CONFIG *may* cause controller to interrupt (not handled yet)
107 // even if no bits are updated. Was observed on ICH7
108 KdPrint2((PRINT_PREFIX "Enabling Mem/Io spaces and busmastering...\n"));
109 KdPrint2((PRINT_PREFIX "Initial pciData.Command = %#x\n", pciData->Command));
110 for(i=0; i<3; i++) {
111 CmdOrig = pciData->Command;
112 switch(i) {
113 case 0:
114 KdPrint2((PRINT_PREFIX "PCI_ENABLE_IO_SPACE\n"));
115 pciData->Command |= PCI_ENABLE_IO_SPACE;
116 break;
117 case 1:
118 KdPrint2((PRINT_PREFIX "PCI_ENABLE_MEMORY_SPACE\n"));
119 pciData->Command |= PCI_ENABLE_MEMORY_SPACE;
120 break;
121 case 2:
122 KdPrint2((PRINT_PREFIX "PCI_ENABLE_BUS_MASTER\n"));
123 pciData->Command |= PCI_ENABLE_BUS_MASTER;
124 break;
125 }
126 if(CmdOrig == pciData->Command) {
127 continue;
128 }
129 HalSetBusDataByOffset( PCIConfiguration, busNumber, slotNumber,
130 &(pciData->Command),
131 offsetof(PCI_COMMON_CONFIG, Command),
132 sizeof(pciData->Command));
133
134 // reread config space
135 busDataRead = HalGetBusData(PCIConfiguration, busNumber, slotNumber,
136 pciData, PCI_COMMON_HDR_LENGTH);
137 if(busDataRead < PCI_COMMON_HDR_LENGTH) {
138 KdPrint2((PRINT_PREFIX "HalGetBusData() failed %#x\n", busDataRead));
139 break;
140 }
141 KdPrint2((PRINT_PREFIX "New pciData.Command = %#x\n", pciData->Command));
142 }
143 KdPrint2((PRINT_PREFIX "InterruptLine = %#x\n", pciData->u.type0.InterruptLine));
144 KdPrint2((PRINT_PREFIX "Final pciData.Command = %#x\n", pciData->Command));
145 return pciData->Command;
146} // end UniataEnableIoPCI()
HalSetBusDataByOffset
ULONG NTAPI HalSetBusDataByOffset(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: bus.c:123
PCI_ENABLE_IO_SPACE
#define PCI_ENABLE_IO_SPACE
Definition: iotypes.h:3616
PCI_ENABLE_MEMORY_SPACE
#define PCI_ENABLE_MEMORY_SPACE
Definition: iotypes.h:3617

Referenced by AtapiChipInit(), UniataEnumBusMasterController__(), and UniataFindBusMasterController().

◆ UniataEnumBusMasterController()

VOID NTAPI UniataEnumBusMasterController ( IN PVOID  DriverObject,
PVOID  Argument2 
)

Definition at line 245 of file id_probe.cpp.

249{
250 UniataEnumBusMasterController__();
251
252} // end UniataEnumBusMasterController()
UniataEnumBusMasterController__
ULONG NTAPI UniataEnumBusMasterController__()
Definition: id_probe.cpp:299

Referenced by DriverEntry().

◆ UniataFindBusMasterController()

ULONG NTAPI UniataFindBusMasterController ( IN PVOID  HwDeviceExtension,
IN PVOID  Context,
IN PVOID  BusInformation,
IN PCHAR  ArgumentString,
IN OUT PPORT_CONFIGURATION_INFORMATION  ConfigInfo,
OUT PBOOLEAN  Again 
)

Definition at line 988 of file id_probe.cpp.

996{
997 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
998 PHW_CHANNEL chan = NULL;
999#ifndef UNIATA_CORE
1000 // this buffer must be global for UNIATA_CORE build
1001 PCI_COMMON_CONFIG pciData;
1002#endif //UNIATA_CORE
1003 ULONG slotNumber;
1004 ULONG busDataRead;
1005 ULONG SystemIoBusNumber;
1006/*
1007 UCHAR vendorString[5];
1008 UCHAR deviceString[5];
1009
1010 PUCHAR vendorStrPtr;
1011 PUCHAR deviceStrPtr;
1012*/
1013 UCHAR BaseClass;
1014 UCHAR SubClass;
1015 ULONG VendorID;
1016 ULONG DeviceID;
1017 ULONG RevID;
1018 ULONG dev_id;
1019 PCI_SLOT_NUMBER slotData;
1020
1021 ULONG i;
1022 ULONG channel;
1023 ULONG c = 0;
1024 PUCHAR ioSpace;
1025 UCHAR statusByte;
1026 ULONG bm_offset;
1027
1028// UCHAR tmp8;
1029// ULONG irq;
1030
1031 BOOLEAN found = FALSE;
1032 BOOLEAN MasterDev;
1033 BOOLEAN simplexOnly = FALSE;
1034#ifndef UNIATA_CORE
1035#ifdef UNIATA_INIT_ON_PROBE
1036 BOOLEAN skip_find_dev = FALSE;
1037#endif
1038#endif
1039 BOOLEAN AltInit = FALSE;
1040
1041 SCSI_PHYSICAL_ADDRESS IoBasePort1;
1042 SCSI_PHYSICAL_ADDRESS IoBasePort2;
1043
1044 PIDE_BUSMASTER_REGISTERS BaseIoAddressBM_0 = NULL;
1045 PIDE_REGISTERS_1 BaseIoAddress1[IDE_MAX_CHAN];
1046 PIDE_REGISTERS_2 BaseIoAddress2[IDE_MAX_CHAN];
1047
1048 RtlZeroMemory(&BaseIoAddress1, sizeof(BaseIoAddress1));
1049 RtlZeroMemory(&BaseIoAddress2, sizeof(BaseIoAddress2));
1050
1051 NTSTATUS status;
1052 PPORT_CONFIGURATION_INFORMATION_COMMON _ConfigInfo =
1053 (PPORT_CONFIGURATION_INFORMATION_COMMON)ConfigInfo;
1054
1055 if(!WinVer_WDM_Model) {
1056 *Again = FALSE;
1057 } else {
1058 *Again = TRUE;
1059 }
1060
1061 KdPrint2((PRINT_PREFIX "UniataFindBusMasterController: Context=%x, BMListLen=%d\n", Context, BMListLen));
1062
1063 KdPrint2((PRINT_PREFIX "ConfigInfo->Length %x\n", ConfigInfo->Length));
1064
1065 if(ForceSimplex) {
1066 KdPrint2((PRINT_PREFIX "ForceSimplex (1)\n"));
1067 simplexOnly = TRUE;
1068 }
1069
1070 if(ConfigInfo->AdapterInterfaceType == Isa) {
1071 KdPrint2((PRINT_PREFIX "AdapterInterfaceType: Isa\n"));
1072 }
1073 if(InDriverEntry) {
1074 i = PtrToUlong(Context);
1075 if(i & 0x80000000) {
1076 AltInit = TRUE;
1077 }
1078 i &= ~0x80000000;
1079 channel = BMList[i].channel;
1080 } else {
1081 channel = 0;
1082 for(i=0; i<BMListLen; i++) {
1083 if(BMList[i].slotNumber == ConfigInfo->SlotNumber &&
1084 BMList[i].busNumber == ConfigInfo->SystemIoBusNumber) {
1085 break;
1086 }
1087 }
1088 if(i >= BMListLen) {
1089 KdPrint2((PRINT_PREFIX "unexpected device arrival\n"));
1090 i = PtrToUlong(Context);
1091 if(FirstMasterOk) {
1092 channel = 1;
1093 }
1094 i &= ~0x80000000;
1095 if(i >= BMListLen) {
1096 KdPrint2((PRINT_PREFIX " => SP_RETURN_NOT_FOUND\n"));
1097 goto exit_notfound;
1098 }
1099 }
1100 BMList[i].channel = (UCHAR)channel;
1101 }
1102
1103 bm_offset = channel ? ATA_BM_OFFSET1 : 0;
1104
1105 KdPrint2((PRINT_PREFIX "bm_offset %x, channel %x \n", bm_offset, channel));
1106
1107 if (!deviceExtension) {
1108 KdPrint2((PRINT_PREFIX "!deviceExtension => SP_RETURN_ERROR\n"));
1109 return SP_RETURN_ERROR;
1110 }
1111 RtlZeroMemory(deviceExtension, sizeof(HW_DEVICE_EXTENSION));
1112/*
1113 vendorStrPtr = vendorString;
1114 deviceStrPtr = deviceString;
1115*/
1116 slotNumber = BMList[i].slotNumber;
1117 SystemIoBusNumber = BMList[i].busNumber;
1118
1119
1120 KdPrint2((PRINT_PREFIX "AdapterInterfaceType=%#x\n",ConfigInfo->AdapterInterfaceType));
1121 KdPrint2((PRINT_PREFIX "IoBusNumber=%#x\n",ConfigInfo->SystemIoBusNumber));
1122 KdPrint2((PRINT_PREFIX "slotNumber=%#x\n",slotNumber));
1123
1124 // this buffer must be global and already filled for UNIATA_CORE build
1125 busDataRead = HalGetBusData(
1126 //busDataRead = ScsiPortGetBusData(HwDeviceExtension,
1127 PCIConfiguration,
1128 SystemIoBusNumber,
1129 slotNumber,
1130 &pciData,
1131 PCI_COMMON_HDR_LENGTH);
1132
1133#ifndef UNIATA_CORE
1134 if (busDataRead < (ULONG)PCI_COMMON_HDR_LENGTH) {
1135 KdPrint2((PRINT_PREFIX "busDataRead < PCI_COMMON_HDR_LENGTH => SP_RETURN_ERROR\n"));
1136 goto exit_error;
1137 }
1138
1139 KdPrint2((PRINT_PREFIX "busDataRead\n"));
1140 if (pciData.VendorID == PCI_INVALID_VENDORID) {
1141 KdPrint2((PRINT_PREFIX "PCI_INVALID_VENDORID\n"));
1142 goto exit_error;
1143 }
1144#endif //UNIATA_CORE
1145
1146 VendorID = pciData.VendorID;
1147 DeviceID = pciData.DeviceID;
1148 BaseClass = pciData.BaseClass;
1149 SubClass = pciData.SubClass;
1150 RevID = pciData.RevisionID;
1151 dev_id = VendorID | (DeviceID << 16);
1152 slotData.u.AsULONG = slotNumber;
1153 KdPrint2((PRINT_PREFIX "DevId = %8.8X Class = %4.4X/%4.4X\n", dev_id, BaseClass, SubClass ));
1154
1155 deviceExtension->slotNumber = slotNumber;
1156 deviceExtension->SystemIoBusNumber = SystemIoBusNumber;
1157 deviceExtension->DevID = dev_id;
1158 deviceExtension->RevID = RevID;
1159 deviceExtension->NumberChannels = IDE_DEFAULT_MAX_CHAN; // default
1160 deviceExtension->NumberLuns = IDE_MAX_LUN_PER_CHAN; // default
1161 deviceExtension->DevIndex = i;
1162
1163 _snprintf(deviceExtension->Signature, sizeof(deviceExtension->Signature),
1164 "UATA%8.8x/%1.1x@%8.8x", dev_id, channel, slotNumber);
1165
1166 if(BaseClass != PCI_DEV_CLASS_STORAGE) {
1167 KdPrint2((PRINT_PREFIX "BaseClass != PCI_DEV_CLASS_STORAGE => SP_RETURN_NOT_FOUND\n"));
1168 goto exit_notfound;
1169 }
1170
1171 KdPrint2((PRINT_PREFIX "Storage Class\n"));
1172
1173 // look for known chipsets
1174 if(VendorID != BMList[i].nVendorId ||
1175 DeviceID != BMList[i].nDeviceId) {
1176 KdPrint2((PRINT_PREFIX "device not suitable\n"));
1177 goto exit_notfound;
1178 }
1179
1180 found = UniataCheckPCISubclass(BMList[i].Known, BMList[i].RaidFlags, SubClass);
1181 if(!found) {
1182 KdPrint2((PRINT_PREFIX "Subclass not supported\n"));
1183 goto exit_notfound;
1184 }
1185
1186 ConfigInfo->AlignmentMask = 0x00000003;
1187
1188 MasterDev = IsMasterDev(&pciData);
1189
1190 if(MasterDev) {
1191 KdPrint2((PRINT_PREFIX "MasterDev (1)\n"));
1192 deviceExtension->MasterDev = TRUE;
1193 KdPrint2((PRINT_PREFIX "Check exclude\n"));
1194 if(AtapiRegCheckDevValue(deviceExtension, channel, DEVNUM_NOT_SPECIFIED, L"Exclude", 0)) {
1195 KdPrint2((PRINT_PREFIX "Device excluded\n"));
1196 goto exit_notfound;
1197 }
1198 }
1199
1200 status = UniataChipDetect(HwDeviceExtension, &pciData, i, ConfigInfo, &simplexOnly);
1201 switch(status) {
1202 case STATUS_SUCCESS:
1203 found = TRUE;
1204 break;
1205 case STATUS_NOT_FOUND:
1206 found = FALSE;
1207 break;
1208 default:
1209 KdPrint2((PRINT_PREFIX "FAILED => SP_RETURN_ERROR\n"));
1210 goto exit_error;
1211 }
1212 KdPrint2((PRINT_PREFIX "ForceSimplex = %d\n", simplexOnly));
1213 KdPrint2((PRINT_PREFIX "HwFlags = %x\n (0)", deviceExtension->HwFlags));
1214 switch(dev_id) {
1215 /* additional checks for some supported chipsets */
1216 case 0xc6931080:
1217 if (SubClass != PCI_DEV_SUBCLASS_IDE) {
1218 KdPrint2((PRINT_PREFIX "0xc6931080, SubClass != PCI_DEV_SUBCLASS_IDE => found = FALSE\n"));
1219 found = FALSE;
1220 } else {
1221 found = FALSE;
1222 }
1223 break;
1224
1225 /* unknown chipsets, try generic DMA if it seems possible */
1226 default:
1227 if (found)
1228 break;
1229 KdPrint2((PRINT_PREFIX "Default device\n"));
1230 if(Ata_is_supported_dev(&pciData)) {
1231 KdPrint2((PRINT_PREFIX "Ata_is_supported_dev\n"));
1232 found = TRUE;
1233 } else
1234 if(deviceExtension->HwFlags & UNIATA_AHCI) {
1235 KdPrint2((PRINT_PREFIX "AHCI candidate\n"));
1236 found = TRUE;
1237 } else {
1238 KdPrint2((PRINT_PREFIX "!Ata_is_supported_dev => found = FALSE\n"));
1239 found = FALSE;
1240 }
1241 deviceExtension->UnknownDev = TRUE;
1242 break;
1243 }
1244
1245 KdPrint2((PRINT_PREFIX "HwFlags = %x\n (1)", deviceExtension->HwFlags));
1246 if(!found) {
1247 KdPrint2((PRINT_PREFIX "!found => SP_RETURN_NOT_FOUND\n"));
1248 goto exit_notfound;
1249 }
1250
1251 KdPrint2((PRINT_PREFIX "HwFlags = %x\n (2)", deviceExtension->HwFlags));
1252 KdPrint2((PRINT_PREFIX "found suitable device\n"));
1253
1254 /***********************************************************/
1255 /***********************************************************/
1256 /***********************************************************/
1257
1258 deviceExtension->UseDpc = TRUE;
1259#ifndef UNIATA_CORE
1260 if (g_Dump) {
1261 deviceExtension->DriverMustPoll = TRUE;
1262 deviceExtension->UseDpc = FALSE;
1263 deviceExtension->simplexOnly = TRUE;
1264 deviceExtension->HwFlags |= UNIATA_NO_DPC;
1265 }
1266#endif //UNIATA_CORE
1267 KdPrint2((PRINT_PREFIX "HwFlags = %x\n (3)", deviceExtension->HwFlags));
1268 if(deviceExtension->HwFlags & UNIATA_NO_DPC) {
1269 /* CMD 649, ROSB SWK33, ICH4 */
1270 KdPrint2((PRINT_PREFIX "UniataFindBusMasterController: UNIATA_NO_DPC (0)\n"));
1271 deviceExtension->UseDpc = FALSE;
1272 }
1273
1274 if(MasterDev) {
1275 if((WinVer_Id() <= WinVer_NT) && AltInit && FirstMasterOk) {
1276 // this is the 2nd attempt to init this controller by OUR driver
1277 KdPrint2((PRINT_PREFIX "Skip primary/secondary claiming checks\n"));
1278 } else {
1279 if((channel==0) && ConfigInfo->AtdiskPrimaryClaimed) {
1280 KdPrint2((PRINT_PREFIX "Error: Primary channel already claimed by another driver\n"));
1281 goto exit_notfound;
1282 }
1283 if((channel==1) && ConfigInfo->AtdiskSecondaryClaimed) {
1284 KdPrint2((PRINT_PREFIX "Error: Secondary channel already claimed by another driver\n"));
1285 goto exit_notfound;
1286 }
1287 }
1288 }
1289 if(deviceExtension->HwFlags & UNIATA_AHCI) {
1290 KdPrint2((PRINT_PREFIX " AHCI registers layout\n"));
1291 } else
1292 if(deviceExtension->AltRegMap) {
1293 KdPrint2((PRINT_PREFIX " Non-standard registers layout\n"));
1294 if(deviceExtension->HwFlags & UNIATA_SATA) {
1295 KdPrint2((PRINT_PREFIX "UNIATA_SATA -> IsBusMaster == TRUE\n"));
1296 if(!deviceExtension->BusMaster) {
1297 deviceExtension->BusMaster = DMA_MODE_BM;
1298 }
1299 }
1300 } else {
1301 deviceExtension->BusMaster = DMA_MODE_NONE;
1302
1303 if(WinVer_WDM_Model && !deviceExtension->UnknownDev) {
1304 UniataEnableIoPCI(ConfigInfo->SystemIoBusNumber, slotData.u.AsULONG, &pciData);
1305 }
1306 // validate Mem/Io ranges
1307 //no_ranges = TRUE;
1308 {
1309 ULONG j;
1310 for(j=0; j<PCI_TYPE0_ADDRESSES; j++) {
1311 if(pciData.u.type0.BaseAddresses[j] & ~0x7) {
1312 //no_ranges = FALSE;
1313 //break;
1314 KdPrint2((PRINT_PREFIX "Range %d = %#x\n", j, pciData.u.type0.BaseAddresses[j]));
1315 }
1316 }
1317 }
1318
1319 if(IsBusMaster(&pciData)) {
1320
1321 KdPrint2((PRINT_PREFIX "IsBusMaster == TRUE\n"));
1322 BaseIoAddressBM_0 = (PIDE_BUSMASTER_REGISTERS)
1323 (AtapiGetIoRange(HwDeviceExtension, ConfigInfo, &pciData, SystemIoBusNumber,
1324 4, bm_offset, MasterDev ? 0x08 : 0x10/*ATA_BMIOSIZE*/)/* - bm_offset*/); //range id
1325 if(BaseIoAddressBM_0) {
1326 UniataInitMapBM(deviceExtension,
1327 BaseIoAddressBM_0,
1328 (*ConfigInfo->AccessRanges)[4].RangeInMemory ? TRUE : FALSE);
1329 deviceExtension->BusMaster = DMA_MODE_BM;
1330 deviceExtension->BaseIoAddressBM_0.Addr = (ULONGIO_PTR)BaseIoAddressBM_0;
1331 if((*ConfigInfo->AccessRanges)[4].RangeInMemory) {
1332 deviceExtension->BaseIoAddressBM_0.MemIo = TRUE;
1333 }
1334 }
1335 KdPrint2((PRINT_PREFIX " BusMasterAddress (base): %#x\n", BaseIoAddressBM_0));
1336 }
1337
1338 if(!deviceExtension->BusMaster) {
1339 KdPrint2((PRINT_PREFIX " !BusMasterAddress -> PIO4\n"));
1340 deviceExtension->MaxTransferMode = ATA_PIO4;
1341 }
1342
1343 if(deviceExtension->BusMaster && !MasterDev) {
1344 KdPrint2((PRINT_PREFIX "IsBusMaster == TRUE && !MasterDev\n"));
1345 statusByte = AtapiReadPort1(&(deviceExtension->chan[0]), IDX_BM_Status);
1346 KdPrint2((PRINT_PREFIX " BM statusByte = %x\n", statusByte));
1347 if(statusByte == IDE_STATUS_WRONG) {
1348 KdPrint2((PRINT_PREFIX " invalid port ?\n"));
1349 deviceExtension->BusMaster = DMA_MODE_NONE;
1350/*
1351 if(BaseIoAddressBM_0) {
1352 ScsiPortFreeDeviceBase(HwDeviceExtension,
1353 BaseIoAddressBM_0);
1354 BaseIoAddressBM_0 = NULL;
1355 }
1356*/
1357 } else
1358 if(statusByte & BM_STATUS_SIMPLEX_ONLY) {
1359 KdPrint2((PRINT_PREFIX " BM_STATUS => simplexOnly\n"));
1360 simplexOnly = TRUE;
1361 }
1362 }
1363 }
1364
1365 /*
1366 * the Cypress chip is a mess, it contains two ATA functions, but
1367 * both channels are visible on the first one.
1368 * simply ignore the second function for now, as the right
1369 * solution (ignoring the second channel on the first function)
1370 * doesn't work with the crappy ATA interrupt setup on the alpha.
1371 */
1372 if (dev_id == 0xc6931080 && slotData.u.bits.FunctionNumber > 1) {
1373 KdPrint2((PRINT_PREFIX "dev_id == 0xc6931080 && FunctionNumber > 1 => exit_findbm\n"));
1374 goto exit_findbm;
1375 }
1376
1377 /* do extra chipset specific setups */
1378 AtapiReadChipConfig(HwDeviceExtension, i, CHAN_NOT_SPECIFIED);
1379 AtapiChipInit(HwDeviceExtension, i, CHAN_NOT_SPECIFIED_CHECK_CABLE);
1380
1381 simplexOnly |= deviceExtension->simplexOnly;
1382 deviceExtension->simplexOnly |= simplexOnly;
1383
1384 KdPrint2((PRINT_PREFIX "simplexOnly = %d (2)", simplexOnly));
1385
1386 //TODO: fix hang with UseDpc=TRUE in Simplex mode
1387 //deviceExtension->UseDpc = TRUE;
1388 if(simplexOnly) {
1389 KdPrint2((PRINT_PREFIX "simplexOnly => UseDpc = FALSE\n"));
1390 deviceExtension->UseDpc = FALSE;
1391 }
1392
1393 if(simplexOnly && MasterDev) {
1394 if(deviceExtension->NumberChannels < IDE_DEFAULT_MAX_CHAN) {
1395 KdPrint2((PRINT_PREFIX "set NumberChannels = %d\n", IDE_DEFAULT_MAX_CHAN));
1396 deviceExtension->NumberChannels = IDE_DEFAULT_MAX_CHAN;
1397 if(BaseIoAddressBM_0) {
1398 UniataInitMapBM(deviceExtension,
1399 BaseIoAddressBM_0,
1400 (*ConfigInfo->AccessRanges)[4].RangeInMemory ? TRUE : FALSE);
1401 }
1402 }
1403 }
1404 if((channel > 0) &&
1405 (deviceExtension->NumberChannels > 1)) {
1406 KdPrint2((PRINT_PREFIX "Error: channel > 0 && NumberChannels > 1\n"));
1407 goto exit_findbm;
1408 }
1409
1410 // Indicate number of buses.
1411 ConfigInfo->NumberOfBuses = (UCHAR)(deviceExtension->NumberChannels);
1412 if(!ConfigInfo->InitiatorBusId[0]) {
1413 ConfigInfo->InitiatorBusId[0] = (CHAR)(IoGetConfigurationInformation()->ScsiPortCount);
1414 KdPrint2((PRINT_PREFIX "set ConfigInfo->InitiatorBusId[0] = %#x\n", ConfigInfo->InitiatorBusId[0]));
1415 }
1416 // Indicate four devices can be attached to the adapter
1417 ConfigInfo->MaximumNumberOfTargets = (UCHAR)(deviceExtension->NumberLuns);
1418
1419 if (MasterDev) {
1420 KdPrint2((PRINT_PREFIX "MasterDev (2)\n"));
1421/*
1422 if((WinVer_Id() > WinVer_NT) ||
1423 (deviceExtension->NumberChannels > 1)) {
1424
1425 KdPrint2((PRINT_PREFIX "2 channels & 2 irq for 1 controller Win 2000+\n"));
1426
1427 if (ConfigInfo->AdapterInterfaceType == MicroChannel) {
1428 ConfigInfo->InterruptMode2 =
1429 ConfigInfo->InterruptMode = LevelSensitive;
1430 } else {
1431 ConfigInfo->InterruptMode2 =
1432 ConfigInfo->InterruptMode = Latched;
1433 }
1434 ConfigInfo->BusInterruptLevel = 14;
1435 ConfigInfo->BusInterruptLevel2 = 15;
1436 } else*/
1437 if(simplexOnly) {
1438
1439 KdPrint2((PRINT_PREFIX "2 channels & 2 irq for 1 controller\n"));
1440
1441 if (ConfigInfo->AdapterInterfaceType == MicroChannel) {
1442 ConfigInfo->InterruptMode2 =
1443 ConfigInfo->InterruptMode = LevelSensitive;
1444 } else {
1445 ConfigInfo->InterruptMode2 =
1446 ConfigInfo->InterruptMode = Latched;
1447 }
1448 ConfigInfo->BusInterruptLevel = 14;
1449 ConfigInfo->BusInterruptLevel2 = 15;
1450 } else {
1451 KdPrint2((PRINT_PREFIX "1 channels & 1 irq for 1 controller\n"));
1452 if (ConfigInfo->AdapterInterfaceType == MicroChannel) {
1453 ConfigInfo->InterruptMode = LevelSensitive;
1454 } else {
1455 ConfigInfo->InterruptMode = Latched;
1456 }
1457 ConfigInfo->BusInterruptLevel = (channel == 0 ? 14 : 15);
1458 }
1459 } else {
1460 KdPrint2((PRINT_PREFIX "!MasterDev\n"));
1461 ConfigInfo->SlotNumber = slotNumber;
1462 ConfigInfo->SystemIoBusNumber = SystemIoBusNumber;
1463 ConfigInfo->InterruptMode = LevelSensitive;
1464
1465 /* primary and secondary channels share the same interrupt */
1466 if(!ConfigInfo->BusInterruptVector ||
1467 (ConfigInfo->BusInterruptVector != pciData.u.type0.InterruptLine)) {
1468 KdPrint2((PRINT_PREFIX "patch irq line = %#x\n", pciData.u.type0.InterruptLine));
1469 ConfigInfo->BusInterruptVector = pciData.u.type0.InterruptLine; // set default value
1470 if(!ConfigInfo->BusInterruptVector) {
1471 KdPrint2((PRINT_PREFIX "patch irq line (2) = 10\n"));
1472 ConfigInfo->BusInterruptVector = 10;
1473 }
1474 }
1475 }
1476 ConfigInfo->MultipleRequestPerLu = TRUE;
1477 ConfigInfo->AutoRequestSense = TRUE;
1478 ConfigInfo->TaggedQueuing = TRUE;
1479
1480 if((WinVer_Id() >= WinVer_NT) ||
1481 (ConfigInfo->Length >= sizeof(_ConfigInfo->comm) + sizeof(_ConfigInfo->nt4))) {
1482 KdPrint2((PRINT_PREFIX "update ConfigInfo->nt4\n"));
1483 _ConfigInfo->nt4.DeviceExtensionSize = sizeof(HW_DEVICE_EXTENSION);
1484 _ConfigInfo->nt4.SpecificLuExtensionSize = sizeof(HW_LU_EXTENSION);
1485 //if(deviceExtension->HwFlags & UNIATA_AHCI) {
1486 _ConfigInfo->nt4.SrbExtensionSize = sizeof(ATA_REQ);
1487 //} else {
1488 // _ConfigInfo->nt4.SrbExtensionSize = FIELD_OFFSET(ATA_REQ, dma_tab) + sizeof(BM_DMA_ENTRY)*ATA_DMA_ENTRIES;
1489 //}
1490 KdPrint2((PRINT_PREFIX "using AtaReq sz %x\n", _ConfigInfo->nt4.SrbExtensionSize));
1491 }
1492 if((WinVer_Id() > WinVer_2k) ||
1493 (ConfigInfo->Length >= sizeof(_ConfigInfo->comm) + sizeof(_ConfigInfo->nt4) + sizeof(_ConfigInfo->w2k))) {
1494 KdPrint2((PRINT_PREFIX "update ConfigInfo->w2k: 64bit %d\n",
1495 deviceExtension->Host64));
1496#ifdef USE_OWN_DMA
1497 // We need not set Dma64BitAddresses since we perform address translation manually.
1498#else
1499 _ConfigInfo->w2k.Dma64BitAddresses = deviceExtension->Host64;
1500#endif //USE_OWN_DMA
1501 _ConfigInfo->w2k.ResetTargetSupported = TRUE;
1502 _ConfigInfo->w2k.MaximumNumberOfLogicalUnits = (UCHAR)deviceExtension->NumberLuns;
1503 }
1504
1505 // Save the Interrupe Mode for later use
1506 deviceExtension->InterruptMode = ConfigInfo->InterruptMode;
1507 deviceExtension->BusInterruptLevel = ConfigInfo->BusInterruptLevel;
1508 deviceExtension->BusInterruptVector = ConfigInfo->BusInterruptVector;
1509 deviceExtension->Channel = channel;
1510 deviceExtension->DevIndex = i;
1511 deviceExtension->OrigAdapterInterfaceType
1512 = ConfigInfo->AdapterInterfaceType;
1513 deviceExtension->AlignmentMask = ConfigInfo->AlignmentMask;
1514 deviceExtension->AdapterInterfaceType = PCIBus;
1515
1516 KdPrint2((PRINT_PREFIX "chan[%d] InterruptMode: %d, Level %d, Level2 %d, Vector %d, Vector2 %d\n",
1517 channel,
1518 ConfigInfo->InterruptMode,
1519 ConfigInfo->BusInterruptLevel,
1520 ConfigInfo->BusInterruptLevel2,
1521 ConfigInfo->BusInterruptVector,
1522 ConfigInfo->BusInterruptVector2
1523 ));
1524
1525 found = FALSE;
1526
1527 if(deviceExtension->BusMaster) {
1528
1529 KdPrint2((PRINT_PREFIX "Reconstruct ConfigInfo\n"));
1530#ifdef USE_OWN_DMA
1531 ConfigInfo->NeedPhysicalAddresses = FALSE;
1532#else
1533 ConfigInfo->NeedPhysicalAddresses = TRUE;
1534#endif //USE_OWN_DMA
1535 if(!MasterDev) {
1536//#ifdef USE_OWN_DMA
1537// KdPrint2((PRINT_PREFIX "!MasterDev, own DMA\n"));
1538//#else
1539 KdPrint2((PRINT_PREFIX "set Dma32BitAddresses\n"));
1540 ConfigInfo->Dma32BitAddresses = TRUE;
1541//#endif //USE_OWN_DMA
1542 }
1543
1544 // thanks to Vitaliy Vorobyov aka deathsoft@yandex.ru for
1545 // better solution:
1546
1547 if(AltInit) {
1548 // I'm sorry, I have to do this
1549 // when Win doesn't
1550
1551 if(ConfigInfo->AdapterInterfaceType == Isa /*&&
1552// InDriverEntry*/) {
1553 KdPrint2((PRINT_PREFIX "AdapterInterfaceType Isa => PCIBus\n"));
1554 ConfigInfo->AdapterInterfaceType = PCIBus;
1555 }
1556 if(ConfigInfo->AdapterInterfaceType == PCIBus /*&&
1557// InDriverEntry*/) {
1558 KdPrint2((PRINT_PREFIX "AdapterInterfaceType PCIBus, update address\n"));
1559 ConfigInfo->SlotNumber = slotNumber;
1560 ConfigInfo->SystemIoBusNumber = SystemIoBusNumber;
1561 }
1562 }
1563
1564#ifndef USE_OWN_DMA
1565 ConfigInfo->Master = TRUE;
1566 ConfigInfo->DmaWidth = Width16Bits;
1567#endif //USE_OWN_DMA
1568 ConfigInfo->ScatterGather = TRUE;
1569 }
1570 ConfigInfo->MapBuffers = TRUE; // Need for PIO and OWN_DMA
1571 ConfigInfo->CachesData = TRUE;
1572
1573 KdPrint2((PRINT_PREFIX "BMList[i].channel %#x, NumberChannels %#x, channel %#x\n",BMList[i].channel, deviceExtension->NumberChannels, channel));
1574
1575 for (; channel < (BMList[i].channel + deviceExtension->NumberChannels); channel++, c++) {
1576
1577 KdPrint2((PRINT_PREFIX "de %#x, Channel %#x\n",deviceExtension, channel));
1578 //PrintNtConsole("de %#x, Channel %#x, nchan %#x\n",deviceExtension, channel, deviceExtension->NumberChannels);
1579 chan = &deviceExtension->chan[c];
1580
1581 KdPrint2((PRINT_PREFIX "chan = %#x\n", chan));
1582 //PrintNtConsole("chan = %#x, c=%#x\n", chan, c);
1583 AtapiSetupLunPtrs(chan, deviceExtension, c);
1584
1585 /* do extra channel-specific setups */
1586 AtapiReadChipConfig(HwDeviceExtension, i, channel);
1587 //AtapiChipInit(HwDeviceExtension, i, channel);
1588 if(deviceExtension->HwFlags & UNIATA_AHCI) {
1589 KdPrint2((PRINT_PREFIX " No more setup for AHCI channel\n"));
1590 } else
1591 if(deviceExtension->AltRegMap) {
1592 KdPrint2((PRINT_PREFIX " Non-standard registers layout\n"));
1593 } else {
1594 // Check if the range specified is not used by another driver
1595 if(MasterDev) {
1596 KdPrint2((PRINT_PREFIX "set AccessRanges\n"));
1597 (*ConfigInfo->AccessRanges)[channel * 2 + 0].RangeStart =
1598 ScsiPortConvertUlongToPhysicalAddress(channel ? IO_WD2 : IO_WD1);
1599 (*ConfigInfo->AccessRanges)[channel * 2 + 0].RangeLength = ATA_IOSIZE;
1600
1601 (*ConfigInfo->AccessRanges)[channel * 2 + 1].RangeStart =
1602 ScsiPortConvertUlongToPhysicalAddress((channel ? IO_WD2 : IO_WD1) + ATA_ALTOFFSET);
1603 (*ConfigInfo->AccessRanges)[channel * 2 + 1].RangeLength = ATA_ALTIOSIZE;
1604 } else
1605 if(AltInit &&
1606 !(*ConfigInfo->AccessRanges)[channel * 2 + 0].RangeStart.QuadPart &&
1607 !(*ConfigInfo->AccessRanges)[channel * 2 + 1].RangeStart.QuadPart) {
1608 KdPrint2((PRINT_PREFIX "cheat ScsiPort, sync real PCI and ConfigInfo IO ranges\n"));
1609 AtapiGetIoRange(HwDeviceExtension, ConfigInfo, &pciData, SystemIoBusNumber,
1610 channel * 2 + 0, 0, ATA_IOSIZE);
1611 AtapiGetIoRange(HwDeviceExtension, ConfigInfo, &pciData, SystemIoBusNumber,
1612 channel * 2 + 1, 0, ATA_ALTIOSIZE);
1613 }
1614
1615 IoBasePort1 = (*ConfigInfo->AccessRanges)[channel * 2 + 0].RangeStart;
1616 IoBasePort2 = (*ConfigInfo->AccessRanges)[channel * 2 + 1].RangeStart;
1617
1618 if(!MasterDev) {
1619 if(!IoBasePort1.QuadPart || !IoBasePort2.QuadPart) {
1620 KdPrint2((PRINT_PREFIX "ScsiPortValidateRange failed (1)\n"));
1621 continue;
1622 }
1623 }
1624
1625 if(!ScsiPortValidateRange(HwDeviceExtension,
1626 PCIBus /*ConfigInfo->AdapterInterfaceType*/,
1627 SystemIoBusNumber /*ConfigInfo->SystemIoBusNumber*/,
1628 IoBasePort1,
1629 ATA_IOSIZE,
1630 TRUE) ) {
1631 KdPrint2((PRINT_PREFIX "ScsiPortValidateRange failed (1)\n"));
1632 continue;
1633 }
1634
1635 if(!ScsiPortValidateRange(HwDeviceExtension,
1636 PCIBus /*ConfigInfo->AdapterInterfaceType*/,
1637 SystemIoBusNumber /*ConfigInfo->SystemIoBusNumber*/,
1638 IoBasePort2,
1639 ATA_ALTIOSIZE,
1640 TRUE) ) {
1641 KdPrint2((PRINT_PREFIX "ScsiPortValidateRange failed (2)\n"));
1642 continue;
1643 }
1644
1645 KdPrint2((PRINT_PREFIX "Getting IO ranges\n"));
1646
1647 // Ok, translate adresses to io-space
1648 if(ScsiPortConvertPhysicalAddressToUlong(IoBasePort2)) {
1649 if(!(MasterDev /* || USE_16_BIT */)) {
1650 KdPrint2((PRINT_PREFIX "!MasterDev mode\n"));
1651 IoBasePort2 = ScsiPortConvertUlongToPhysicalAddress(
1652 ScsiPortConvertPhysicalAddressToUlong(IoBasePort2) + 2);
1653 }
1654 } else {
1655 KdPrint2((PRINT_PREFIX "use relative IoBasePort2\n"));
1656 IoBasePort2 = ScsiPortConvertUlongToPhysicalAddress(
1657 ScsiPortConvertPhysicalAddressToUlong(IoBasePort1) + ATA_PCCARD_ALTOFFSET);
1658 }
1659
1660 // Get the system physical address for this IO range.
1661 ioSpace = (PUCHAR)ScsiPortGetDeviceBase(HwDeviceExtension,
1662 MasterDev ? ConfigInfo->AdapterInterfaceType : PCIBus /*ConfigInfo->AdapterInterfaceType*/,
1663 MasterDev ? ConfigInfo->SystemIoBusNumber : SystemIoBusNumber /*ConfigInfo->SystemIoBusNumber*/,
1664 IoBasePort1,
1665 ATA_IOSIZE,
1666 TRUE);
1667 KdPrint2((PRINT_PREFIX "IO range 1 %#x\n",ioSpace));
1668
1669 // Check if ioSpace accessible.
1670 if (!ioSpace) {
1671 KdPrint2((PRINT_PREFIX "!ioSpace\n"));
1672 continue;
1673 }
1674/*
1675 if(deviceExtension->BusMaster) {
1676 KdPrint2((PRINT_PREFIX "set BusMaster io-range in DO\n"));
1677 // bm_offset already includes (channel ? ATA_BM_OFFSET1 : 0)
1678 deviceExtension->BaseIoAddressBM[c] = (PIDE_BUSMASTER_REGISTERS)
1679 ((ULONG)(deviceExtension->BaseIoAddressBM_0) + bm_offset + (c ? ATA_BM_OFFSET1 : 0));
1680 }
1681*/
1682 //deviceExtension->BaseIoAddress1[c] = (PIDE_REGISTERS_1)(ioSpace);
1683 BaseIoAddress1[c] = (PIDE_REGISTERS_1)(ioSpace);
1684
1685 // Get the system physical address for the second IO range.
1686 ioSpace = (PUCHAR)ScsiPortGetDeviceBase(HwDeviceExtension,
1687 MasterDev ? ConfigInfo->AdapterInterfaceType : PCIBus /*ConfigInfo->AdapterInterfaceType*/,
1688 MasterDev ? ConfigInfo->SystemIoBusNumber : SystemIoBusNumber /*ConfigInfo->SystemIoBusNumber*/,
1689 IoBasePort2,
1690 ATA_ALTIOSIZE,
1691 TRUE);
1692 KdPrint2((PRINT_PREFIX "IO range 2 %#x\n",ioSpace));
1693
1694 BaseIoAddress2[c] = (PIDE_REGISTERS_2)(ioSpace);
1695 if(!ioSpace) {
1696 // Release all allocated resources
1697 KdPrint2((PRINT_PREFIX "!deviceExtension->BaseIoAddress2\n"));
1698 //ioSpace = (PUCHAR)BaseIoAddress1[c];
1699 // goto free_iospace_1;
1700 found = FALSE;
1701 goto exit_findbm;
1702 }
1703 UniataInitMapBase(chan, BaseIoAddress1[c], BaseIoAddress2[c]);
1704 }
1705 //ioSpace = (PUCHAR)(deviceExtension->BaseIoAddress1[c]);
1706
1707 DbgDumpRegTranslation(chan, IDX_IO1);
1708 DbgDumpRegTranslation(chan, IDX_IO2);
1709 DbgDumpRegTranslation(chan, IDX_BM_IO);
1710 DbgDumpRegTranslation(chan, IDX_SATA_IO);
1711
1712 if(!(deviceExtension->HwFlags & UNIATA_AHCI)) {
1713#ifdef _DEBUG
1714 UniataDumpATARegs(chan);
1715#endif
1716
1717#ifndef UNIATA_CORE
1718#ifdef UNIATA_INIT_ON_PROBE
1719// if(deviceExtension->HwFlags & UNIATA_SATA) {
1720//#endif //UNIATA_INIT_ON_PROBE
1721 KdPrint2((PRINT_PREFIX "Check drive 0\n"));
1722 // Check master.
1723 SelectDrive(chan, 0);
1724 AtapiStallExecution(10);
1725 GetBaseStatus(chan, statusByte);
1726 skip_find_dev = FALSE;
1727 if(!(deviceExtension->HwFlags & UNIATA_NO_SLAVE) && (deviceExtension->NumberLuns > 1)) {
1728 if ((statusByte & 0xf8) == 0xf8 ||
1729 (statusByte == 0xa5)) {
1730 // Check slave.
1731 KdPrint2((PRINT_PREFIX "Check drive 1\n"));
1732 SelectDrive(chan, 1);
1733 AtapiStallExecution(1);
1734 GetBaseStatus(chan, statusByte);
1735 if ((statusByte & 0xf8) == 0xf8 ||
1736 (statusByte == 0xa5)) {
1737 // No controller at this base address.
1738 KdPrint2((PRINT_PREFIX "Empty channel\n"));
1739 skip_find_dev = TRUE;
1740 }
1741 }
1742 }
1743
1744 // Search for devices on this controller.
1745 if (!skip_find_dev &&
1746 FindDevices(HwDeviceExtension,
1747 0,
1748 c)) {
1749 KdPrint2((PRINT_PREFIX "Found some devices\n"));
1750 found = TRUE;
1751 } else {
1752 KdPrint2((PRINT_PREFIX "no devices\n"));
1753 /* KeBugCheckEx(0xc000000e,
1754 ScsiPortConvertPhysicalAddressToUlong(IoBasePort1),
1755 ScsiPortConvertPhysicalAddressToUlong(IoBasePort2),
1756 (ULONG)(deviceExtension->BaseIoAddressBM[c]), skip_find_dev);*/
1757 }
1758//#ifdef UNIATA_INIT_ON_PROBE
1759// }
1760#else //UNIATA_INIT_ON_PROBE
1761 KdPrint2((PRINT_PREFIX "clean IDE intr 0\n"));
1762
1763 SelectDrive(chan, 0);
1764 AtapiStallExecution(10);
1765 GetBaseStatus(chan, statusByte);
1766
1767 if(!(deviceExtension->HwFlags & UNIATA_NO_SLAVE) && (deviceExtension->NumberLuns > 1)) {
1768 KdPrint2((PRINT_PREFIX "clean IDE intr 1\n"));
1769
1770 SelectDrive(chan, 1);
1771 AtapiStallExecution(1);
1772 GetBaseStatus(chan, statusByte);
1773
1774 SelectDrive(chan, 0);
1775 }
1776
1777 statusByte = GetDmaStatus(deviceExtension, c);
1778 KdPrint2((PRINT_PREFIX " DMA status %#x\n", statusByte));
1779 if(statusByte & BM_STATUS_INTR) {
1780 // bullshit, we have DMA interrupt, but had never initiate DMA operation
1781 KdPrint2((PRINT_PREFIX " clear unexpected DMA intr\n"));
1782 AtapiDmaDone(deviceExtension, 0, c, NULL);
1783 GetBaseStatus(chan, statusByte);
1784 }
1785
1786#endif //UNIATA_INIT_ON_PROBE
1787 }
1788 found = TRUE;
1789
1790 chan->PrimaryAddress = FALSE;
1791 // Claim primary or secondary ATA IO range.
1792 if (MasterDev) {
1793 KdPrint2((PRINT_PREFIX "claim Compatible controller\n"));
1794 if (channel == 0) {
1795 KdPrint2((PRINT_PREFIX "claim Primary\n"));
1796 AtdiskPrimaryClaimed =
1797 ConfigInfo->AtdiskPrimaryClaimed = TRUE;
1798 chan->PrimaryAddress = TRUE;
1799
1800 FirstMasterOk = TRUE;
1801
1802 } else
1803 if (channel == 1) {
1804 KdPrint2((PRINT_PREFIX "claim Secondary\n"));
1805 AtdiskSecondaryClaimed =
1806 ConfigInfo->AtdiskSecondaryClaimed = TRUE;
1807
1808 FirstMasterOk = TRUE;
1809 }
1810 } else {
1811 if(chan->RegTranslation[IDX_IO1].Addr == IO_WD1 &&
1812 !chan->RegTranslation[IDX_IO1].MemIo) {
1813 KdPrint2((PRINT_PREFIX "claim Primary (PCI over ISA range)\n"));
1814 AtdiskPrimaryClaimed =
1815 ConfigInfo->AtdiskPrimaryClaimed = TRUE;
1816 }
1817 if(chan->RegTranslation[IDX_IO1].Addr == IO_WD2 &&
1818 !chan->RegTranslation[IDX_IO1].MemIo) {
1819 KdPrint2((PRINT_PREFIX "claim Secondary (PCI over ISA range)\n"));
1820 AtdiskSecondaryClaimed =
1821 ConfigInfo->AtdiskSecondaryClaimed = TRUE;
1822 }
1823 }
1824
1825 AtapiDmaAlloc(HwDeviceExtension, ConfigInfo, c);
1826#else //UNIATA_CORE
1827 }
1828 found = TRUE;
1829#endif //UNIATA_CORE
1830 } // end for(channel)
1831
1832exit_findbm:
1833
1834#ifndef UNIATA_CORE
1835 if(!found) {
1836 KdPrint2((PRINT_PREFIX "exit: !found\n"));
1837 if(BaseIoAddress1[0])
1838 ScsiPortFreeDeviceBase(HwDeviceExtension,
1839 BaseIoAddress1[0]);
1840 if(BaseIoAddress2[0])
1841 ScsiPortFreeDeviceBase(HwDeviceExtension,
1842 BaseIoAddress2[0]);
1843
1844 if(BaseIoAddress1[1])
1845 ScsiPortFreeDeviceBase(HwDeviceExtension,
1846 BaseIoAddress1[1]);
1847 if(BaseIoAddress2[1])
1848 ScsiPortFreeDeviceBase(HwDeviceExtension,
1849 BaseIoAddress2[1]);
1850
1851 if(BaseIoAddressBM_0)
1852 ScsiPortFreeDeviceBase(HwDeviceExtension,
1853 BaseIoAddressBM_0);
1854
1855 if(deviceExtension->BaseIoAHCI_0.Addr) {
1856 ScsiPortFreeDeviceBase(HwDeviceExtension,
1857 deviceExtension->BaseIoAHCI_0.pAddr);
1858 }
1859
1860 KdPrint2((PRINT_PREFIX "return SP_RETURN_NOT_FOUND\n"));
1861 goto exit_notfound;
1862 } else {
1863
1864 KdPrint2((PRINT_PREFIX "exit: init spinlock\n"));
1865 //KeInitializeSpinLock(&(deviceExtension->DpcSpinLock));
1866 deviceExtension->ActiveDpcChan =
1867 deviceExtension->FirstDpcChan = CHAN_NOT_SPECIFIED;
1868
1869 BMList[i].Isr2Enable = FALSE;
1870
1871 KdPrint2((PRINT_PREFIX "MasterDev=%#x, NumberChannels=%#x, Isr2DevObj=%#x\n",
1872 MasterDev, deviceExtension->NumberChannels, BMList[i].Isr2DevObj));
1873
1874 // ConnectIntr2 should be moved to HwInitialize
1875 status = UniataConnectIntr2(HwDeviceExtension);
1876
1877 KdPrint2((PRINT_PREFIX "MasterDev=%#x, NumberChannels=%#x, Isr2DevObj=%#x\n",
1878 MasterDev, deviceExtension->NumberChannels, BMList[i].Isr2DevObj));
1879
1880 if(/*WinVer_WDM_Model &&*/ MasterDev) {
1881 KdPrint2((PRINT_PREFIX "do not tell system, that we know about PCI IO ranges\n"));
1882/* if(BaseIoAddressBM_0) {
1883 ScsiPortFreeDeviceBase(HwDeviceExtension,
1884 BaseIoAddressBM_0);
1885 }*/
1886 (*ConfigInfo->AccessRanges)[4].RangeStart = ScsiPortConvertUlongToPhysicalAddress(0);
1887 (*ConfigInfo->AccessRanges)[4].RangeLength = 0;
1888 (*ConfigInfo->AccessRanges)[5].RangeStart = ScsiPortConvertUlongToPhysicalAddress(0);
1889 (*ConfigInfo->AccessRanges)[5].RangeLength = 0;
1890 }
1891
1892 if(!NT_SUCCESS(status)) {
1893 KdPrint2((PRINT_PREFIX "failed\n"));
1894 found = FALSE;
1895 goto exit_findbm;
1896 }
1897
1898 KdPrint2((PRINT_PREFIX "final chan[%d] InterruptMode: %d, Level %d, Level2 %d, Vector %d, Vector2 %d\n",
1899 channel,
1900 ConfigInfo->InterruptMode,
1901 ConfigInfo->BusInterruptLevel,
1902 ConfigInfo->BusInterruptLevel2,
1903 ConfigInfo->BusInterruptVector,
1904 ConfigInfo->BusInterruptVector2
1905 ));
1906
1907
1908 }
1909#endif //UNIATA_CORE
1910
1911 KdPrint2((PRINT_PREFIX "return SP_RETURN_FOUND\n"));
1912 //PrintNtConsole("return SP_RETURN_FOUND, de %#x, c0.lun0 %#x\n", deviceExtension, deviceExtension->chan[0].lun[0]);
1913
1914 if(MasterDev) {
1915 KdPrint2((PRINT_PREFIX "Attempt %d of MasterDev ok\n", AltInit));
1916 FirstMasterOk = TRUE;
1917 }
1918
1919 ConfigInfo->NumberOfBuses++; // add virtual channel for communication port
1920 return SP_RETURN_FOUND;
1921
1922exit_error:
1923 UniataFreeLunExt(deviceExtension);
1924 return SP_RETURN_ERROR;
1925
1926exit_notfound:
1927 UniataFreeLunExt(deviceExtension);
1928 return SP_RETURN_NOT_FOUND;
1929
1930} // end UniataFindBusMasterController()
GetBaseStatus
#define GetBaseStatus(BaseIoAddress, Status)
Definition: atapi.h:331
PIDE_REGISTERS_2
struct _IDE_REGISTERS_2 * PIDE_REGISTERS_2
PIDE_REGISTERS_1
struct _IDE_REGISTERS_1 * PIDE_REGISTERS_1
HW_LU_EXTENSION
struct _HW_LU_EXTENSION HW_LU_EXTENSION
HW_DEVICE_EXTENSION
struct _HW_DEVICE_EXTENSION HW_DEVICE_EXTENSION
IDE_MAX_CHAN
#define IDE_MAX_CHAN
Definition: bm_devs_decl.h:42
UNIATA_NO_SLAVE
#define UNIATA_NO_SLAVE
Definition: bm_devs_decl.h:625
UNIATA_NO_DPC
#define UNIATA_NO_DPC
Definition: bm_devs_decl.h:627
IDE_DEFAULT_MAX_CHAN
#define IDE_DEFAULT_MAX_CHAN
Definition: bm_devs_decl.h:43
Ata_is_supported_dev
#define Ata_is_supported_dev(pciData)
Definition: bm_devs_decl.h:777
ScsiPortValidateRange
BOOLEAN NTAPI ScsiPortValidateRange(IN PVOID HwDeviceExtension, IN INTERFACE_TYPE BusType, IN ULONG SystemIoBusNumber, IN SCSI_PHYSICAL_ADDRESS IoAddress, IN ULONG NumberOfBytes, IN BOOLEAN InIoSpace)
Definition: scsiport.c:1497
AtapiDmaDone
UCHAR NTAPI AtapiDmaDone(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb)
Definition: id_dma.cpp:685
WinVer_WDM_Model
BOOLEAN WinVer_WDM_Model
Definition: id_ata.cpp:112
UniataChipDetect
NTSTATUS NTAPI UniataChipDetect(IN PVOID HwDeviceExtension, IN PPCI_COMMON_CONFIG pciData, IN ULONG DeviceNumber, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN BOOLEAN *simplexOnly)
Definition: id_init.cpp:339
IsMasterDev
#define IsMasterDev(pciData)
Definition: bsmaster.h:861
ATA_ALTOFFSET
#define ATA_ALTOFFSET
Definition: bsmaster.h:87
ATA_BM_OFFSET1
#define ATA_BM_OFFSET1
Definition: bsmaster.h:85
AtapiSetupLunPtrs
VOID NTAPI AtapiSetupLunPtrs(IN PHW_CHANNEL chan, IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG c)
Definition: id_init.cpp:2846
ATA_PCCARD_ALTOFFSET
#define ATA_PCCARD_ALTOFFSET
Definition: bsmaster.h:88
ATA_REQ
union _ATA_REQ ATA_REQ
PIDE_BUSMASTER_REGISTERS
struct _IDE_BUSMASTER_REGISTERS * PIDE_BUSMASTER_REGISTERS
BM_STATUS_SIMPLEX_ONLY
#define BM_STATUS_SIMPLEX_ONLY
Definition: bsmaster.h:148
IsBusMaster
#define IsBusMaster(pciData)
Definition: bsmaster.h:853
AtapiDmaAlloc
VOID NTAPI AtapiDmaAlloc(IN PVOID HwDeviceExtension, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN ULONG lChannel)
Definition: id_dma.cpp:138
g_Dump
BOOLEAN g_Dump
Definition: id_ata.cpp:108
ATA_IOSIZE
#define ATA_IOSIZE
Definition: bsmaster.h:86
PCI_DEV_CLASS_STORAGE
#define PCI_DEV_CLASS_STORAGE
Definition: bsmaster.h:117
AtapiReadChipConfig
BOOLEAN NTAPI AtapiReadChipConfig(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG channel)
Definition: id_init.cpp:1782
InDriverEntry
BOOLEAN InDriverEntry
Definition: id_ata.cpp:107
IO_WD2
#define IO_WD2
Definition: bsmaster.h:79
ATA_ALTIOSIZE
#define ATA_ALTIOSIZE
Definition: bsmaster.h:89
UniataFreeLunExt
VOID NTAPI UniataFreeLunExt(PHW_DEVICE_EXTENSION deviceExtension)
Definition: id_init.cpp:2956
AtapiChipInit
BOOLEAN NTAPI AtapiChipInit(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG c)
Definition: id_init.cpp:1879
IO_WD1
#define IO_WD1
Definition: bsmaster.h:78
ForceSimplex
ULONG ForceSimplex
Definition: id_ata.cpp:78
FindDevices
MMRESULT FindDevices()
Definition: utils.c:159
PtrToUlong
#define PtrToUlong(u)
Definition: config.h:107
SP_RETURN_ERROR
#define SP_RETURN_ERROR
Definition: srb.h:523
SP_RETURN_FOUND
#define SP_RETURN_FOUND
Definition: srb.h:522
SP_RETURN_NOT_FOUND
#define SP_RETURN_NOT_FOUND
Definition: srb.h:521
PPORT_CONFIGURATION_INFORMATION_COMMON
struct _PORT_CONFIGURATION_INFORMATION_COMMON * PPORT_CONFIGURATION_INFORMATION_COMMON
WinVer_2k
#define WinVer_2k
Definition: CrossNt.h:114
MicroChannel
@ MicroChannel
Definition: hwresource.cpp:140
Isa
@ Isa
Definition: hwresource.cpp:138
BMListLen
ULONG BMListLen
Definition: id_probe.cpp:54
AtdiskSecondaryClaimed
BOOLEAN AtdiskSecondaryClaimed
Definition: id_probe.cpp:62
UniataCheckPCISubclass
BOOLEAN NTAPI UniataCheckPCISubclass(BOOLEAN known, ULONG RaidFlags, UCHAR SubClass)
Definition: id_probe.cpp:256
UniataConnectIntr2
NTSTATUS NTAPI UniataConnectIntr2(IN PVOID HwDeviceExtension)
Definition: id_probe.cpp:2050
AtapiGetIoRange
ULONGIO_PTR NTAPI AtapiGetIoRange(IN PVOID HwDeviceExtension, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN PPCI_COMMON_CONFIG pciData, IN ULONG SystemIoBusNumber, IN ULONG rid, IN ULONG offset, IN ULONG length)
Definition: id_probe.cpp:153
AtdiskPrimaryClaimed
BOOLEAN AtdiskPrimaryClaimed
Definition: id_probe.cpp:61
UniataEnableIoPCI
USHORT NTAPI UniataEnableIoPCI(IN ULONG busNumber, IN ULONG slotNumber, IN OUT PPCI_COMMON_CONFIG pciData)
Definition: id_probe.cpp:95
FirstMasterOk
BOOLEAN FirstMasterOk
Definition: id_probe.cpp:58
IoGetConfigurationInformation
PCONFIGURATION_INFORMATION NTAPI IoGetConfigurationInformation(VOID)
Returns a pointer to the I/O manager's global configuration information structure.
Definition: iorsrce.c:998
Latched
@ Latched
Definition: miniport.h:81
LevelSensitive
@ LevelSensitive
Definition: miniport.h:80
Width16Bits
@ Width16Bits
Definition: miniport.h:106
DbgDumpRegTranslation
#define DbgDumpRegTranslation(chan, idx)
Definition: tools.h:135
_BUSMASTER_CONTROLLER_INFORMATION::slotNumber
ULONG slotNumber
Definition: bm_devs_decl.h:87
_CONFIGURATION_INFORMATION::ScsiPortCount
ULONG ScsiPortCount
Definition: iotypes.h:4479
_HW_CHANNEL::PrimaryAddress
BOOLEAN PrimaryAddress
Definition: bsmaster.h:1036
_HW_CHANNEL::RegTranslation
IORES RegTranslation[IDX_MAX_REG]
Definition: bsmaster.h:1127
_HW_DEVICE_EXTENSION::FirstDpcChan
ULONG FirstDpcChan
Definition: bsmaster.h:1271
_HW_DEVICE_EXTENSION::DriverMustPoll
BOOLEAN DriverMustPoll
Definition: atapi.c:111
_HW_DEVICE_EXTENSION::AdapterInterfaceType
INTERFACE_TYPE AdapterInterfaceType
Definition: bsmaster.h:1316
_HW_DEVICE_EXTENSION::Signature
CHAR Signature[32]
Definition: bsmaster.h:1239
_HW_DEVICE_EXTENSION::ActiveDpcChan
ULONG ActiveDpcChan
Definition: bsmaster.h:1270
_HW_DEVICE_EXTENSION::UseDpc
BOOLEAN UseDpc
Definition: bsmaster.h:1264
_IORES::pAddr
PVOID pAddr
Definition: bsmaster.h:1011
_IORES::MemIo
ULONG MemIo
Definition: bsmaster.h:1013
_PORT_CONFIGURATION_INFORMATION_2K::Dma64BitAddresses
UCHAR Dma64BitAddresses
Definition: srb.h:121
_PORT_CONFIGURATION_INFORMATION_2K::MaximumNumberOfLogicalUnits
UCHAR MaximumNumberOfLogicalUnits
Definition: srb.h:127
_PORT_CONFIGURATION_INFORMATION_2K::ResetTargetSupported
BOOLEAN ResetTargetSupported
Definition: srb.h:124
_PORT_CONFIGURATION_INFORMATION_COMMON
Definition: srb.h:136
_PORT_CONFIGURATION_INFORMATION_COMMON::comm
PORT_CONFIGURATION_INFORMATION comm
Definition: srb.h:137
_PORT_CONFIGURATION_INFORMATION_COMMON::w2k
PORT_CONFIGURATION_INFORMATION_2K w2k
Definition: srb.h:139
_PORT_CONFIGURATION_INFORMATION_COMMON::nt4
PORT_CONFIGURATION_INFORMATION_NT nt4
Definition: srb.h:138
_PORT_CONFIGURATION_INFORMATION_NT::DeviceExtensionSize
ULONG DeviceExtensionSize
Definition: srb.h:113
_PORT_CONFIGURATION_INFORMATION_NT::SpecificLuExtensionSize
ULONG SpecificLuExtensionSize
Definition: srb.h:114
_PORT_CONFIGURATION_INFORMATION_NT::SrbExtensionSize
ULONG SrbExtensionSize
Definition: srb.h:115
UniataDumpATARegs
VOID NTAPI UniataDumpATARegs(IN struct _HW_CHANNEL *chan)
IDX_IO2
#define IDX_IO2
Definition: atapi.h:222
UniataInitMapBase
VOID NTAPI UniataInitMapBase(IN struct _HW_CHANNEL *chan, IN PIDE_REGISTERS_1 BaseIoAddress1, IN PIDE_REGISTERS_2 BaseIoAddress2)
UniataInitMapBM
VOID NTAPI UniataInitMapBM(IN struct _HW_DEVICE_EXTENSION *deviceExtension, IN struct _IDE_BUSMASTER_REGISTERS *BaseIoAddressBM_0, IN BOOLEAN MemIo)
_LARGE_INTEGER
Definition: typedefs.h:103
_LARGE_INTEGER::QuadPart
LONGLONG QuadPart
Definition: typedefs.h:114
PCI_INVALID_VENDORID
#define PCI_INVALID_VENDORID
Definition: iotypes.h:3601
PCI_TYPE0_ADDRESSES
#define PCI_TYPE0_ADDRESSES
Definition: iotypes.h:3500
_snprintf
#define _snprintf
Definition: xmlstorage.h:200

Referenced by DriverEntry(), UniataFindCompatBusMasterController1(), and UniataFindCompatBusMasterController2().

◆ UniataFindCompatBusMasterController1()

ULONG NTAPI UniataFindCompatBusMasterController1 ( IN PVOID  HwDeviceExtension,
IN PVOID  Context,
IN PVOID  BusInformation,
IN PCHAR  ArgumentString,
IN OUT PPORT_CONFIGURATION_INFORMATION  ConfigInfo,
OUT PBOOLEAN  Again 
)

Definition at line 924 of file id_probe.cpp.

932{
933 return UniataFindBusMasterController(
934 HwDeviceExtension,
935 UlongToPtr(0x00000000),
936 BusInformation,
937 ArgumentString,
938 ConfigInfo,
939 Again
940 );
941} // end UniataFindCompatBusMasterController1()
UlongToPtr
#define UlongToPtr(u)
Definition: config.h:106
UniataFindBusMasterController
ULONG NTAPI UniataFindBusMasterController(IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
Definition: id_probe.cpp:988
BusInformation
_In_ WDFDEVICE _In_ PPNP_BUS_INFORMATION BusInformation
Definition: wdfdevice.h:3915

Referenced by DriverEntry().

◆ UniataFindCompatBusMasterController2()

ULONG NTAPI UniataFindCompatBusMasterController2 ( IN PVOID  HwDeviceExtension,
IN PVOID  Context,
IN PVOID  BusInformation,
IN PCHAR  ArgumentString,
IN OUT PPORT_CONFIGURATION_INFORMATION  ConfigInfo,
OUT PBOOLEAN  Again 
)

Definition at line 945 of file id_probe.cpp.

953{
954 return UniataFindBusMasterController(
955 HwDeviceExtension,
956 UlongToPtr(0x80000000),
957 BusInformation,
958 ArgumentString,
959 ConfigInfo,
960 Again
961 );
962} // end UniataFindCompatBusMasterController2()

Referenced by DriverEntry().

◆ UniataForgetDevice()

VOID NTAPI UniataForgetDevice ( PHW_LU_EXTENSION  LunExt)

Definition at line 2385 of file id_ata.cpp.

2388{
2389 // keep only DFLAGS_HIDDEN flag
2390 LunExt->DeviceFlags &= DFLAGS_HIDDEN;
2391 LunExt->AtapiReadyWaitDelay = 0;
2392} // end UniataForgetDevice()
_HW_LU_EXTENSION::AtapiReadyWaitDelay
ULONG AtapiReadyWaitDelay
Definition: bsmaster.h:1191
DFLAGS_HIDDEN
#define DFLAGS_HIDDEN
Definition: atapi.h:253

Referenced by AtapiResetController__(), AtapiStartIo__(), CheckDevice(), FindDevices(), IdeSendCommand(), UniataAhciReset(), UniataAnybodyHome(), and UniataSataEvent().

◆ UniataFreeLunExt()

VOID NTAPI UniataFreeLunExt ( PHW_DEVICE_EXTENSION  deviceExtension)

Definition at line 2956 of file id_init.cpp.

2959{
2960 if (deviceExtension->lun) {
2961 ExFreePool(deviceExtension->lun);
2962 deviceExtension->lun = NULL;
2963 }
2964 if (deviceExtension->chan) {
2965 ExFreePool(deviceExtension->chan);
2966 deviceExtension->chan = NULL;
2967 }
2968 if(deviceExtension->AhciInternalAtaReq0) {
2969 ExFreePool(deviceExtension->AhciInternalAtaReq0);
2970 deviceExtension->AhciInternalAtaReq0 = NULL;
2971 }
2972 if(deviceExtension->AhciInternalSrb0) {
2973 ExFreePool(deviceExtension->AhciInternalSrb0);
2974 deviceExtension->AhciInternalSrb0 = NULL;
2975 }
2976
2977 return;
2978} // end UniataFreeLunExt()

Referenced by AtapiFindIsaController(), and UniataAllocateLunExt().

Variable Documentation

◆ BMList

PBUSMASTER_CONTROLLER_INFORMATION BMList
extern

Definition at line 53 of file id_probe.cpp.

Referenced by AtapiAdapterControl(), AtapiHwInitialize(), AtapiInterrupt2(), AtapiStartIo__(), DriverEntry(), UniataChipDetectChannels(), UniataClaimLegacyPCIIDE(), UniataConnectIntr2(), UniataDisconnectIntr2(), UniataEnumBusMasterController__(), and UniataFindBusMasterController().

◆ BMListLen

ULONG BMListLen
extern

Definition at line 54 of file id_probe.cpp.

Referenced by AtapiRegCheckDevValue(), DriverEntry(), UniataEnumBusMasterController__(), and UniataFindBusMasterController().

◆ CPU_num

ULONG CPU_num
extern

Definition at line 113 of file id_ata.cpp.

Referenced by AtaSetTransferMode(), and DriverEntry().

◆ ForceSimplex

ULONG ForceSimplex
extern

Definition at line 78 of file id_ata.cpp.

Referenced by DriverEntry(), and UniataFindBusMasterController().

◆ g_Dump

BOOLEAN g_Dump
extern

Definition at line 108 of file id_ata.cpp.

Referenced by AtapiFindIsaController(), AtapiReadArgumentString(), AtapiRegCheckParameterValue(), CheckDevice(), DriverEntry(), and UniataFindBusMasterController().

◆ g_opt_AtapiDmaRawRead

BOOLEAN g_opt_AtapiDmaRawRead
extern

Definition at line 100 of file id_ata.cpp.

Referenced by AtapiReadChipConfig(), and DriverEntry().

◆ g_opt_Verbose

BOOLEAN g_opt_Verbose
extern

Definition at line 110 of file id_ata.cpp.

Referenced by DriverEntry().

◆ g_opt_VirtualMachine

ULONG g_opt_VirtualMachine
extern

Definition at line 105 of file id_ata.cpp.

Referenced by AtapiInterrupt__(), AtapiResetController__(), AtapiSoftReset(), CheckDevice(), DriverEntry(), IssueIdentify(), UniataAnybodyHome(), UniataChipDetectChannels(), and UniataEnumBusMasterController__().

◆ g_opt_WaitBusyResetCount

ULONG g_opt_WaitBusyResetCount
extern

Definition at line 89 of file id_ata.cpp.

Referenced by CheckDevice(), and DriverEntry().

◆ hasPCI

BOOLEAN hasPCI
extern

Definition at line 103 of file id_ata.cpp.

Referenced by AtapiFindIsaController(), DriverEntry(), and UniataEnumBusMasterController__().

◆ InDriverEntry

BOOLEAN InDriverEntry
extern

Definition at line 107 of file id_ata.cpp.

Referenced by DriverEntry(), and UniataFindBusMasterController().

◆ IsaCount

ULONG IsaCount
extern

Definition at line 55 of file id_probe.cpp.

Referenced by AtapiFindIsaController(), and AtapiRegCheckDevValue().

◆ MCACount

ULONG MCACount
extern

Definition at line 56 of file id_probe.cpp.

Referenced by AtapiFindIsaController().

◆ pciBuffer

UCHAR pciBuffer[256]
extern

Definition at line 66 of file id_probe.cpp.

Referenced by AtapiFindController(), and FindBrokenController().

◆ SavedDriverObject

PDRIVER_OBJECT SavedDriverObject
extern

Definition at line 69 of file id_probe.cpp.

Referenced by DriverEntry(), UniataClaimLegacyPCIIDE(), and UniataConnectIntr2().

◆ SavedRegPath

UNICODE_STRING SavedRegPath
extern

Definition at line 69 of file id_ata.cpp.

Referenced by AtapiRegCheckParameterValue(), DriverEntry(), and UniataClaimLegacyPCIIDE().

◆ SkipRaids

ULONG SkipRaids
extern

Definition at line 77 of file id_ata.cpp.

Referenced by DriverEntry(), and UniataCheckPCISubclass().

◆ WinVer_WDM_Model

BOOLEAN WinVer_WDM_Model
extern

Definition at line 112 of file id_ata.cpp.

Referenced by AtapiHwInitialize(), DriverEntry(), and UniataFindBusMasterController().