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ReactOS Development > Doxygen

Data Structures | Defines | Functions | Variables
bsmaster.h File Reference
#include "config.h"
#include "tools.h"
#include "bm_devs.h"
#include "uata_ctl.h"

Go to the source code of this file.

Data Structures

struct  PBUSMASTER_CTX
struct  PBM_DMA_ENTRY
struct  PIDE_BUSMASTER_REGISTERS
struct  PIDE_AHCI_REGISTERS
union  PSATA_SSTATUS_REG
union  PSATA_SCONTROL_REG
union  PSATA_SERROR_REG
struct  PIDE_SATA_REGISTERS
union  PAHCI_IS_REG
struct  PIDE_AHCI_PORT_REGISTERS
struct  PIDE_AHCI_PRD_ENTRY
struct  PIDE_AHCI_CMD
struct  PIDE_AHCI_CMD_LIST
struct  PIDE_AHCI_RCV_FIS
struct  PIDE_AHCI_CHANNEL_CTL_BLOCK
union  PATA_REQ
struct  PIORES
struct  PHW_CHANNEL
struct  PHW_LU_EXTENSION
struct  PHW_DEVICE_EXTENSION
struct  PISR2_DEVICE_EXTENSION

Defines

#define ATA_IDLE   0x0
#define ATA_IMMEDIATE   0x1
#define ATA_WAIT_INTR   0x2
#define ATA_WAIT_READY   0x3
#define ATA_ACTIVE   0x4
#define ATA_ACTIVE_ATA   0x5
#define ATA_ACTIVE_ATAPI   0x6
#define ATA_REINITING   0x7
#define ATA_WAIT_BASE_READY   0x8
#define ATA_WAIT_IDLE   0x9
#define MAX_RETRIES   6
#define RETRY_UDMA2   1
#define RETRY_WDMA   2
#define RETRY_PIO   3
#define IO_WD1   0x1F0 /* Primary Fixed Disk Controller */
#define IO_WD2   0x170 /* Secondary Fixed Disk Controller */
#define IP_PC98_BANK   0x432
#define PCI_ADDRESS_IOMASK   0xfffffff0
#define ATA_BM_OFFSET1   0x08
#define ATA_IOSIZE   0x08
#define ATA_ALTOFFSET   0x206 /* alternate registers offset */
#define ATA_PCCARD_ALTOFFSET   0x0e /* do for PCCARD devices */
#define ATA_ALTIOSIZE   0x01 /* alternate registers size */
#define ATA_BMIOSIZE   0x20
#define ATA_PC98_BANKIOSIZE   0x01
#define ATA_MAX_IOLBA28   DEF_U64(0x0fffff80)
#define ATA_MAX_LBA28   DEF_U64(0x0fffffff)
#define ATA_DMA_ENTRIES   256 /* PAGESIZE/2/sizeof(BM_DMA_ENTRY)*/
#define ATA_DMA_EOT   0x80000000
#define DEV_BSIZE   512
#define ATAPI_MAGIC_LSB   0x14
#define ATAPI_MAGIC_MSB   0xeb
#define AHCI_MAX_PORT   32
#define SATA_MAX_PM_UNITS   16
#define PCI_DEV_CLASS_STORAGE   0x01
#define PCI_DEV_SUBCLASS_IDE   0x01
#define PCI_DEV_SUBCLASS_RAID   0x04
#define PCI_DEV_SUBCLASS_ATA   0x05
#define PCI_DEV_SUBCLASS_SATA   0x06
#define PCI_DEV_PROGIF_AHCI_1_0   0x01
#define BM_STATUS_ACTIVE   0x01
#define BM_STATUS_ERR   0x02
#define BM_STATUS_INTR   0x04
#define BM_STATUS_MASK   0x07
#define BM_STATUS_DRIVE_0_DMA   0x20
#define BM_STATUS_DRIVE_1_DMA   0x40
#define BM_STATUS_SIMPLEX_ONLY   0x80
#define BM_COMMAND_START_STOP   0x01
#define BM_COMMAND_WRITE   0x00
#define BM_COMMAND_READ   0x08
#define BM_DS0_SII_DMA_ENABLE   (1 << 0) /* DMA run switch */
#define BM_DS0_SII_IRQ   (1 << 3) /* ??? */
#define BM_DS0_SII_DMA_SATA_IRQ   (1 << 4) /* OR of all SATA IRQs */
#define BM_DS0_SII_DMA_ERROR   (1 << 17) /* PCI bus error */
#define BM_DS0_SII_DMA_COMPLETE   (1 << 18) /* cmd complete / IRQ pending */
#define IDX_BM_IO   (IDX_IO2_o+IDX_IO2_o_SZ)
#define IDX_BM_IO_SZ   5
#define IDX_BM_Command   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Command )+IDX_BM_IO)
#define IDX_BM_DeviceSpecific0   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific0)+IDX_BM_IO)
#define IDX_BM_Status   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Status )+IDX_BM_IO)
#define IDX_BM_DeviceSpecific1   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific1)+IDX_BM_IO)
#define IDX_BM_PRD_Table   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, PRD_Table )+IDX_BM_IO)
#define AHCI_CAP_NOP_MASK   0x0000001f
#define AHCI_CAP_NCS_MASK   0x00001f00
#define AHCI_CAP_PMD   0x00008000
#define AHCI_CAP_SPM   0x00020000
#define AHCI_CAP_SAM   0x00040000
#define AHCI_CAP_SCLO   0x01000000
#define AHCI_CAP_S64A   0x80000000
#define AHCI_GHC   0x04
#define AHCI_GHC_HR   0x00000001
#define AHCI_GHC_IE   0x00000002
#define AHCI_GHC_AE   0x80000000
#define IDX_AHCI_CAP   (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP))
#define IDX_AHCI_GHC   (FIELD_OFFSET(IDE_AHCI_REGISTERS, GHC))
#define IDX_AHCI_IS   (FIELD_OFFSET(IDE_AHCI_REGISTERS, IS))
#define IDX_AHCI_VS   (FIELD_OFFSET(IDE_AHCI_REGISTERS, VS))
#define IDX_AHCI_PI   (FIELD_OFFSET(IDE_AHCI_REGISTERS, PI))
#define SStatus_DET_NoDev   0x00
#define SStatus_DET_Dev_NoPhy   0x01
#define SStatus_DET_Dev_Ok   0x03
#define SStatus_DET_Offline   0x04
#define SStatus_SPD_NoDev   0x00
#define SStatus_SPD_Gen1   0x01
#define SStatus_SPD_Gen2   0x02
#define SStatus_SPD_Gen3   0x03
#define SStatus_IPM_NoDev   0x00
#define SStatus_IPM_Active   0x01
#define SStatus_IPM_Partial   0x02
#define SStatus_IPM_Slumber   0x06
#define SControl_DET_DoNothing   0x00
#define SControl_DET_Idle   0x00
#define SControl_DET_Init   0x01
#define SControl_DET_Disable   0x04
#define SControl_SPD_NoRestrict   0x00
#define SControl_SPD_LimGen1   0x01
#define SControl_SPD_LimGen2   0x02
#define SControl_SPD_LimGen3   0x03
#define SControl_IPM_NoRestrict   0x00
#define SControl_IPM_NoPartial   0x01
#define SControl_IPM_NoSlumber   0x02
#define SControl_IPM_NoPartialSlumber   0x03
#define IDX_SATA_IO   (IDX_BM_IO+IDX_BM_IO_SZ)
#define IDX_SATA_IO_SZ   5
#define IDX_SATA_SStatus   (0+IDX_SATA_IO)
#define IDX_SATA_SError   (1+IDX_SATA_IO)
#define IDX_SATA_SControl   (2+IDX_SATA_IO)
#define IDX_SATA_SActive   (3+IDX_SATA_IO)
#define IDX_SATA_SNTF_PMN   (4+IDX_SATA_IO)
#define IDX_INDEXED_IO   (IDX_SATA_IO+IDX_SATA_IO_SZ)
#define IDX_INDEXED_IO_SZ   2
#define IDX_INDEXED_ADDR   (0+IDX_INDEXED_IO)
#define IDX_INDEXED_DATA   (1+IDX_INDEXED_IO)
#define IDX_MAX_REG   (IDX_INDEXED_IO+IDX_INDEXED_IO_SZ)
#define ATA_AHCI_P_IX_DHR   0x00000001
#define ATA_AHCI_P_IX_PS   0x00000002
#define ATA_AHCI_P_IX_DS   0x00000004
#define ATA_AHCI_P_IX_SDB   0x00000008
#define ATA_AHCI_P_IX_UF   0x00000010
#define ATA_AHCI_P_IX_DP   0x00000020
#define ATA_AHCI_P_IX_PC   0x00000040
#define ATA_AHCI_P_IX_DI   0x00000080
#define ATA_AHCI_P_IX_PRC   0x00400000
#define ATA_AHCI_P_IX_IPM   0x00800000
#define ATA_AHCI_P_IX_OF   0x01000000
#define ATA_AHCI_P_IX_INF   0x04000000
#define ATA_AHCI_P_IX_IF   0x08000000
#define ATA_AHCI_P_IX_HBD   0x10000000
#define ATA_AHCI_P_IX_HBF   0x20000000
#define ATA_AHCI_P_IX_TFE   0x40000000
#define ATA_AHCI_P_IX_CPD   0x80000000
#define AHCI_CLB_ALIGNEMENT_MASK   ((ULONGLONG)(1024-1))
#define AHCI_FIS_ALIGNEMENT_MASK   ((ULONGLONG)(256-1))
#define AHCI_CMD_ALIGNEMENT_MASK   ((ULONGLONG)(128-1))
#define SATA_CMD_ICC_Idle   0x00
#define SATA_CMD_ICC_NoOp   0x00
#define SATA_CMD_ICC_Active   0x01
#define SATA_CMD_ICC_Partial   0x02
#define SATA_CMD_ICC_Slumber   0x06
#define IDX_AHCI_P_CLB   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CLB))
#define IDX_AHCI_P_FB   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, FB))
#define IDX_AHCI_P_IS   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IS))
#define IDX_AHCI_P_IE   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IE))
#define IDX_AHCI_P_CI   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CI))
#define IDX_AHCI_P_TFD   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, TFD))
#define IDX_AHCI_P_SIG   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SIG))
#define IDX_AHCI_P_CMD   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CMD))
#define IDX_AHCI_P_SNTF   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SNTF))
#define ATA_AHCI_P_CMD_ST   0x00000001
#define ATA_AHCI_P_CMD_SUD   0x00000002
#define ATA_AHCI_P_CMD_POD   0x00000004
#define ATA_AHCI_P_CMD_CLO   0x00000008
#define ATA_AHCI_P_CMD_FRE   0x00000010
#define ATA_AHCI_P_CMD_CCS_MASK   0x00001f00
#define ATA_AHCI_P_CMD_ISS   0x00002000
#define ATA_AHCI_P_CMD_FR   0x00004000
#define ATA_AHCI_P_CMD_CR   0x00008000
#define ATA_AHCI_P_CMD_CPS   0x00010000
#define ATA_AHCI_P_CMD_PMA   0x00020000
#define ATA_AHCI_P_CMD_HPCP   0x00040000
#define ATA_AHCI_P_CMD_ISP   0x00080000
#define ATA_AHCI_P_CMD_CPD   0x00100000
#define ATA_AHCI_P_CMD_ATAPI   0x01000000
#define ATA_AHCI_P_CMD_DLAE   0x02000000
#define ATA_AHCI_P_CMD_ALPE   0x04000000
#define ATA_AHCI_P_CMD_ASP   0x08000000
#define ATA_AHCI_P_CMD_ICC_MASK   0xf0000000
#define ATA_AHCI_P_CMD_NOOP   0x00000000
#define ATA_AHCI_P_CMD_ACTIVE   0x10000000
#define ATA_AHCI_P_CMD_PARTIAL   0x20000000
#define ATA_AHCI_P_CMD_SLUMBER   0x60000000
#define ATA_AHCI_DMA_ENTRIES   (PAGE_SIZE/2/sizeof(IDE_AHCI_PRD_ENTRY)) /* 128 */
#define ATA_AHCI_MAX_TAGS   32
#define AHCI_FIS_TYPE_ATA_H2D   0x27
#define AHCI_FIS_TYPE_ATA_D2H   0x34
#define AHCI_FIS_COMM_PM   (0x80 | AHCI_DEV_SEL_PM)
#define AHCI_DEV_SEL_1   0x00
#define AHCI_DEV_SEL_2   0x01
#define AHCI_DEV_SEL_PM   0x0f
#define ATA_AHCI_CMD_ATAPI   0x0020
#define ATA_AHCI_CMD_WRITE   0x0040
#define ATA_AHCI_CMD_PREFETCH   0x0080
#define ATA_AHCI_CMD_RESET   0x0100
#define ATA_AHCI_CMD_BIST   0x0200
#define ATA_AHCI_CMD_CLR_BUSY   0x0400
#define IsBusMaster(pciData)
#define PCI_IDE_PROGIF_NATIVE_1   0x01
#define PCI_IDE_PROGIF_NATIVE_2   0x04
#define PCI_IDE_PROGIF_NATIVE_ALL   0x05
#define IsMasterDev(pciData)
#define MIN_REQ_TTL   4
#define REQ_FLAG_FORCE_DOWNRATE   0x01
#define REQ_FLAG_DMA_OPERATION   0x02
#define REQ_FLAG_REORDERABLE_CMD   0x04
#define REQ_FLAG_RW_MASK   0x08
#define REQ_FLAG_READ   0x08
#define REQ_FLAG_WRITE   0x00
#define REQ_FLAG_FORCE_DOWNRATE_LBA48   0x10
#define REQ_FLAG_DMA_DBUF   0x20
#define REQ_FLAG_DMA_DBUF_PRD   0x40
#define REQ_FLAG_LBA48   0x80
#define REQ_STATE_NONE   0x00
#define REQ_STATE_QUEUED   0x10
#define REQ_STATE_PREPARE_TO_TRANSFER   0x20
#define REQ_STATE_PREPARE_TO_NEXT   0x21
#define REQ_STATE_READY_TO_TRANSFER   0x30
#define REQ_STATE_EXPECTING_INTR   0x40
#define REQ_STATE_ATAPI_EXPECTING_CMD_INTR   0x41
#define REQ_STATE_ATAPI_EXPECTING_DATA_INTR   0x42
#define REQ_STATE_ATAPI_DO_NOTHING_INTR   0x43
#define REQ_STATE_EARLY_INTR   0x48
#define REQ_STATE_PROCESSING_INTR   0x50
#define REQ_STATE_DPC_INTR_REQ   0x51
#define REQ_STATE_DPC_RESET_REQ   0x52
#define REQ_STATE_DPC_COMPLETE_REQ   0x53
#define REQ_STATE_DPC_WAIT_BUSY0   0x57
#define REQ_STATE_DPC_WAIT_BUSY1   0x58
#define REQ_STATE_DPC_WAIT_BUSY   0x59
#define REQ_STATE_DPC_WAIT_DRQ   0x5a
#define REQ_STATE_DPC_WAIT_DRQ0   0x5b
#define REQ_STATE_DPC_WAIT_DRQ_ERR   0x5c
#define REQ_STATE_TRANSFER_COMPLETE   0x7f
#define CMD_ACTION_PREPARE   0x01
#define CMD_ACTION_EXEC   0x02
#define CMD_ACTION_ALL   (CMD_ACTION_PREPARE | CMD_ACTION_EXEC)
#define REORDER_COST_MAX   ((DEF_I64(0x1) << 60) - 1)
#define REORDER_COST_TTL   (REORDER_COST_MAX - 1)
#define REORDER_COST_INTERSECT   (REORDER_COST_MAX - 2)
#define REORDER_COST_DENIED   (REORDER_COST_MAX - 3)
#define REORDER_COST_RESELECT   (REORDER_COST_MAX/4)
#define REORDER_COST_SWITCH_RW_CD   (REORDER_COST_MAX/8)
#define REORDER_MCOST_SWITCH_RW_CD   (0)
#define REORDER_MCOST_SEEK_BACK_CD   (16)
#define REORDER_COST_SWITCH_RW_HDD   (0)
#define REORDER_MCOST_SWITCH_RW_HDD   (4)
#define REORDER_MCOST_SEEK_BACK_HDD   (2)
#define CHECK_INTR_ACTIVE   0x03
#define CHECK_INTR_DETECTED   0x02
#define CHECK_INTR_CHECK   0x01
#define CHECK_INTR_IDLE   0x00
#define CTRFLAGS_DMA_ACTIVE   0x0001
#define CTRFLAGS_DMA_RO   0x0002
#define CTRFLAGS_DMA_OPERATION   0x0004
#define CTRFLAGS_INTR_DISABLED   0x0008
#define CTRFLAGS_DPC_REQ   0x0010
#define CTRFLAGS_ENABLE_INTR_REQ   0x0020
#define CTRFLAGS_LBA48   0x0040
#define CTRFLAGS_DSC_BSY   0x0080
#define CTRFLAGS_NO_SLAVE   0x0100
#define CTRFLAGS_AHCI_PM   0x0400
#define CTRFLAGS_AHCI_PM2   0x0800
#define CTRFLAGS_PERMANENT   (CTRFLAGS_DMA_RO | CTRFLAGS_NO_SLAVE)
#define GEOM_AUTO   0xffffffff
#define GEOM_STD   0x0000
#define GEOM_UNIATA   0x0001
#define GEOM_ORIG   0x0002
#define GEOM_MANUAL   0x0003
#define DPC_STATE_NONE   0x00
#define DPC_STATE_ISR   0x10
#define DPC_STATE_DPC   0x20
#define DPC_STATE_TIMER   0x30
#define DPC_STATE_COMPLETE   0x40
#define HBAFLAGS_DMA_DISABLED   0x01
#define HBAFLAGS_DMA_DISABLED_LBA48   0x02
#define UNIATA_ALLOCATE_NEW_LUNS   0x00
#define PCIBUSNUM_NOT_SPECIFIED   (0xffffffffL)
#define PCISLOTNUM_NOT_SPECIFIED   (0xffffffffL)
#define GetPciConfig1(offs, op)
#define SetPciConfig1(offs, op)
#define ChangePciConfig1(offs, _op)
#define GetPciConfig2(offs, op)
#define SetPciConfig2(offs, op)
#define ChangePciConfig2(offs, _op)
#define GetPciConfig4(offs, op)
#define SetPciConfig4(offs, op)
#define ChangePciConfig4(offs, _op)
#define GetDmaStatus(de, c)   (((de)->BusMaster) ? AtapiReadPort1(&((de)->chan[c]), IDX_BM_Status) : 0)
#define AtapiVirtToPhysAddr(hwde, srb, phaddr, plen, phaddru)   AtapiVirtToPhysAddr_(hwde, srb, phaddr, plen, phaddru);
#define GET_CHANNEL(Srb)   (Srb->PathId)
#define GET_CDEV(Srb)   (Srb->TargetId)
#define VM_AUTO   0x00
#define VM_NONE   0x01
#define VM_VBOX   0x02
#define VM_VMWARE   0x03
#define VM_QEMU   0x04
#define VM_MAX_KNOWN   VM_QEMU

Functions

VOID NTAPI UniataEnumBusMasterController (IN PVOID DriverObject, PVOID Argument2)
ULONG NTAPI UniataFindCompatBusMasterController1 (IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
ULONG NTAPI UniataFindCompatBusMasterController2 (IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
BOOLEAN NTAPI UniataAllocateLunExt (PHW_DEVICE_EXTENSION deviceExtension, ULONG NewNumberChannels)
ULONG NTAPI UniataFindBusMasterController (IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
ULONG NTAPI UniataFindFakeBusMasterController (IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
NTSTATUS NTAPI UniataConnectIntr2 (IN PVOID HwDeviceExtension)
NTSTATUS NTAPI UniataDisconnectIntr2 (IN PVOID HwDeviceExtension)
ULONG NTAPI ScsiPortGetBusDataByOffset (IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
ULONG NTAPI AtapiFindListedDev (PBUSMASTER_CONTROLLER_INFORMATION BusMasterAdapters, ULONG lim, IN PVOID HwDeviceExtension, IN ULONG BusNumber, IN ULONG SlotNumber, OUT PCI_SLOT_NUMBER *_slotData)
ULONG NTAPI AtapiFindDev (IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN ULONG dev_id, IN ULONG RevID)
VOID NTAPI AtapiDmaAlloc (IN PVOID HwDeviceExtension, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN ULONG lChannel)
BOOLEAN NTAPI AtapiDmaSetup (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb, IN PUCHAR data, IN ULONG count)
BOOLEAN NTAPI AtapiDmaPioSync (PVOID HwDeviceExtension, PSCSI_REQUEST_BLOCK Srb, PUCHAR data, ULONG count)
BOOLEAN NTAPI AtapiDmaDBSync (PHW_CHANNEL chan, PSCSI_REQUEST_BLOCK Srb)
VOID NTAPI AtapiDmaStart (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb)
UCHAR NTAPI AtapiDmaDone (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb)
VOID NTAPI AtapiDmaReinit (IN PHW_DEVICE_EXTENSION deviceExtension, IN PHW_LU_EXTENSION LunExt, IN PATA_REQ AtaReq)
VOID NTAPI AtapiDmaInit__ (IN PHW_DEVICE_EXTENSION deviceExtension, IN PHW_LU_EXTENSION LunExt)
VOID NTAPI AtapiDmaInit (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN SCHAR apiomode, IN SCHAR wdmamode, IN SCHAR udmamode)
BOOLEAN NTAPI AtapiInterrupt2 (IN PKINTERRUPT Interrupt, IN PVOID HwDeviceExtension)
BOOLEAN NTAPI UniataChipDetectChannels (IN PVOID HwDeviceExtension, IN PPCI_COMMON_CONFIG pciData, IN ULONG DeviceNumber, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo)
NTSTATUS NTAPI UniataChipDetect (IN PVOID HwDeviceExtension, IN PPCI_COMMON_CONFIG pciData, IN ULONG DeviceNumber, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN BOOLEAN *simplexOnly)
BOOLEAN NTAPI AtapiChipInit (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG c)
ULONG NTAPI AtapiGetIoRange (IN PVOID HwDeviceExtension, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN PPCI_COMMON_CONFIG pciData, IN ULONG SystemIoBusNumber, IN ULONG rid, IN ULONG offset, IN ULONG length)
VOID DDKFASTAPI AtapiWritePort4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG data)
VOID DDKFASTAPI AtapiWritePort2 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN USHORT data)
VOID DDKFASTAPI AtapiWritePort1 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN UCHAR data)
VOID DDKFASTAPI AtapiWritePortEx4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN ULONG data)
VOID DDKFASTAPI AtapiWritePortEx1 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN UCHAR data)
ULONG DDKFASTAPI AtapiReadPort4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
USHORT DDKFASTAPI AtapiReadPort2 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
UCHAR DDKFASTAPI AtapiReadPort1 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
ULONG DDKFASTAPI AtapiReadPortEx4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
UCHAR DDKFASTAPI AtapiReadPortEx1 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
VOID DDKFASTAPI AtapiWriteBuffer4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
VOID DDKFASTAPI AtapiWriteBuffer2 (IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
VOID DDKFASTAPI AtapiReadBuffer4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
VOID DDKFASTAPI AtapiReadBuffer2 (IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
VOID NTAPI AtapiSetupLunPtrs (IN PHW_CHANNEL chan, IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG c)
BOOLEAN NTAPI AtapiReadChipConfig (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG channel)
VOID NTAPI UniataForgetDevice (PHW_LU_EXTENSION LunExt)

Variables

UCHAR pciBuffer [256]
PBUSMASTER_CONTROLLER_INFORMATION BMList
ULONG BMListLen
ULONG IsaCount
ULONG MCACount
PDRIVER_OBJECT SavedDriverObject
ULONG SkipRaids
ULONG ForceSimplex
BOOLEAN g_opt_AtapiDmaRawRead
BOOLEAN InDriverEntry
BOOLEAN g_opt_Verbose
ULONG g_opt_VirtualMachine
BOOLEAN WinVer_WDM_Model
Generated on Sat May 26 2012 05:24:51 for ReactOS by doxygen 1.7.6.1
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