This graph shows which files directly or indirectly include this file:

Macros
#define	HDA_REG_GCAP 0x00

#define	HDA_GCAP_64OK (1 << 0) /* 64bit address support */

#define	HDA_GCAP_NSDO (3 << 1) /* # of serial data out signals */

#define	HDA_GCAP_BSS (31 << 3) /* # of bidirectional streams */

#define	HDA_GCAP_ISS (15 << 8) /* # of input streams */

#define	HDA_GCAP_OSS (15 << 12) /* # of output streams */

#define	HDA_REG_VMIN 0x02

#define	HDA_REG_VMAJ 0x03

#define	HDA_REG_OUTPAY 0x04

#define	HDA_REG_INPAY 0x06

#define	HDA_REG_GCTL 0x08

#define	HDA_GCTL_RESET (1 << 0) /* controller reset */

#define	HDA_GCTL_FCNTRL (1 << 1) /* flush control */

#define	HDA_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */

#define	HDA_REG_WAKEEN 0x0c

#define	HDA_REG_STATESTS 0x0e

#define	HDA_REG_GSTS 0x10

#define	HDA_GSTS_FSTS (1 << 1) /* flush status */

#define	HDA_REG_GCAP2 0x12

#define	HDA_REG_LLCH 0x14

#define	HDA_REG_OUTSTRMPAY 0x18

#define	HDA_REG_INSTRMPAY 0x1A

#define	HDA_REG_INTCTL 0x20

#define	HDA_REG_INTSTS 0x24

#define	HDA_REG_WALLCLK 0x30 /* 24Mhz source */

#define	HDA_REG_WALLCLKA 0x2030 /* 24Mhz source */

#define	HDA_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */

#define	HDA_REG_SSYNC 0x38

#define	HDA_REG_CORBLBASE 0x40

#define	HDA_REG_CORBUBASE 0x44

#define	HDA_REG_CORBWP 0x48

#define	HDA_REG_CORBRP 0x4a

#define	HDA_CORBRP_RST (1 << 15) /* read pointer reset */

#define	HDA_REG_CORBCTL 0x4c

#define	HDA_CORBCTL_RUN (1 << 1) /* enable DMA */

#define	HDA_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */

#define	HDA_REG_CORBSTS 0x4d

#define	HDA_CORBSTS_CMEI (1 << 0) /* memory error indication */

#define	HDA_REG_CORBSIZE 0x4e

#define	HDA_REG_RIRBLBASE 0x50

#define	HDA_REG_RIRBUBASE 0x54

#define	HDA_REG_RIRBWP 0x58

#define	HDA_RIRBWP_RST (1 << 15) /* write pointer reset */

#define	HDA_REG_RINTCNT 0x5a

#define	HDA_REG_RIRBCTL 0x5c

#define	HDA_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */

#define	HDA_RBCTL_DMA_EN (1 << 1) /* enable DMA */

#define	HDA_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */

#define	HDA_REG_RIRBSTS 0x5d

#define	HDA_RBSTS_IRQ (1 << 0) /* response irq */

#define	HDA_RBSTS_OVERRUN (1 << 2) /* overrun irq */

#define	HDA_REG_RIRBSIZE 0x5e

#define	HDA_REG_IC 0x60

#define	HDA_REG_IR 0x64

#define	HDA_REG_IRS 0x68

#define	HDA_IRS_VALID (1<<1)

#define	HDA_IRS_BUSY (1<<0)

#define	HDA_REG_DPLBASE 0x70

#define	HDA_REG_DPUBASE 0x74

#define	HDA_DPLBASE_ENABLE 0x1 /* Enable position buffer */

#define	HDA_REG_SD_CTL 0x00

#define	HDA_REG_SD_CTL_3B 0x02 /* 3rd byte of SD_CTL register */

#define	HDA_REG_SD_STS 0x03

#define	HDA_REG_SD_LPIB 0x04

#define	HDA_REG_SD_CBL 0x08

#define	HDA_REG_SD_LVI 0x0c

#define	HDA_REG_SD_FIFOW 0x0e

#define	HDA_REG_SD_FIFOSIZE 0x10

#define	HDA_REG_SD_FORMAT 0x12

#define	HDA_REG_SD_FIFOL 0x14

#define	HDA_REG_SD_BDLPL 0x18

#define	HDA_REG_SD_BDLPU 0x1c

#define	HDA_REG_SD_LPIBA 0x2004

#define	HDA_REG_LLCH 0x14

#define	HDA_REG_GTS_BASE 0x520

#define	HDA_REG_GTSCC (HDA_REG_GTS_BASE + 0x00)

#define	HDA_REG_WALFCC (HDA_REG_GTS_BASE + 0x04)

#define	HDA_REG_TSCCL (HDA_REG_GTS_BASE + 0x08)

#define	HDA_REG_TSCCU (HDA_REG_GTS_BASE + 0x0C)

#define	HDA_REG_LLPFOC (HDA_REG_GTS_BASE + 0x14)

#define	HDA_REG_LLPCL (HDA_REG_GTS_BASE + 0x18)

#define	HDA_REG_LLPCU (HDA_REG_GTS_BASE + 0x1C)

#define	HDA_REG_HSW_EM4 0x100c

#define	HDA_REG_HSW_EM5 0x1010

#define	HDA_REG_VS_EM1 0x1000

#define	HDA_REG_VS_INRC 0x1004

#define	HDA_REG_VS_OUTRC 0x1008

#define	HDA_REG_VS_FIFOTRK 0x100C

#define	HDA_REG_VS_FIFOTRK2 0x1010

#define	HDA_REG_VS_EM2 0x1030

#define	HDA_REG_VS_EM3L 0x1038

#define	HDA_REG_VS_EM3U 0x103C

#define	HDA_REG_VS_EM4L 0x1040

#define	HDA_REG_VS_EM4U 0x1044

#define	HDA_REG_VS_LTRP 0x1048

#define	HDA_REG_VS_D0I3C 0x104A

#define	HDA_REG_VS_PCE 0x104B

#define	HDA_REG_VS_L2MAGC 0x1050

#define	HDA_REG_VS_L2LAHPT 0x1054

#define	HDA_REG_VS_SDXDPIB_XBASE 0x1084

#define	HDA_REG_VS_SDXDPIB_XINTERVAL 0x20

#define	HDA_REG_VS_SDXEFIFOS_XBASE 0x1094

#define	HDA_REG_VS_SDXEFIFOS_XINTERVAL 0x20

#define	HDA_PCIREG_TCSEL 0x44

#define	BDL_SIZE 4096

#define	HDA_MAX_BDL_ENTRIES (BDL_SIZE / 16)

#define	HDA_MAX_BUF_SIZE (410241024)

#define	RIRB_INT_RESPONSE 0x01

#define	RIRB_INT_OVERRUN 0x04

#define	RIRB_INT_MASK 0x05

#define	STATESTS_INT_MASK ((1 << HDA_MAX_CODECS) - 1)

#define	SD_CTL_STREAM_RESET 0x01 /* stream reset bit */

#define	SD_CTL_DMA_START 0x02 /* stream DMA start bit */

#define	SD_CTL_STRIPE (3 << 16) /* stripe control */

#define	SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */

#define	SD_CTL_DIR (1 << 19) /* bi-directional stream */

#define	SD_CTL_STREAM_TAG_MASK (0xf << 20)

#define	SD_CTL_STREAM_TAG_SHIFT 20

#define	SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */

#define	SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */

#define	SD_INT_COMPLETE 0x04 /* completion interrupt */

#define	SD_INT_MASK

#define	SD_CTL_STRIPE_MASK 0x3 /* stripe control mask */

#define	SD_STS_FIFO_READY 0x20 /* FIFO ready */

#define	HDA_INT_ALL_STREAM 0xff /* all stream interrupts */

#define	HDA_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */

#define	HDA_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */

#define	HDA_MAX_CORB_ENTRIES 256

#define	HDA_MAX_RIRB_ENTRIES 256

#define	HDA_REG_CAP_HDR 0x0

#define	HDA_CAP_HDR_VER_OFF 28

#define	HDA_CAP_HDR_VER_MASK (0xF << HDA_CAP_HDR_VER_OFF)

#define	HDA_CAP_HDR_ID_OFF 16

#define	HDA_CAP_HDR_ID_MASK (0xFFF << HDA_CAP_HDR_ID_OFF)

#define	HDA_CAP_HDR_NXT_PTR_MASK 0xFFFF

#define	HDA_SPB_CAP_ID 0x4

#define	HDA_REG_SPB_BASE_ADDR 0x700

#define	HDA_REG_SPB_SPBFCH 0x00

#define	HDA_REG_SPB_SPBFCCTL 0x04

#define	HDA_SPB_BASE 0x08

#define	HDA_SPB_INTERVAL 0x08

#define	HDA_SPB_SPIB 0x00

#define	HDA_SPB_MAXFIFO 0x04

#define	HDA_GTS_CAP_ID 0x1

#define	HDA_REG_GTS_GTSCH 0x00

#define	HDA_REG_GTS_GTSCD 0x04

#define	HDA_REG_GTS_GTSCTLAC 0x0C

#define	HDA_GTS_BASE 0x20

#define	HDA_GTS_INTERVAL 0x20

#define	HDA_PP_CAP_ID 0x3

#define	HDA_REG_PP_PPCH 0x10

#define	HDA_REG_PP_PPCTL 0x04

#define	HDA_PPCTL_PIE (1<<31)

#define	HDA_PPCTL_GPROCEN (1<<30)

#define	HDA_PPCTL_PROCEN(_X_) (1<<(_X_))

#define	HDA_REG_PP_PPSTS 0x08

#define	HDA_PPHC_BASE 0x10

#define	HDA_PPHC_INTERVAL 0x10

#define	HDA_REG_PPHCLLPL 0x0

#define	HDA_REG_PPHCLLPU 0x4

#define	HDA_REG_PPHCLDPL 0x8

#define	HDA_REG_PPHCLDPU 0xC

#define	HDA_PPLC_BASE 0x10

#define	HDA_PPLC_MULTI 0x10

#define	HDA_PPLC_INTERVAL 0x10

#define	HDA_REG_PPLCCTL 0x0

#define	HDA_PPLCCTL_STRM_BITS 4

#define	HDA_PPLCCTL_STRM_SHIFT 20

#define	HDA_REG_MASK(bit_num, offset) (((1 << (bit_num)) - 1) << (offset))

#define	HDA_PPLCCTL_STRM_MASK HDA_REG_MASK(HDA_PPLCCTL_STRM_BITS, HDA_PPLCCTL_STRM_SHIFT)

#define	HDA_PPLCCTL_RUN (1<<1)

#define	HDA_PPLCCTL_STRST (1<<0)

#define	HDA_REG_PPLCFMT 0x4

#define	HDA_REG_PPLCLLPL 0x8

#define	HDA_REG_PPLCLLPU 0xC

#define	HDA_ML_CAP_ID 0x2

#define	HDA_REG_ML_MLCH 0x00

#define	HDA_REG_ML_MLCD 0x04

#define	HDA_ML_BASE 0x40

#define	HDA_ML_INTERVAL 0x40

#define	HDA_REG_ML_LCAP 0x00

#define	HDA_REG_ML_LCTL 0x04

#define	HDA_REG_ML_LOSIDV 0x08

#define	HDA_REG_ML_LSDIID 0x0C

#define	HDA_REG_ML_LPSOO 0x10

#define	HDA_REG_ML_LPSIO 0x12

#define	HDA_REG_ML_LWALFC 0x18

#define	HDA_REG_ML_LOUTPAY 0x20

#define	HDA_REG_ML_LINPAY 0x30

#define	ML_LOSIDV_STREAM_MASK 0xFFFE

#define	ML_LCTL_SCF_MASK 0xF

#define	HDA_MLCTL_SPA (0x1 << 16)

#define	HDA_MLCTL_CPA (0x1 << 23)

#define	HDA_MLCTL_SPA_SHIFT 16

#define	HDA_MLCTL_CPA_SHIFT 23

#define	HDA_DRSM_CAP_ID 0x5

#define	HDA_REG_DRSM_CTL 0x4

#define	HDA_DRSM_BASE 0x08

#define	HDA_DRSM_INTERVAL 0x08

#define	GTSCC_TSCCD_MASK 0x80000000

#define	GTSCC_TSCCD_SHIFT BIT(31)

#define	GTSCC_TSCCI_MASK 0x20

#define	GTSCC_CDMAS_DMA_DIR_SHIFT 4

#define	WALFCC_CIF_MASK 0x1FF

#define	WALFCC_FN_SHIFT 9

#define	HDA_CLK_CYCLES_PER_FRAME 512

#define	HDA_MAX_CYCLE_VALUE 499

#define	HDA_MAX_CYCLE_OFFSET 10

#define	HDA_MAX_CYCLE_READ_RETRY 10

#define	TSCCU_CCU_SHIFT 32

#define	LLPC_CCU_SHIFT 32

#define	INTEL_HDA_CGCTL 0x48

#define	INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)

#define	INTEL_SCH_HDA_DEVC 0x78

#define	INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)

#define	HDA_VS_EM2_DUM (1 << 23)

#define	ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42

#define	ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02

#define	NVIDIA_HDA_TRANSREG_ADDR 0x4e

#define	NVIDIA_HDA_ENABLE_COHBITS 0x0f

#define	NVIDIA_HDA_ISTRM_COH 0x4d

#define	NVIDIA_HDA_OSTRM_COH 0x4c

#define	NVIDIA_HDA_ENABLE_COHBIT 0x01

#define	INTEL_HDA_CGCTL 0x48

#define	INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)

#define	INTEL_SCH_HDA_DEVC 0x78

#define	INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)

Enumerations
enum	{ SDI0 , SDI1 , SDI2 , SDI3 , SDO0 , SDO1 , SDO2 , SDO3 }

Macro Definition Documentation

◆ ATI_SB450_HDAUDIO_ENABLE_SNOOP

#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02

Definition at line 308 of file hda_registers.h.

◆ ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR

#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42

Definition at line 307 of file hda_registers.h.

◆ BDL_SIZE

#define BDL_SIZE 4096

Definition at line 129 of file hda_registers.h.

◆ GTSCC_CDMAS_DMA_DIR_SHIFT

#define GTSCC_CDMAS_DMA_DIR_SHIFT 4

Definition at line 280 of file hda_registers.h.

◆ GTSCC_TSCCD_MASK

#define GTSCC_TSCCD_MASK 0x80000000

Definition at line 277 of file hda_registers.h.

◆ GTSCC_TSCCD_SHIFT

#define GTSCC_TSCCD_SHIFT BIT(31)

Definition at line 278 of file hda_registers.h.

◆ GTSCC_TSCCI_MASK

#define GTSCC_TSCCI_MASK 0x20

Definition at line 279 of file hda_registers.h.

◆ HDA_CAP_HDR_ID_MASK

#define HDA_CAP_HDR_ID_MASK (0xFFF << HDA_CAP_HDR_ID_OFF)

Definition at line 180 of file hda_registers.h.

◆ HDA_CAP_HDR_ID_OFF

#define HDA_CAP_HDR_ID_OFF 16

Definition at line 179 of file hda_registers.h.

◆ HDA_CAP_HDR_NXT_PTR_MASK

#define HDA_CAP_HDR_NXT_PTR_MASK 0xFFFF

Definition at line 181 of file hda_registers.h.

◆ HDA_CAP_HDR_VER_MASK

#define HDA_CAP_HDR_VER_MASK (0xF << HDA_CAP_HDR_VER_OFF)

Definition at line 178 of file hda_registers.h.

◆ HDA_CAP_HDR_VER_OFF

#define HDA_CAP_HDR_VER_OFF 28

Definition at line 177 of file hda_registers.h.

◆ HDA_CLK_CYCLES_PER_FRAME

#define HDA_CLK_CYCLES_PER_FRAME 512

Definition at line 284 of file hda_registers.h.

◆ HDA_CORBCTL_CMEIE

#define HDA_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */

Definition at line 36 of file hda_registers.h.

◆ HDA_CORBCTL_RUN

#define HDA_CORBCTL_RUN (1 << 1) /* enable DMA */

Definition at line 35 of file hda_registers.h.

◆ HDA_CORBRP_RST

#define HDA_CORBRP_RST (1 << 15) /* read pointer reset */

Definition at line 33 of file hda_registers.h.

◆ HDA_CORBSTS_CMEI

#define HDA_CORBSTS_CMEI (1 << 0) /* memory error indication */

Definition at line 38 of file hda_registers.h.

◆ HDA_DPLBASE_ENABLE

#define HDA_DPLBASE_ENABLE 0x1 /* Enable position buffer */

Definition at line 63 of file hda_registers.h.

◆ HDA_DRSM_BASE

#define HDA_DRSM_BASE 0x08

Definition at line 272 of file hda_registers.h.

◆ HDA_DRSM_CAP_ID

#define HDA_DRSM_CAP_ID 0x5

Definition at line 269 of file hda_registers.h.

◆ HDA_DRSM_INTERVAL

#define HDA_DRSM_INTERVAL 0x08

Definition at line 274 of file hda_registers.h.

◆ HDA_GCAP_64OK

#define HDA_GCAP_64OK (1 << 0) /* 64bit address support */

Definition at line 2 of file hda_registers.h.

◆ HDA_GCAP_BSS

#define HDA_GCAP_BSS (31 << 3) /* # of bidirectional streams */

Definition at line 4 of file hda_registers.h.

◆ HDA_GCAP_ISS

#define HDA_GCAP_ISS (15 << 8) /* # of input streams */

Definition at line 5 of file hda_registers.h.

◆ HDA_GCAP_NSDO

#define HDA_GCAP_NSDO (3 << 1) /* # of serial data out signals */

Definition at line 3 of file hda_registers.h.

◆ HDA_GCAP_OSS

#define HDA_GCAP_OSS (15 << 12) /* # of output streams */

Definition at line 6 of file hda_registers.h.

◆ HDA_GCTL_FCNTRL

#define HDA_GCTL_FCNTRL (1 << 1) /* flush control */

Definition at line 13 of file hda_registers.h.

◆ HDA_GCTL_RESET

#define HDA_GCTL_RESET (1 << 0) /* controller reset */

Definition at line 12 of file hda_registers.h.

◆ HDA_GCTL_UNSOL

#define HDA_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */

Definition at line 14 of file hda_registers.h.

◆ HDA_GSTS_FSTS

#define HDA_GSTS_FSTS (1 << 1) /* flush status */

Definition at line 18 of file hda_registers.h.

◆ HDA_GTS_BASE

#define HDA_GTS_BASE 0x20

Definition at line 202 of file hda_registers.h.

◆ HDA_GTS_CAP_ID

#define HDA_GTS_CAP_ID 0x1

Definition at line 198 of file hda_registers.h.

◆ HDA_GTS_INTERVAL

#define HDA_GTS_INTERVAL 0x20

Definition at line 203 of file hda_registers.h.

◆ HDA_INT_ALL_STREAM

#define HDA_INT_ALL_STREAM 0xff /* all stream interrupts */

Definition at line 167 of file hda_registers.h.

◆ HDA_INT_CTRL_EN

#define HDA_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */

Definition at line 168 of file hda_registers.h.

◆ HDA_INT_GLOBAL_EN

#define HDA_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */

Definition at line 169 of file hda_registers.h.

◆ HDA_IRS_BUSY

#define HDA_IRS_BUSY (1<<0)

Definition at line 59 of file hda_registers.h.

◆ HDA_IRS_VALID

#define HDA_IRS_VALID (1<<1)

Definition at line 58 of file hda_registers.h.

◆ HDA_MAX_BDL_ENTRIES

#define HDA_MAX_BDL_ENTRIES (BDL_SIZE / 16)

Definition at line 130 of file hda_registers.h.

◆ HDA_MAX_BUF_SIZE

#define HDA_MAX_BUF_SIZE (4*1024*1024)

Definition at line 136 of file hda_registers.h.

◆ HDA_MAX_CORB_ENTRIES

#define HDA_MAX_CORB_ENTRIES 256

Definition at line 172 of file hda_registers.h.

◆ HDA_MAX_CYCLE_OFFSET

#define HDA_MAX_CYCLE_OFFSET 10

Definition at line 292 of file hda_registers.h.

◆ HDA_MAX_CYCLE_READ_RETRY

#define HDA_MAX_CYCLE_READ_RETRY 10

Definition at line 293 of file hda_registers.h.

◆ HDA_MAX_CYCLE_VALUE

#define HDA_MAX_CYCLE_VALUE 499

Definition at line 291 of file hda_registers.h.

◆ HDA_MAX_RIRB_ENTRIES

#define HDA_MAX_RIRB_ENTRIES 256

Definition at line 173 of file hda_registers.h.

◆ HDA_ML_BASE

#define HDA_ML_BASE 0x40

Definition at line 246 of file hda_registers.h.

◆ HDA_ML_CAP_ID

#define HDA_ML_CAP_ID 0x2

Definition at line 243 of file hda_registers.h.

◆ HDA_ML_INTERVAL

#define HDA_ML_INTERVAL 0x40

Definition at line 247 of file hda_registers.h.

◆ HDA_MLCTL_CPA

#define HDA_MLCTL_CPA (0x1 << 23)

Definition at line 264 of file hda_registers.h.

◆ HDA_MLCTL_CPA_SHIFT

#define HDA_MLCTL_CPA_SHIFT 23

Definition at line 266 of file hda_registers.h.

◆ HDA_MLCTL_SPA

#define HDA_MLCTL_SPA (0x1 << 16)

Definition at line 263 of file hda_registers.h.

◆ HDA_MLCTL_SPA_SHIFT

#define HDA_MLCTL_SPA_SHIFT 16

Definition at line 265 of file hda_registers.h.

◆ HDA_PCIREG_TCSEL

#define HDA_PCIREG_TCSEL 0x44

Definition at line 122 of file hda_registers.h.

◆ HDA_PP_CAP_ID

#define HDA_PP_CAP_ID 0x3

Definition at line 206 of file hda_registers.h.

◆ HDA_PPCTL_GPROCEN

#define HDA_PPCTL_GPROCEN (1<<30)

Definition at line 210 of file hda_registers.h.

◆ HDA_PPCTL_PIE

#define HDA_PPCTL_PIE (1<<31)

Definition at line 209 of file hda_registers.h.

◆ HDA_PPCTL_PROCEN

#define HDA_PPCTL_PROCEN ( _X_ ) (1<<(_X_))

Definition at line 212 of file hda_registers.h.

◆ HDA_PPHC_BASE

#define HDA_PPHC_BASE 0x10

Definition at line 216 of file hda_registers.h.

◆ HDA_PPHC_INTERVAL

#define HDA_PPHC_INTERVAL 0x10

Definition at line 217 of file hda_registers.h.

◆ HDA_PPLC_BASE

#define HDA_PPLC_BASE 0x10

Definition at line 224 of file hda_registers.h.

◆ HDA_PPLC_INTERVAL

#define HDA_PPLC_INTERVAL 0x10

Definition at line 226 of file hda_registers.h.

◆ HDA_PPLC_MULTI

#define HDA_PPLC_MULTI 0x10

Definition at line 225 of file hda_registers.h.

◆ HDA_PPLCCTL_RUN

#define HDA_PPLCCTL_RUN (1<<1)

Definition at line 235 of file hda_registers.h.

◆ HDA_PPLCCTL_STRM_BITS

#define HDA_PPLCCTL_STRM_BITS 4

Definition at line 229 of file hda_registers.h.

◆ HDA_PPLCCTL_STRM_MASK

#define HDA_PPLCCTL_STRM_MASK HDA_REG_MASK(HDA_PPLCCTL_STRM_BITS, HDA_PPLCCTL_STRM_SHIFT)

Definition at line 233 of file hda_registers.h.

◆ HDA_PPLCCTL_STRM_SHIFT

#define HDA_PPLCCTL_STRM_SHIFT 20

Definition at line 230 of file hda_registers.h.

◆ HDA_PPLCCTL_STRST

#define HDA_PPLCCTL_STRST (1<<0)

Definition at line 236 of file hda_registers.h.

◆ HDA_RBCTL_DMA_EN

#define HDA_RBCTL_DMA_EN (1 << 1) /* enable DMA */

Definition at line 48 of file hda_registers.h.

◆ HDA_RBCTL_IRQ_EN

#define HDA_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */

Definition at line 47 of file hda_registers.h.

◆ HDA_RBCTL_OVERRUN_EN

#define HDA_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */

Definition at line 49 of file hda_registers.h.

◆ HDA_RBSTS_IRQ

#define HDA_RBSTS_IRQ (1 << 0) /* response irq */

Definition at line 51 of file hda_registers.h.

◆ HDA_RBSTS_OVERRUN

#define HDA_RBSTS_OVERRUN (1 << 2) /* overrun irq */

Definition at line 52 of file hda_registers.h.

◆ HDA_REG_CAP_HDR

#define HDA_REG_CAP_HDR 0x0

Definition at line 176 of file hda_registers.h.

◆ HDA_REG_CORBCTL

#define HDA_REG_CORBCTL 0x4c

Definition at line 34 of file hda_registers.h.

◆ HDA_REG_CORBLBASE

#define HDA_REG_CORBLBASE 0x40

Definition at line 29 of file hda_registers.h.

◆ HDA_REG_CORBRP

#define HDA_REG_CORBRP 0x4a

Definition at line 32 of file hda_registers.h.

◆ HDA_REG_CORBSIZE

#define HDA_REG_CORBSIZE 0x4e

Definition at line 39 of file hda_registers.h.

◆ HDA_REG_CORBSTS

#define HDA_REG_CORBSTS 0x4d

Definition at line 37 of file hda_registers.h.

◆ HDA_REG_CORBUBASE

#define HDA_REG_CORBUBASE 0x44

Definition at line 30 of file hda_registers.h.

◆ HDA_REG_CORBWP

#define HDA_REG_CORBWP 0x48

Definition at line 31 of file hda_registers.h.

◆ HDA_REG_DPLBASE

#define HDA_REG_DPLBASE 0x70

Definition at line 61 of file hda_registers.h.

◆ HDA_REG_DPUBASE

#define HDA_REG_DPUBASE 0x74

Definition at line 62 of file hda_registers.h.

◆ HDA_REG_DRSM_CTL

#define HDA_REG_DRSM_CTL 0x4

Definition at line 270 of file hda_registers.h.

◆ HDA_REG_GCAP

#define HDA_REG_GCAP 0x00

Definition at line 1 of file hda_registers.h.

◆ HDA_REG_GCAP2

#define HDA_REG_GCAP2 0x12

Definition at line 19 of file hda_registers.h.

◆ HDA_REG_GCTL

#define HDA_REG_GCTL 0x08

Definition at line 11 of file hda_registers.h.

◆ HDA_REG_GSTS

#define HDA_REG_GSTS 0x10

Definition at line 17 of file hda_registers.h.

◆ HDA_REG_GTS_BASE

#define HDA_REG_GTS_BASE 0x520

Definition at line 86 of file hda_registers.h.

◆ HDA_REG_GTS_GTSCD

#define HDA_REG_GTS_GTSCD 0x04

Definition at line 200 of file hda_registers.h.

◆ HDA_REG_GTS_GTSCH

#define HDA_REG_GTS_GTSCH 0x00

Definition at line 199 of file hda_registers.h.

◆ HDA_REG_GTS_GTSCTLAC

#define HDA_REG_GTS_GTSCTLAC 0x0C

Definition at line 201 of file hda_registers.h.

◆ HDA_REG_GTSCC

#define HDA_REG_GTSCC (HDA_REG_GTS_BASE + 0x00)

Definition at line 88 of file hda_registers.h.

◆ HDA_REG_HSW_EM4

#define HDA_REG_HSW_EM4 0x100c

Definition at line 97 of file hda_registers.h.

◆ HDA_REG_HSW_EM5

#define HDA_REG_HSW_EM5 0x1010

Definition at line 98 of file hda_registers.h.

◆ HDA_REG_IC

#define HDA_REG_IC 0x60

Definition at line 55 of file hda_registers.h.

◆ HDA_REG_INPAY

#define HDA_REG_INPAY 0x06

Definition at line 10 of file hda_registers.h.

◆ HDA_REG_INSTRMPAY

#define HDA_REG_INSTRMPAY 0x1A

Definition at line 22 of file hda_registers.h.

◆ HDA_REG_INTCTL

#define HDA_REG_INTCTL 0x20

Definition at line 23 of file hda_registers.h.

◆ HDA_REG_INTSTS

#define HDA_REG_INTSTS 0x24

Definition at line 24 of file hda_registers.h.

◆ HDA_REG_IR

#define HDA_REG_IR 0x64

Definition at line 56 of file hda_registers.h.

◆ HDA_REG_IRS

#define HDA_REG_IRS 0x68

Definition at line 57 of file hda_registers.h.

◆ HDA_REG_LLCH [1/2]

#define HDA_REG_LLCH 0x14

Definition at line 84 of file hda_registers.h.

◆ HDA_REG_LLCH [2/2]

#define HDA_REG_LLCH 0x14

Definition at line 84 of file hda_registers.h.

◆ HDA_REG_LLPCL

#define HDA_REG_LLPCL (HDA_REG_GTS_BASE + 0x18)

Definition at line 93 of file hda_registers.h.

◆ HDA_REG_LLPCU

#define HDA_REG_LLPCU (HDA_REG_GTS_BASE + 0x1C)

Definition at line 94 of file hda_registers.h.

◆ HDA_REG_LLPFOC

#define HDA_REG_LLPFOC (HDA_REG_GTS_BASE + 0x14)

Definition at line 92 of file hda_registers.h.

◆ HDA_REG_MASK

#define HDA_REG_MASK	(	bit_num,
		offset
	)	(((1 << (bit_num)) - 1) << (offset))

Definition at line 231 of file hda_registers.h.

◆ HDA_REG_ML_LCAP

#define HDA_REG_ML_LCAP 0x00

Definition at line 249 of file hda_registers.h.

◆ HDA_REG_ML_LCTL

#define HDA_REG_ML_LCTL 0x04

Definition at line 250 of file hda_registers.h.

◆ HDA_REG_ML_LINPAY

#define HDA_REG_ML_LINPAY 0x30

Definition at line 257 of file hda_registers.h.

◆ HDA_REG_ML_LOSIDV

#define HDA_REG_ML_LOSIDV 0x08

Definition at line 251 of file hda_registers.h.

◆ HDA_REG_ML_LOUTPAY

#define HDA_REG_ML_LOUTPAY 0x20

Definition at line 256 of file hda_registers.h.

◆ HDA_REG_ML_LPSIO

#define HDA_REG_ML_LPSIO 0x12

Definition at line 254 of file hda_registers.h.

◆ HDA_REG_ML_LPSOO

#define HDA_REG_ML_LPSOO 0x10

Definition at line 253 of file hda_registers.h.

◆ HDA_REG_ML_LSDIID

#define HDA_REG_ML_LSDIID 0x0C

Definition at line 252 of file hda_registers.h.

◆ HDA_REG_ML_LWALFC

#define HDA_REG_ML_LWALFC 0x18

Definition at line 255 of file hda_registers.h.

◆ HDA_REG_ML_MLCD

#define HDA_REG_ML_MLCD 0x04

Definition at line 245 of file hda_registers.h.

◆ HDA_REG_ML_MLCH

#define HDA_REG_ML_MLCH 0x00

Definition at line 244 of file hda_registers.h.

◆ HDA_REG_OLD_SSYNC

#define HDA_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */

Definition at line 27 of file hda_registers.h.

◆ HDA_REG_OUTPAY

#define HDA_REG_OUTPAY 0x04

Definition at line 9 of file hda_registers.h.

◆ HDA_REG_OUTSTRMPAY

#define HDA_REG_OUTSTRMPAY 0x18

Definition at line 21 of file hda_registers.h.

◆ HDA_REG_PP_PPCH

#define HDA_REG_PP_PPCH 0x10

Definition at line 207 of file hda_registers.h.

◆ HDA_REG_PP_PPCTL

#define HDA_REG_PP_PPCTL 0x04

Definition at line 208 of file hda_registers.h.

◆ HDA_REG_PP_PPSTS

#define HDA_REG_PP_PPSTS 0x08

Definition at line 214 of file hda_registers.h.

◆ HDA_REG_PPHCLDPL

#define HDA_REG_PPHCLDPL 0x8

Definition at line 221 of file hda_registers.h.

◆ HDA_REG_PPHCLDPU

#define HDA_REG_PPHCLDPU 0xC

Definition at line 222 of file hda_registers.h.

◆ HDA_REG_PPHCLLPL

#define HDA_REG_PPHCLLPL 0x0

Definition at line 219 of file hda_registers.h.

◆ HDA_REG_PPHCLLPU

#define HDA_REG_PPHCLLPU 0x4

Definition at line 220 of file hda_registers.h.

◆ HDA_REG_PPLCCTL

#define HDA_REG_PPLCCTL 0x0

Definition at line 228 of file hda_registers.h.

◆ HDA_REG_PPLCFMT

#define HDA_REG_PPLCFMT 0x4

Definition at line 238 of file hda_registers.h.

◆ HDA_REG_PPLCLLPL

#define HDA_REG_PPLCLLPL 0x8

Definition at line 239 of file hda_registers.h.

◆ HDA_REG_PPLCLLPU

#define HDA_REG_PPLCLLPU 0xC

Definition at line 240 of file hda_registers.h.

◆ HDA_REG_RINTCNT

#define HDA_REG_RINTCNT 0x5a

Definition at line 45 of file hda_registers.h.

◆ HDA_REG_RIRBCTL

#define HDA_REG_RIRBCTL 0x5c

Definition at line 46 of file hda_registers.h.

◆ HDA_REG_RIRBLBASE

#define HDA_REG_RIRBLBASE 0x50

Definition at line 41 of file hda_registers.h.

◆ HDA_REG_RIRBSIZE

#define HDA_REG_RIRBSIZE 0x5e

Definition at line 53 of file hda_registers.h.

◆ HDA_REG_RIRBSTS

#define HDA_REG_RIRBSTS 0x5d

Definition at line 50 of file hda_registers.h.

◆ HDA_REG_RIRBUBASE

#define HDA_REG_RIRBUBASE 0x54

Definition at line 42 of file hda_registers.h.

◆ HDA_REG_RIRBWP

#define HDA_REG_RIRBWP 0x58

Definition at line 43 of file hda_registers.h.

◆ HDA_REG_SD_BDLPL

#define HDA_REG_SD_BDLPL 0x18

Definition at line 79 of file hda_registers.h.

◆ HDA_REG_SD_BDLPU

#define HDA_REG_SD_BDLPU 0x1c

Definition at line 80 of file hda_registers.h.

◆ HDA_REG_SD_CBL

#define HDA_REG_SD_CBL 0x08

Definition at line 73 of file hda_registers.h.

◆ HDA_REG_SD_CTL

#define HDA_REG_SD_CTL 0x00

Definition at line 69 of file hda_registers.h.

◆ HDA_REG_SD_CTL_3B

#define HDA_REG_SD_CTL_3B 0x02 /* 3rd byte of SD_CTL register */

Definition at line 70 of file hda_registers.h.

◆ HDA_REG_SD_FIFOL

#define HDA_REG_SD_FIFOL 0x14

Definition at line 78 of file hda_registers.h.

◆ HDA_REG_SD_FIFOSIZE

#define HDA_REG_SD_FIFOSIZE 0x10

Definition at line 76 of file hda_registers.h.

◆ HDA_REG_SD_FIFOW

#define HDA_REG_SD_FIFOW 0x0e

Definition at line 75 of file hda_registers.h.

◆ HDA_REG_SD_FORMAT

#define HDA_REG_SD_FORMAT 0x12

Definition at line 77 of file hda_registers.h.

◆ HDA_REG_SD_LPIB

#define HDA_REG_SD_LPIB 0x04

Definition at line 72 of file hda_registers.h.

◆ HDA_REG_SD_LPIBA

#define HDA_REG_SD_LPIBA 0x2004

Definition at line 81 of file hda_registers.h.

◆ HDA_REG_SD_LVI

#define HDA_REG_SD_LVI 0x0c

Definition at line 74 of file hda_registers.h.

◆ HDA_REG_SD_STS

#define HDA_REG_SD_STS 0x03

Definition at line 71 of file hda_registers.h.

◆ HDA_REG_SPB_BASE_ADDR

#define HDA_REG_SPB_BASE_ADDR 0x700

Definition at line 185 of file hda_registers.h.

◆ HDA_REG_SPB_SPBFCCTL

#define HDA_REG_SPB_SPBFCCTL 0x04

Definition at line 187 of file hda_registers.h.

◆ HDA_REG_SPB_SPBFCH

#define HDA_REG_SPB_SPBFCH 0x00

Definition at line 186 of file hda_registers.h.

◆ HDA_REG_SSYNC

#define HDA_REG_SSYNC 0x38

Definition at line 28 of file hda_registers.h.

◆ HDA_REG_STATESTS

#define HDA_REG_STATESTS 0x0e

Definition at line 16 of file hda_registers.h.

◆ HDA_REG_TSCCL

#define HDA_REG_TSCCL (HDA_REG_GTS_BASE + 0x08)

Definition at line 90 of file hda_registers.h.

◆ HDA_REG_TSCCU

#define HDA_REG_TSCCU (HDA_REG_GTS_BASE + 0x0C)

Definition at line 91 of file hda_registers.h.

◆ HDA_REG_VMAJ

#define HDA_REG_VMAJ 0x03

Definition at line 8 of file hda_registers.h.

◆ HDA_REG_VMIN

#define HDA_REG_VMIN 0x02

Definition at line 7 of file hda_registers.h.

◆ HDA_REG_VS_D0I3C

#define HDA_REG_VS_D0I3C 0x104A

Definition at line 112 of file hda_registers.h.

◆ HDA_REG_VS_EM1

#define HDA_REG_VS_EM1 0x1000

Definition at line 101 of file hda_registers.h.

◆ HDA_REG_VS_EM2

#define HDA_REG_VS_EM2 0x1030

Definition at line 106 of file hda_registers.h.

◆ HDA_REG_VS_EM3L

#define HDA_REG_VS_EM3L 0x1038

Definition at line 107 of file hda_registers.h.

◆ HDA_REG_VS_EM3U

#define HDA_REG_VS_EM3U 0x103C

Definition at line 108 of file hda_registers.h.

◆ HDA_REG_VS_EM4L

#define HDA_REG_VS_EM4L 0x1040

Definition at line 109 of file hda_registers.h.

◆ HDA_REG_VS_EM4U

#define HDA_REG_VS_EM4U 0x1044

Definition at line 110 of file hda_registers.h.

◆ HDA_REG_VS_FIFOTRK

#define HDA_REG_VS_FIFOTRK 0x100C

Definition at line 104 of file hda_registers.h.

◆ HDA_REG_VS_FIFOTRK2

#define HDA_REG_VS_FIFOTRK2 0x1010

Definition at line 105 of file hda_registers.h.

◆ HDA_REG_VS_INRC

#define HDA_REG_VS_INRC 0x1004

Definition at line 102 of file hda_registers.h.

◆ HDA_REG_VS_L2LAHPT

#define HDA_REG_VS_L2LAHPT 0x1054

Definition at line 115 of file hda_registers.h.

◆ HDA_REG_VS_L2MAGC

#define HDA_REG_VS_L2MAGC 0x1050

Definition at line 114 of file hda_registers.h.

◆ HDA_REG_VS_LTRP

#define HDA_REG_VS_LTRP 0x1048

Definition at line 111 of file hda_registers.h.

◆ HDA_REG_VS_OUTRC

#define HDA_REG_VS_OUTRC 0x1008

Definition at line 103 of file hda_registers.h.

◆ HDA_REG_VS_PCE

#define HDA_REG_VS_PCE 0x104B

Definition at line 113 of file hda_registers.h.

◆ HDA_REG_VS_SDXDPIB_XBASE

#define HDA_REG_VS_SDXDPIB_XBASE 0x1084

Definition at line 116 of file hda_registers.h.

◆ HDA_REG_VS_SDXDPIB_XINTERVAL

#define HDA_REG_VS_SDXDPIB_XINTERVAL 0x20

Definition at line 117 of file hda_registers.h.

◆ HDA_REG_VS_SDXEFIFOS_XBASE

#define HDA_REG_VS_SDXEFIFOS_XBASE 0x1094

Definition at line 118 of file hda_registers.h.

◆ HDA_REG_VS_SDXEFIFOS_XINTERVAL

#define HDA_REG_VS_SDXEFIFOS_XINTERVAL 0x20

Definition at line 119 of file hda_registers.h.

◆ HDA_REG_WAKEEN

#define HDA_REG_WAKEEN 0x0c

Definition at line 15 of file hda_registers.h.

◆ HDA_REG_WALFCC

#define HDA_REG_WALFCC (HDA_REG_GTS_BASE + 0x04)

Definition at line 89 of file hda_registers.h.

◆ HDA_REG_WALLCLK

#define HDA_REG_WALLCLK 0x30 /* 24Mhz source */

Definition at line 25 of file hda_registers.h.

◆ HDA_REG_WALLCLKA

#define HDA_REG_WALLCLKA 0x2030 /* 24Mhz source */

Definition at line 26 of file hda_registers.h.

◆ HDA_RIRBWP_RST

#define HDA_RIRBWP_RST (1 << 15) /* write pointer reset */

Definition at line 44 of file hda_registers.h.

◆ HDA_SPB_BASE

#define HDA_SPB_BASE 0x08

Definition at line 189 of file hda_registers.h.

◆ HDA_SPB_CAP_ID

#define HDA_SPB_CAP_ID 0x4

Definition at line 184 of file hda_registers.h.

◆ HDA_SPB_INTERVAL

#define HDA_SPB_INTERVAL 0x08

Definition at line 191 of file hda_registers.h.

◆ HDA_SPB_MAXFIFO

#define HDA_SPB_MAXFIFO 0x04

Definition at line 195 of file hda_registers.h.

◆ HDA_SPB_SPIB

#define HDA_SPB_SPIB 0x00

Definition at line 193 of file hda_registers.h.

◆ HDA_VS_EM2_DUM

#define HDA_VS_EM2_DUM (1 << 23)

Definition at line 304 of file hda_registers.h.

◆ INTEL_HDA_CGCTL [1/2]

#define INTEL_HDA_CGCTL 0x48

Definition at line 318 of file hda_registers.h.

◆ INTEL_HDA_CGCTL [2/2]

#define INTEL_HDA_CGCTL 0x48

Definition at line 318 of file hda_registers.h.

◆ INTEL_HDA_CGCTL_MISCBDCGE [1/2]

#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)

Definition at line 319 of file hda_registers.h.

◆ INTEL_HDA_CGCTL_MISCBDCGE [2/2]

#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)

Definition at line 319 of file hda_registers.h.

◆ INTEL_SCH_HDA_DEVC [1/2]

#define INTEL_SCH_HDA_DEVC 0x78

Definition at line 320 of file hda_registers.h.

◆ INTEL_SCH_HDA_DEVC [2/2]

#define INTEL_SCH_HDA_DEVC 0x78

Definition at line 320 of file hda_registers.h.

◆ INTEL_SCH_HDA_DEVC_NOSNOOP [1/2]

#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)

Definition at line 321 of file hda_registers.h.

◆ INTEL_SCH_HDA_DEVC_NOSNOOP [2/2]

#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)

Definition at line 321 of file hda_registers.h.

◆ LLPC_CCU_SHIFT

#define LLPC_CCU_SHIFT 32

Definition at line 296 of file hda_registers.h.

◆ ML_LCTL_SCF_MASK

#define ML_LCTL_SCF_MASK 0xF

Definition at line 262 of file hda_registers.h.

◆ ML_LOSIDV_STREAM_MASK

#define ML_LOSIDV_STREAM_MASK 0xFFFE

Definition at line 260 of file hda_registers.h.

◆ NVIDIA_HDA_ENABLE_COHBIT

#define NVIDIA_HDA_ENABLE_COHBIT 0x01

Definition at line 315 of file hda_registers.h.

◆ NVIDIA_HDA_ENABLE_COHBITS

#define NVIDIA_HDA_ENABLE_COHBITS 0x0f

Definition at line 312 of file hda_registers.h.

◆ NVIDIA_HDA_ISTRM_COH

#define NVIDIA_HDA_ISTRM_COH 0x4d

Definition at line 313 of file hda_registers.h.

◆ NVIDIA_HDA_OSTRM_COH

#define NVIDIA_HDA_OSTRM_COH 0x4c

Definition at line 314 of file hda_registers.h.

◆ NVIDIA_HDA_TRANSREG_ADDR

#define NVIDIA_HDA_TRANSREG_ADDR 0x4e

Definition at line 311 of file hda_registers.h.

◆ RIRB_INT_MASK

#define RIRB_INT_MASK 0x05

Definition at line 141 of file hda_registers.h.

◆ RIRB_INT_OVERRUN

#define RIRB_INT_OVERRUN 0x04

Definition at line 140 of file hda_registers.h.

◆ RIRB_INT_RESPONSE

#define RIRB_INT_RESPONSE 0x01

Definition at line 139 of file hda_registers.h.

◆ SD_CTL_DIR

#define SD_CTL_DIR (1 << 19) /* bi-directional stream */

Definition at line 151 of file hda_registers.h.

◆ SD_CTL_DMA_START

#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */

Definition at line 148 of file hda_registers.h.

◆ SD_CTL_STREAM_RESET

#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */

Definition at line 147 of file hda_registers.h.

◆ SD_CTL_STREAM_TAG_MASK

#define SD_CTL_STREAM_TAG_MASK (0xf << 20)

Definition at line 152 of file hda_registers.h.

◆ SD_CTL_STREAM_TAG_SHIFT

#define SD_CTL_STREAM_TAG_SHIFT 20

Definition at line 153 of file hda_registers.h.

◆ SD_CTL_STRIPE

#define SD_CTL_STRIPE (3 << 16) /* stripe control */

Definition at line 149 of file hda_registers.h.

◆ SD_CTL_STRIPE_MASK

#define SD_CTL_STRIPE_MASK 0x3 /* stripe control mask */

Definition at line 161 of file hda_registers.h.

◆ SD_CTL_TRAFFIC_PRIO

#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */

Definition at line 150 of file hda_registers.h.

◆ SD_INT_COMPLETE

#define SD_INT_COMPLETE 0x04 /* completion interrupt */

Definition at line 158 of file hda_registers.h.

◆ SD_INT_DESC_ERR

#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */

Definition at line 156 of file hda_registers.h.

◆ SD_INT_FIFO_ERR

#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */

Definition at line 157 of file hda_registers.h.

◆ SD_INT_MASK

#define SD_INT_MASK

Value:

(SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\

SD_INT_COMPLETE)

SD_INT_COMPLETE

#define SD_INT_COMPLETE

Definition: hda_registers.h:158

SD_INT_DESC_ERR

#define SD_INT_DESC_ERR

Definition: hda_registers.h:156

SD_INT_FIFO_ERR

#define SD_INT_FIFO_ERR

Definition: hda_registers.h:157

Definition at line 159 of file hda_registers.h.

◆ SD_STS_FIFO_READY

#define SD_STS_FIFO_READY 0x20 /* FIFO ready */

Definition at line 164 of file hda_registers.h.

◆ STATESTS_INT_MASK

#define STATESTS_INT_MASK ((1 << HDA_MAX_CODECS) - 1)

Definition at line 144 of file hda_registers.h.

◆ TSCCU_CCU_SHIFT

#define TSCCU_CCU_SHIFT 32

Definition at line 295 of file hda_registers.h.

◆ WALFCC_CIF_MASK

#define WALFCC_CIF_MASK 0x1FF

Definition at line 282 of file hda_registers.h.

◆ WALFCC_FN_SHIFT

#define WALFCC_FN_SHIFT 9

Definition at line 283 of file hda_registers.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
SDI0
SDI1
SDI2
SDI3
SDO0
SDO1
SDO2
SDO3

Definition at line 66 of file hda_registers.h.

66{ SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };

SDI3

@ SDI3

Definition: hda_registers.h:66

SDO0

@ SDO0

Definition: hda_registers.h:66

SDI0

@ SDI0

Definition: hda_registers.h:66

SDO3

@ SDO3

Definition: hda_registers.h:66

SDI2

@ SDI2

Definition: hda_registers.h:66

SDI1

@ SDI1

Definition: hda_registers.h:66

SDO1

@ SDO1

Definition: hda_registers.h:66

SDO2

@ SDO2

Definition: hda_registers.h:66

Macros

Enumerations

Macro Definition Documentation

◆ ATI_SB450_HDAUDIO_ENABLE_SNOOP

◆ ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR

◆ BDL_SIZE

◆ GTSCC_CDMAS_DMA_DIR_SHIFT

◆ GTSCC_TSCCD_MASK

◆ GTSCC_TSCCD_SHIFT

◆ GTSCC_TSCCI_MASK

◆ HDA_CAP_HDR_ID_MASK

◆ HDA_CAP_HDR_ID_OFF

◆ HDA_CAP_HDR_NXT_PTR_MASK

◆ HDA_CAP_HDR_VER_MASK

◆ HDA_CAP_HDR_VER_OFF

◆ HDA_CLK_CYCLES_PER_FRAME

◆ HDA_CORBCTL_CMEIE

◆ HDA_CORBCTL_RUN

◆ HDA_CORBRP_RST

◆ HDA_CORBSTS_CMEI

◆ HDA_DPLBASE_ENABLE

◆ HDA_DRSM_BASE

◆ HDA_DRSM_CAP_ID

◆ HDA_DRSM_INTERVAL

◆ HDA_GCAP_64OK

◆ HDA_GCAP_BSS

◆ HDA_GCAP_ISS

◆ HDA_GCAP_NSDO

◆ HDA_GCAP_OSS

◆ HDA_GCTL_FCNTRL

◆ HDA_GCTL_RESET

◆ HDA_GCTL_UNSOL

◆ HDA_GSTS_FSTS

◆ HDA_GTS_BASE

◆ HDA_GTS_CAP_ID

◆ HDA_GTS_INTERVAL

◆ HDA_INT_ALL_STREAM

◆ HDA_INT_CTRL_EN

◆ HDA_INT_GLOBAL_EN

◆ HDA_IRS_BUSY

◆ HDA_IRS_VALID

◆ HDA_MAX_BDL_ENTRIES

◆ HDA_MAX_BUF_SIZE

◆ HDA_MAX_CORB_ENTRIES

◆ HDA_MAX_CYCLE_OFFSET

◆ HDA_MAX_CYCLE_READ_RETRY

◆ HDA_MAX_CYCLE_VALUE

◆ HDA_MAX_RIRB_ENTRIES

◆ HDA_ML_BASE

◆ HDA_ML_CAP_ID

◆ HDA_ML_INTERVAL

◆ HDA_MLCTL_CPA

◆ HDA_MLCTL_CPA_SHIFT

◆ HDA_MLCTL_SPA

◆ HDA_MLCTL_SPA_SHIFT

◆ HDA_PCIREG_TCSEL

◆ HDA_PP_CAP_ID

◆ HDA_PPCTL_GPROCEN

◆ HDA_PPCTL_PIE

◆ HDA_PPCTL_PROCEN

◆ HDA_PPHC_BASE

◆ HDA_PPHC_INTERVAL

◆ HDA_PPLC_BASE

◆ HDA_PPLC_INTERVAL

◆ HDA_PPLC_MULTI

◆ HDA_PPLCCTL_RUN

◆ HDA_PPLCCTL_STRM_BITS

◆ HDA_PPLCCTL_STRM_MASK

◆ HDA_PPLCCTL_STRM_SHIFT

◆ HDA_PPLCCTL_STRST

◆ HDA_RBCTL_DMA_EN

◆ HDA_RBCTL_IRQ_EN

◆ HDA_RBCTL_OVERRUN_EN

◆ HDA_RBSTS_IRQ

◆ HDA_RBSTS_OVERRUN

◆ HDA_REG_CAP_HDR

◆ HDA_REG_CORBCTL

◆ HDA_REG_CORBLBASE

◆ HDA_REG_CORBRP

◆ HDA_REG_CORBSIZE