ReactOS  0.4.14-dev-838-g99f979d
hardware.h
Go to the documentation of this file.
1 /*
2  * PROJECT: ReactOS USB UHCI Miniport Driver
3  * LICENSE: GPL-2.0+ (https://spdx.org/licenses/GPL-2.0+)
4  * PURPOSE: USBUHCI hardware declarations
5  * COPYRIGHT: Copyright 2017-2018 Vadim Galyant <vgal@rambler.ru>
6  */
7 
8 #define UHCI_FRAME_LIST_MAX_ENTRIES 1024 // Number of frames in Frame List
9 #define UHCI_NUM_ROOT_HUB_PORTS 2
10 
11 /* UHCI HC I/O Registers offset (PUSHORT) */
12 #define UHCI_USBCMD 0 // USB Command R/W
13 #define UHCI_USBSTS 1 // USB Status R/WC
14 #define UHCI_USBINTR 2 // USB Interrupt Enable R/W
15 #define UHCI_FRNUM 3 // Frame Number R/W WORD writeable only
16 #define UHCI_FRBASEADD 4 // Frame List Base Address R/W // 32 bit
17 #define UHCI_SOFMOD 6 // Start Of Frame Modify R/W // 8 bit
18 #define UHCI_PORTSC1 8 // Port 1 Status/Control R/WC WORD writeable only
19 #define UHCI_PORTSC2 9 // Port 2 Status/Control R/WC WORD writeable only
20 
21 /* PCI Legacy Support */
22 #define PCI_LEGSUP 0xC0 // Legacy Support register offset. R/WC
23 #define PCI_LEGSUP_USBPIRQDEN 0x2000
24 #define PCI_LEGSUP_CLEAR_SMI 0x8F00
25 
26 /* LEGSUP Legacy support register (PCI Configuration - Function 2) */
27 typedef union _UHCI_PCI_LEGSUP {
28  struct {
29  USHORT Smi60Read : 1; // (60REN) Trap/SMI On 60h Read Enable. R/W.
30  USHORT Smi60Write : 1; // (60WEN) Trap/SMI On 60h Write Enable. R/W.
31  USHORT Smi64Read : 1; // (64REN) Trap/SMI On 64h Read Enable. R/W.
32  USHORT Smi64Write : 1; // (64WEN) Trap/SMI On 64h Write Enable. R/W.
33  USHORT SmiIrq : 1; // (USBSMIEN) Trap/SMI ON IRQ Enable. R/W.
34  USHORT A20Gate : 1; // (A20PTEN) A20Gate Pass Through Enable. R/W.
35  USHORT PassThroughStatus : 1; // (PSS) Pass Through Status. RO.
36  USHORT SmiEndPassThrough : 1; // (SMIEPTE) SMI At End Of Pass Through Enable. R/W.
37  USHORT TrapBy60ReadStatus : 1; // (TBY60R) Trap By 60h Read Status. R/WC.
38  USHORT TrapBy60WriteStatus : 1; // (TBY60W) Trap By 60h Write Status. R/WC.
39  USHORT TrapBy64ReadStatus : 1; // (TBY64R) Trap By 64h Read Status. R/WC.
40  USHORT TrapBy64WriteStatus : 1; // (TBY64W) Trap By 64h Write Status. R/WC.
41  USHORT UsbIrqStatus : 1; // (USBIRQS) USB IRQ Status. RO.
42  USHORT UsbPIRQ : 1; // (USBPIRQDEN) USB PIRQ Enable. R/W.
44  USHORT EndA20GateStatus : 1; // (A20PTS) End OF A20GATE Pass Through Status. R/WC.
45  };
48 
49 C_ASSERT(sizeof(UHCI_PCI_LEGSUP) == sizeof(USHORT));
50 
51 /* USBCMD Command register */
52 typedef union _UHCI_USB_COMMAND {
53  struct {
54  USHORT Run : 1;
58  USHORT GlobalResume : 1; // Force Global Resume
59  USHORT SoftwareDebug : 1; // 0 - Normal Mode, 1 - Debug mode
60  USHORT ConfigureFlag : 1; // no effect on the hardware
61  USHORT MaxPacket : 1; // 0 = 32, 1 = 64
63  };
66 
67 C_ASSERT(sizeof(UHCI_USB_COMMAND) == sizeof(USHORT));
68 
69 /* USBSTS Status register */
70 #define UHCI_USB_STATUS_MASK 0x3F
71 
72 typedef union _UHCI_USB_STATUS {
73  struct {
74  USHORT Interrupt : 1; // due to IOC (Interrupt On Complete)
75  USHORT ErrorInterrupt : 1; // due to error
77  USHORT HostSystemError : 1; // PCI problems
78  USHORT HcProcessError : 1; // Schedule is buggy
81  };
84 
85 C_ASSERT(sizeof(UHCI_USB_STATUS) == sizeof(USHORT));
86 
87 /* USBINTR Interrupt enable register */
88 typedef union _UHCI_INTERRUPT_ENABLE {
89  struct {
90  USHORT TimeoutCRC : 1; // Timeout/CRC error enable
95  };
98 
99 C_ASSERT(sizeof(UHCI_INTERRUPT_ENABLE) == sizeof(USHORT));
100 
101 /* FRNUM Frame Number register */
102 #define UHCI_FRNUM_FRAME_MASK 0x7FF
103 #define UHCI_FRNUM_INDEX_MASK 0x3FF
104 #define UHCI_FRNUM_OVERFLOW_LIST 0x400
105 
106 /* PORTSC(1|2) USB port status and control registers */
108  struct {
113  USHORT LineStatus : 2; // D+ and D-
115  USHORT Reserved1 : 1; // always 1
116  USHORT LowSpeedDevice : 1; // LS device Attached
118  USHORT Reserved2 : 2; // Intel use it (not UHCI 1.1d spec)
120  USHORT Reserved3 : 3; // write zeroes
121  };
124 
125 C_ASSERT(sizeof(UHCI_PORT_STATUS_CONTROL) == sizeof(USHORT));
126 
127 typedef struct _UHCI_HW_REGISTERS {
131  USHORT FrameNumber; // R/W WORD writeable only
137 
138 /* Transfer Descriptor (TD) */
139 #define UHCI_TD_STS_ACTIVE (1 << 7)
140 #define UHCI_TD_STS_STALLED (1 << 6)
141 #define UHCI_TD_STS_DATA_BUFFER_ERROR (1 << 5)
142 #define UHCI_TD_STS_BABBLE_DETECTED (1 << 4)
143 #define UHCI_TD_STS_NAK_RECEIVED (1 << 3)
144 #define UHCI_TD_STS_TIMEOUT_CRC_ERROR (1 << 2)
145 #define UHCI_TD_STS_BITSTUFF_ERROR (1 << 1)
146 //#define UHCI_TD_STS_Reserved (1 << 0)
147 
148 #define UHCI_TD_VALID_LENGTH 0x4FF
149 #define UHCI_TD_LENGTH_INVALID 0x7FE
150 #define UHCI_TD_LENGTH_NULL 0x7FF
151 
152 typedef union _UHCI_CONTROL_STATUS {
153  struct {
154  ULONG ActualLength : 11; // encoded as n - 1
156  ULONG Status : 8; // UHCI_TD_STS_ xxx
163  };
166 
167 C_ASSERT(sizeof(UHCI_CONTROL_STATUS) == sizeof(ULONG));
168 
169 #define UHCI_TD_PID_IN 0x69
170 #define UHCI_TD_PID_OUT 0xE1
171 #define UHCI_TD_PID_SETUP 0x2D
172 
173 #define UHCI_TD_PID_DATA0 0
174 #define UHCI_TD_PID_DATA1 1
175 
176 typedef union _UHCI_TD_TOKEN {
177  struct {
184  };
186 } UHCI_TD_TOKEN;
187 
188 C_ASSERT(sizeof(UHCI_TD_TOKEN) == sizeof(ULONG));
189 
190 #define UHCI_TD_LINK_PTR_VALID (0 << 0)
191 #define UHCI_TD_LINK_PTR_TERMINATE (1 << 0)
192 #define UHCI_TD_LINK_PTR_TD (0 << 1)
193 #define UHCI_TD_LINK_PTR_QH (1 << 1)
194 #define UHCI_TD_LINK_PTR_BREADTH_FIRST (0 << 2)
195 #define UHCI_TD_LINK_PTR_DEPTH_FIRST (1 << 2)
196 #define UHCI_TD_LINK_POINTER_MASK 0xFFFFFFF0
197 
198 typedef struct _UHCI_TD { // Transfer Descriptors always aligned on 16-byte boundaries
203 } UHCI_TD, *PUHCI_TD;
204 
205 C_ASSERT(sizeof(UHCI_TD) == 16);
206 
207 /* Queue Header (QH) */
208 #define UHCI_QH_HEAD_LINK_PTR_VALID (0 << 0)
209 #define UHCI_QH_HEAD_LINK_PTR_TERMINATE (1 << 0)
210 #define UHCI_QH_HEAD_LINK_PTR_TD (0 << 1)
211 #define UHCI_QH_HEAD_LINK_PTR_QH (1 << 1)
212 #define UHCI_QH_HEAD_LINK_POINTER_MASK 0xFFFFFFF0
213 
214 #define UHCI_QH_ELEMENT_LINK_PTR_VALID (0 << 0)
215 #define UHCI_QH_ELEMENT_LINK_PTR_TERMINATE (1 << 0)
216 #define UHCI_QH_ELEMENT_LINK_PTR_TD (0 << 1)
217 #define UHCI_QH_ELEMENT_LINK_PTR_QH (1 << 1)
218 #define UHCI_QH_ELEMENT_LINK_POINTER_MASK 0xFFFFFFF0
219 
220 typedef struct _UHCI_QH { // Queue Heads must be aligned on a 16-byte boundary
223 } UHCI_QH, *PUHCI_QH;
224 
225 C_ASSERT(sizeof(UHCI_QH) == 8);
struct _UHCI_TD UHCI_TD
ULONG Buffer
Definition: hardware.h:202
USHORT AsUSHORT
Definition: hardware.h:82
USHORT ResumeDetect
Definition: hardware.h:76
struct _UHCI_QH UHCI_QH
ULONG NextElement
Definition: hardware.h:222
USHORT GlobalReset
Definition: hardware.h:56
USHORT GlobalResume
Definition: hardware.h:58
USHORT Smi64Read
Definition: hardware.h:31
USHORT SmiIrq
Definition: hardware.h:33
USHORT Reserved
Definition: hardware.h:43
ULONG DataToggle
Definition: hardware.h:181
USHORT TrapBy60WriteStatus
Definition: hardware.h:38
USHORT SoftwareDebug
Definition: hardware.h:59
struct _UHCI_HW_REGISTERS UHCI_HW_REGISTERS
ULONG PIDCode
Definition: hardware.h:178
USHORT InterruptOnComplete
Definition: hardware.h:92
ULONG Reserved
Definition: hardware.h:182
struct _UHCI_QH * PUHCI_QH
union _UHCI_USB_STATUS UHCI_USB_STATUS
UHCI_USB_STATUS HcStatus
Definition: hardware.h:129
USHORT TrapBy60ReadStatus
Definition: hardware.h:37
_Reserved_ PVOID Reserved
Definition: winddi.h:3974
USHORT UsbPIRQ
Definition: hardware.h:42
USHORT ConfigureFlag
Definition: hardware.h:60
union _UHCI_TD_TOKEN UHCI_TD_TOKEN
union _UHCI_PORT_STATUS_CONTROL UHCI_PORT_STATUS_CONTROL
USHORT EndA20GateStatus
Definition: hardware.h:44
USHORT Smi60Read
Definition: hardware.h:29
ULONG MaximumLength
Definition: hardware.h:183
USHORT Interrupt
Definition: hardware.h:74
ULONG Endpoint
Definition: hardware.h:180
ULONG NextElement
Definition: hardware.h:199
USHORT HostSystemError
Definition: hardware.h:77
struct _UHCI_TD * PUHCI_TD
USHORT GlobalSuspend
Definition: hardware.h:57
USHORT AsUSHORT
Definition: hardware.h:64
USHORT SmiEndPassThrough
Definition: hardware.h:36
struct _UHCI_HW_REGISTERS * PUHCI_HW_REGISTERS
union _UHCI_USB_COMMAND UHCI_USB_COMMAND
union _UHCI_CONTROL_STATUS UHCI_CONTROL_STATUS
C_ASSERT(sizeof(PAGE_TABLE_ARM)==PAGE_SIZE)
union _UHCI_INTERRUPT_ENABLE UHCI_INTERRUPT_ENABLE
ULONG DeviceAddress
Definition: hardware.h:179
unsigned char UCHAR
Definition: xmlstorage.h:181
USHORT HcHalted
Definition: hardware.h:79
ULONG NextQH
Definition: hardware.h:221
union _UHCI_PCI_LEGSUP UHCI_PCI_LEGSUP
USHORT Reserved
Definition: hardware.h:80
USHORT ErrorInterrupt
Definition: hardware.h:75
UHCI_PORT_STATUS_CONTROL PortControl[UHCI_NUM_ROOT_HUB_PORTS]
Definition: hardware.h:135
ULONG InterruptOnComplete
Definition: hardware.h:157
unsigned short USHORT
Definition: pedump.c:61
#define UHCI_NUM_ROOT_HUB_PORTS
Definition: hardware.h:9
USHORT TrapBy64ReadStatus
Definition: hardware.h:39
USHORT Smi60Write
Definition: hardware.h:30
USHORT A20Gate
Definition: hardware.h:34
ULONG AsULONG
Definition: hardware.h:185
USHORT HcProcessError
Definition: hardware.h:78
USHORT PassThroughStatus
Definition: hardware.h:35
UHCI_CONTROL_STATUS ControlStatus
Definition: hardware.h:200
UHCI_USB_COMMAND HcCommand
Definition: hardware.h:128
USHORT TrapBy64WriteStatus
Definition: hardware.h:40
unsigned int ULONG
Definition: retypes.h:1
USHORT Reserved
Definition: hardware.h:62
USHORT UsbIrqStatus
Definition: hardware.h:41
USHORT FrameNumber
Definition: hardware.h:131
UHCI_INTERRUPT_ENABLE HcInterruptEnable
Definition: hardware.h:130
USHORT MaxPacket
Definition: hardware.h:61
USHORT Smi64Write
Definition: hardware.h:32
USHORT AsUSHORT
Definition: hardware.h:46
UHCI_TD_TOKEN Token
Definition: hardware.h:201
USHORT HcReset
Definition: hardware.h:55