8 #define UHCI_FRAME_LIST_MAX_ENTRIES 1024 // Number of frames in Frame List 9 #define UHCI_NUM_ROOT_HUB_PORTS 2 12 #define UHCI_USBCMD 0 // USB Command R/W 13 #define UHCI_USBSTS 1 // USB Status R/WC 14 #define UHCI_USBINTR 2 // USB Interrupt Enable R/W 15 #define UHCI_FRNUM 3 // Frame Number R/W WORD writeable only 16 #define UHCI_FRBASEADD 4 // Frame List Base Address R/W // 32 bit 17 #define UHCI_SOFMOD 6 // Start Of Frame Modify R/W // 8 bit 18 #define UHCI_PORTSC1 8 // Port 1 Status/Control R/WC WORD writeable only 19 #define UHCI_PORTSC2 9 // Port 2 Status/Control R/WC WORD writeable only 22 #define PCI_LEGSUP 0xC0 // Legacy Support register offset. R/WC 23 #define PCI_LEGSUP_USBPIRQDEN 0x2000 24 #define PCI_LEGSUP_CLEAR_SMI 0x8F00 70 #define UHCI_USB_STATUS_MASK 0x3F 102 #define UHCI_FRNUM_FRAME_MASK 0x7FF 103 #define UHCI_FRNUM_INDEX_MASK 0x3FF 104 #define UHCI_FRNUM_OVERFLOW_LIST 0x400 139 #define UHCI_TD_STS_ACTIVE (1 << 7) 140 #define UHCI_TD_STS_STALLED (1 << 6) 141 #define UHCI_TD_STS_DATA_BUFFER_ERROR (1 << 5) 142 #define UHCI_TD_STS_BABBLE_DETECTED (1 << 4) 143 #define UHCI_TD_STS_NAK_RECEIVED (1 << 3) 144 #define UHCI_TD_STS_TIMEOUT_CRC_ERROR (1 << 2) 145 #define UHCI_TD_STS_BITSTUFF_ERROR (1 << 1) 148 #define UHCI_TD_VALID_LENGTH 0x4FF 149 #define UHCI_TD_LENGTH_INVALID 0x7FE 150 #define UHCI_TD_LENGTH_NULL 0x7FF 169 #define UHCI_TD_PID_IN 0x69 170 #define UHCI_TD_PID_OUT 0xE1 171 #define UHCI_TD_PID_SETUP 0x2D 173 #define UHCI_TD_PID_DATA0 0 174 #define UHCI_TD_PID_DATA1 1 190 #define UHCI_TD_LINK_PTR_VALID (0 << 0) 191 #define UHCI_TD_LINK_PTR_TERMINATE (1 << 0) 192 #define UHCI_TD_LINK_PTR_TD (0 << 1) 193 #define UHCI_TD_LINK_PTR_QH (1 << 1) 194 #define UHCI_TD_LINK_PTR_BREADTH_FIRST (0 << 2) 195 #define UHCI_TD_LINK_PTR_DEPTH_FIRST (1 << 2) 196 #define UHCI_TD_LINK_POINTER_MASK 0xFFFFFFF0 208 #define UHCI_QH_HEAD_LINK_PTR_VALID (0 << 0) 209 #define UHCI_QH_HEAD_LINK_PTR_TERMINATE (1 << 0) 210 #define UHCI_QH_HEAD_LINK_PTR_TD (0 << 1) 211 #define UHCI_QH_HEAD_LINK_PTR_QH (1 << 1) 212 #define UHCI_QH_HEAD_LINK_POINTER_MASK 0xFFFFFFF0 214 #define UHCI_QH_ELEMENT_LINK_PTR_VALID (0 << 0) 215 #define UHCI_QH_ELEMENT_LINK_PTR_TERMINATE (1 << 0) 216 #define UHCI_QH_ELEMENT_LINK_PTR_TD (0 << 1) 217 #define UHCI_QH_ELEMENT_LINK_PTR_QH (1 << 1) 218 #define UHCI_QH_ELEMENT_LINK_POINTER_MASK 0xFFFFFFF0
USHORT TrapBy60WriteStatus
struct _UHCI_HW_REGISTERS UHCI_HW_REGISTERS
USHORT InterruptOnComplete
struct _UHCI_QH * PUHCI_QH
union _UHCI_USB_STATUS UHCI_USB_STATUS
USHORT TrapBy60ReadStatus
USHORT CurrentConnectStatus
_Reserved_ PVOID Reserved
union _UHCI_TD_TOKEN UHCI_TD_TOKEN
union _UHCI_PORT_STATUS_CONTROL UHCI_PORT_STATUS_CONTROL
struct _UHCI_TD * PUHCI_TD
USHORT PortEnabledDisabled
struct _UHCI_HW_REGISTERS * PUHCI_HW_REGISTERS
union _UHCI_USB_COMMAND UHCI_USB_COMMAND
union _UHCI_CONTROL_STATUS UHCI_CONTROL_STATUS
C_ASSERT(sizeof(PAGE_TABLE_ARM)==PAGE_SIZE)
union _UHCI_INTERRUPT_ENABLE UHCI_INTERRUPT_ENABLE
union _UHCI_PCI_LEGSUP UHCI_PCI_LEGSUP
UHCI_PORT_STATUS_CONTROL PortControl[UHCI_NUM_ROOT_HUB_PORTS]
USHORT PortEnableDisableChange
ULONG InterruptOnComplete
#define UHCI_NUM_ROOT_HUB_PORTS
USHORT TrapBy64ReadStatus
USHORT ConnectStatusChange
UHCI_CONTROL_STATUS ControlStatus
UHCI_USB_COMMAND HcCommand
USHORT TrapBy64WriteStatus
UHCI_INTERRUPT_ENABLE HcInterruptEnable