ReactOS 0.4.15-dev-8227-g32d615f
bootdata.c
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1/*
2 * PROJECT: ReactOS Boot Video Driver for VGA-compatible cards
3 * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
4 * PURPOSE: Command strings for VGA built-in modes
5 * COPYRIGHT: Copyright 2007 Alex Ionescu <alex.ionescu@reactos.org>
6 * Copyright 2019 Hermès Bélusca-Maïto <hermes.belusca-maito@reactos.org>
7 */
8
9#include "precomp.h"
10
11//
12// Minimal Attribute Controller Registers initialization command stream.
13// Compatible EGA.
14//
16{
17 /* Reset ATC to index mode */
18 IB,
19 VGA_BASE_IO_PORT + ATT_INITIALIZE_PORT_COLOR /* INPUT_STATUS_1_COLOR */,
20
21 /* Write the AC registers */
23 VGA_BASE_IO_PORT + ATT_ADDRESS_PORT /* ATT_DATA_WRITE_PORT */,
24 16, 0, // Values Count and Start Index
25 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, // Palette indices 0-5
26 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, // Palette indices 6-11
27 0x0C, 0x0D, 0x0E, 0x0F, // Palette indices 12-15
28
29 /* Reset ATC to index mode */
30 IB,
31 VGA_BASE_IO_PORT + ATT_INITIALIZE_PORT_COLOR /* INPUT_STATUS_1_COLOR */,
32
33 /* Enable screen and disable palette access */
34 OB,
35 VGA_BASE_IO_PORT + ATT_ADDRESS_PORT /* ATT_DATA_WRITE_PORT */,
37
38 /* End of Stream */
39 EOD
40};
41
42//
43// 640x480 256-color 60Hz mode (BIOS mode 12) set command stream for VGA.
44// Adapted from win32ss/drivers/miniport/vga_new/vgadata.c
45//
47{
48 /* Write the Sequencer Registers */
49 OWM,
51 VGA_NUM_SEQUENCER_PORTS, // Values Count (5)
52 // HI: Value in SEQ_DATA_PORT, LO: Register index in SEQ_ADDRESS_PORT
53 0x0100, // Synchronous reset on
54 0x0101, // 8-Dot Mode
55 0x0F02, // Memory Plane Write Enable on all planes 0-3
56 0x0003, // No character set selected
57 0x0604, // Disable Odd/Even host mem addressing; Enable Extended Memory
58
59 /* Write the Miscellaneous Register */
60 OB,
62 0xE3, // V/H-SYNC polarity, Odd/Even High page select, RAM enable,
63 // I/O Address select (1: color/graphics adapter)
64
65 /* Enable Graphics Mode */
66 OW,
68 // HI: Value in GRAPH_DATA_PORT, LO: Register index in GRAPH_ADDRESS_PORT
69 0x506, // Select A0000h-AFFFFh memory region, Disable Alphanumeric mode
70
71 /* Synchronous reset off */
72 OW,
74 // HI: Value in SEQ_DATA_PORT, LO: Register index in SEQ_ADDRESS_PORT
75 0x0300, // Synchronous reset off (LO: IND_SYNC_RESET, HI: END_SYNC_RESET_VALUE)
76
77 /* Unlock CRTC registers 0-7 */
78 OW,
80 0x511,
81
82 /* Write the CRTC registers */
85 VGA_NUM_CRTC_PORTS, 0, // Values Count (25) and Start Index
86 0x5F, 0x4F, 0x50, 0x82, 0x54, 0x80, 0x0B, 0x3E, 0x00, 0x40, 0x00, 0x00,
87 0x00, 0x00, 0x00, 0x00, 0xEA, 0x8C, 0xDF, 0x28, 0x00, 0xE7, 0x04, 0xE3,
88 0xFF,
89
90 /* Reset ATC to index mode */
91 IB,
92 VGA_BASE_IO_PORT + ATT_INITIALIZE_PORT_COLOR /* INPUT_STATUS_1_COLOR */,
93
94 /* Write the AC registers */
96 VGA_BASE_IO_PORT + ATT_ADDRESS_PORT /* ATT_DATA_WRITE_PORT */,
97 VGA_NUM_ATTRIB_CONT_PORTS, 0, // Values Count (21) and Start Index
98 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, // Palette indices 0-5
99 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, // Palette indices 6-11
100 0x0C, 0x0D, 0x0E, 0x0F, // Palette indices 12-15
101 0x01, 0x00, 0x0F, 0x00, 0x00,
102
103 /* Write the GC registers */
106 VGA_NUM_GRAPH_CONT_PORTS, 0, // Values Count (9) and Start Index
107 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
108 0x05, 0x0F, 0xFF,
109
110 /* Set the PEL mask */
111 OB,
113 0xFF,
114
115 /* Reset ATC to index mode */
116 IB,
117 VGA_BASE_IO_PORT + ATT_INITIALIZE_PORT_COLOR /* INPUT_STATUS_1_COLOR */,
118
119 /* Enable screen and disable palette access */
120 OB,
121 VGA_BASE_IO_PORT + ATT_ADDRESS_PORT /* ATT_DATA_WRITE_PORT */,
123
124 /* End of Stream */
125 EOD
126};
USHORT VGA_640x480[]
Definition: bootdata.c:46
USHORT AT_Initialization[]
Definition: bootdata.c:15
#define ATCOUT
Definition: cmdcnst.h:76
#define INDXOUT
Definition: cmdcnst.h:75
#define OW
Definition: cmdcnst.h:84
#define EOD
Definition: cmdcnst.h:60
#define METAOUT
Definition: cmdcnst.h:62
#define IB
Definition: cmdcnst.h:87
#define OB
Definition: cmdcnst.h:82
#define OWM
Definition: cmdcnst.h:85
#define MISC_OUTPUT_REG_WRITE_PORT
Definition: vga.h:63
#define SEQ_ADDRESS_PORT
Definition: vga.h:69
#define ATT_INITIALIZE_PORT_COLOR
Definition: vga.h:90
#define DAC_PIXEL_MASK_PORT
Definition: vga.h:71
#define VGA_NUM_SEQUENCER_PORTS
Definition: vga.h:208
#define VGA_NUM_ATTRIB_CONT_PORTS
Definition: vga.h:211
#define GRAPH_ADDRESS_PORT
Definition: vga.h:81
#define VGA_NUM_CRTC_PORTS
Definition: vga.h:209
#define CRTC_ADDRESS_PORT_COLOR
Definition: vga.h:84
#define VGA_NUM_GRAPH_CONT_PORTS
Definition: vga.h:210
#define VGA_BASE_IO_PORT
Definition: vga.h:38
#define ATT_ADDRESS_PORT
Definition: vga.h:57
#define VIDEO_ENABLE
Definition: vga.h:134
unsigned short USHORT
Definition: pedump.c:61