ReactOS 0.4.16-dev-106-g10b08aa
phyreg.h
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1/*
2 * PROJECT: ReactOS nVidia nForce Ethernet Controller Driver
3 * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
4 * PURPOSE: PHY layer register definitions
5 * COPYRIGHT: Copyright 2021-2022 Dmitry Borisov <di.sean@protonmail.com>
6 */
7
8#pragma once
9
10/* IEEE 802.3 */
11#define MII_CONTROL 0x00
12#define MII_CR_AUTONEG_RESTART 0x0200
13#define MII_CR_POWER_DOWN 0x0800
14#define MII_CR_AUTONEG 0x1000
15#define MII_CR_RESET 0x8000
16#define MII_STATUS 0x01
17#define MII_SR_LINK_STATUS 0x0004
18#define MII_SR_AUTONEG_COMPLETE 0x0020
19#define MII_PHY_ID1 0x02
20#define MII_PHY_ID2 0x03
21#define MII_AUTONEG_ADVERTISE 0x04
22#define MII_ADV_10T_HD 0x0020
23#define MII_ADV_10T_FD 0x0040
24#define MII_ADV_100T_HD 0x0080
25#define MII_ADV_100T_FD 0x0100
26#define MII_ADV_100T4 0x0200
27#define MII_ADV_PAUSE_SYM 0x0400
28#define MII_ADV_PAUSE_ASYM 0x0800
29#define MII_AUTONEG_LINK_PARTNER 0x05
30#define MII_LP_10T_HD 0x0020
31#define MII_LP_10T_FD 0x0040
32#define MII_LP_100T_HD 0x0080
33#define MII_LP_100T_FD 0x0100
34#define MII_LP_PAUSE_SYM 0x0400
35#define MII_LP_PAUSE_ASYM 0x0800
36#define MII_AUTONEG_EXPANSION 0x06
37#define MII_EXP_LP_AUTONEG 0x0001
38#define MII_MASTER_SLAVE_CONTROL 0x09
39#define MII_MS_CR_1000T_HD 0x0100
40#define MII_MS_CR_1000T_FD 0x0200
41#define MII_MASTER_SLAVE_STATUS 0x0A
42#define MII_MS_SR_1000T_FD 0x0800