ReactOS
0.4.16-dev-106-g10b08aa
phyreg.h
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/*
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* PROJECT: ReactOS nVidia nForce Ethernet Controller Driver
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* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
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* PURPOSE: PHY layer register definitions
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* COPYRIGHT: Copyright 2021-2022 Dmitry Borisov <di.sean@protonmail.com>
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*/
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#pragma once
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/* IEEE 802.3 */
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#define MII_CONTROL 0x00
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#define MII_CR_AUTONEG_RESTART 0x0200
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#define MII_CR_POWER_DOWN 0x0800
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#define MII_CR_AUTONEG 0x1000
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#define MII_CR_RESET 0x8000
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#define MII_STATUS 0x01
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#define MII_SR_LINK_STATUS 0x0004
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#define MII_SR_AUTONEG_COMPLETE 0x0020
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#define MII_PHY_ID1 0x02
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#define MII_PHY_ID2 0x03
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#define MII_AUTONEG_ADVERTISE 0x04
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#define MII_ADV_10T_HD 0x0020
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#define MII_ADV_10T_FD 0x0040
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#define MII_ADV_100T_HD 0x0080
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#define MII_ADV_100T_FD 0x0100
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#define MII_ADV_100T4 0x0200
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#define MII_ADV_PAUSE_SYM 0x0400
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#define MII_ADV_PAUSE_ASYM 0x0800
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#define MII_AUTONEG_LINK_PARTNER 0x05
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#define MII_LP_10T_HD 0x0020
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#define MII_LP_10T_FD 0x0040
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#define MII_LP_100T_HD 0x0080
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#define MII_LP_100T_FD 0x0100
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#define MII_LP_PAUSE_SYM 0x0400
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#define MII_LP_PAUSE_ASYM 0x0800
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#define MII_AUTONEG_EXPANSION 0x06
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#define MII_EXP_LP_AUTONEG 0x0001
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#define MII_MASTER_SLAVE_CONTROL 0x09
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#define MII_MS_CR_1000T_HD 0x0100
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#define MII_MS_CR_1000T_FD 0x0200
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#define MII_MASTER_SLAVE_STATUS 0x0A
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#define MII_MS_SR_1000T_FD 0x0800
drivers
network
dd
nvnet
phyreg.h
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