#include <Cpuid.h>

Collaboration diagram for CPUID_AMD_L1_TLB_INFO_EDX:

[legend]

Public Attributes
struct {
UINT32 L1IcLineSize: 8
	EDX[7..0] - L1 instruction cache line size in bytes. More...

UINT32 L1IcLinesPerTag: 8
	EDX[15..8] - L1 instruction cache lines per tag. More...

UINT32 L1IcAssoc: 8
	EDX[23..16] - L1 instruction cache associativity (0xFF = Fully associative) More...

UINT32 L1IcSize: 8
	EDX[31..24] - L1 instruction cache size KB. More...

}	Bits

UINT32	Uint32

Detailed Description

Definition at line 219 of file Cpuid.h.

Member Data Documentation

struct { ... } CPUID_AMD_L1_TLB_INFO_EDX::Bits

UINT32 CPUID_AMD_L1_TLB_INFO_EDX::L1IcAssoc

EDX[23..16] - L1 instruction cache associativity (0xFF = Fully associative)

Definition at line 225 of file Cpuid.h.

UINT32 CPUID_AMD_L1_TLB_INFO_EDX::L1IcLineSize

EDX[7..0] - L1 instruction cache line size in bytes.

Definition at line 223 of file Cpuid.h.

UINT32 CPUID_AMD_L1_TLB_INFO_EDX::L1IcLinesPerTag

EDX[15..8] - L1 instruction cache lines per tag.

Definition at line 224 of file Cpuid.h.

UINT32 CPUID_AMD_L1_TLB_INFO_EDX::L1IcSize

EDX[31..24] - L1 instruction cache size KB.

Definition at line 226 of file Cpuid.h.

UINT32 CPUID_AMD_L1_TLB_INFO_EDX::Uint32

Definition at line 228 of file Cpuid.h.

The documentation for this union was generated from the following file: