ReactOS  0.4.15-dev-1197-g8081ba9
video.h
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1 /*
2  * PROJECT: NEC PC-98 series onboard hardware
3  * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
4  * PURPOSE: Graphics system header file
5  * COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
6  */
7 
8 #pragma once
9 
10 /* Video memory ***************************************************************/
11 
12 #define VRAM_NORMAL_PLANE_B 0xA8000 /* Blue */
13 #define VRAM_NORMAL_PLANE_G 0xB0000 /* Green */
14 #define VRAM_NORMAL_PLANE_R 0xB8000 /* Red */
15 #define VRAM_NORMAL_PLANE_I 0xE0000 /* Intensity */
16 #define VRAM_PLANE_SIZE 0x08000
17 #define VRAM_NORMAL_TEXT 0xA0000
18 #define VRAM_TEXT_ATTR_OFFSET 0x02000
19 #define VRAM_TEXT_SIZE 0x02000
20 #define VRAM_ATTR_SIZE 0x02000
21 
22 #define PEGC_FRAMEBUFFER_PACKED 0xF00000
23 #define PEGC_FRAMEBUFFER_SIZE 0x080000
24 
25 #define PEGC_CONTROL_SIZE 0x000200
26 
27 /* High-resolution machine */
28 #define VRAM_HI_RESO_PLANE_B 0xC0000
29 #define VRAM_HI_RESO_PLANE_G 0xC8000
30 #define VRAM_HI_RESO_PLANE_R 0xD0000
31 #define VRAM_HI_RESO_PLANE_I 0xD8000
32 #define VRAM_HI_RESO_TEXT 0xE0000
33 
34 /* GDC definitions ************************************************************/
35 
36 #define GDC_STATUS_DRDY 0x01
37 #define GDC_STATUS_FIFO_FULL 0x02
38 #define GDC_STATUS_FIFO_EMPTY 0x04
39 #define GDC_STATUS_DRAWING 0x08
40 #define GDC_STATUS_DMA_EXECUTE 0x10
41 #define GDC_STATUS_VSYNC 0x20
42 #define GDC_STATUS_HBLANK 0x40
43 #define GDC_STATUS_LPEN 0x80
44 
45 #define GDC_ATTR_VISIBLE 0x01
46 #define GDC_ATTR_BLINK 0x02
47 #define GDC_ATTR_REVERSE 0x04
48 #define GDC_ATTR_UNDERLINE 0x08
49 #define GDC_ATTR_VERTICAL_LINE 0x10
50 
51 #define GDC_ATTR_BLACK 0x00
52 #define GDC_ATTR_BLUE 0x20
53 #define GDC_ATTR_RED 0x40
54 #define GDC_ATTR_PURPLE 0x60
55 #define GDC_ATTR_GREEN 0x80
56 #define GDC_ATTR_LIGHTBLUE 0xA0
57 #define GDC_ATTR_YELLOW 0xC0
58 #define GDC_ATTR_WHITE 0xE0
59 
60 /* Operation type */
61 #define GDC_MOD_REPLACE 0x00
62 #define GDC_MOD_COMPLEMENT 0x01 /* XOR */
63 #define GDC_MOD_CLEAR 0x02 /* AND */
64 #define GDC_MOD_SET 0x03 /* OR */
65 
66 #define GDC_GRAPHICS_DRAWING 0x40
67 
68 #define GDC_COMMAND_RESET1 0x00
69 #define GDC_COMMAND_RESET2 0x01
70 #define GDC_COMMAND_STOP2 0x05
71 #define GDC_COMMAND_RESET3 0x09
72 #define GDC_COMMAND_BCTRL_STOP 0x0C
73 #define GDC_COMMAND_BCTRL_START 0x0D
74 
75 #define GDC_COMMAND_SYNC_ON 0x0E
76 typedef struct _SYNCPARAM
77 {
79 #define SYNC_DISPLAY_MODE_GRAPHICS_AND_CHARACTERS 0x00
80 #define SYNC_DISPLAY_MODE_GRAPHICS 0x02
81 #define SYNC_DISPLAY_MODE_CHARACTERS 0x20
82 
83 #define SYNC_VIDEO_FRAMING_NONINTERLACED 0x00
84 #define SYNC_VIDEO_FRAMING_INTERLACED_REPEAT_FOR_CHARACTERS 0x08
85 #define SYNC_VIDEO_FRAMING_INTERLACED 0x09
86 
87 #define SYNC_DRAW_DURING_ACTIVE_DISPLAY_TIME_AND_RETRACE_BLANKING 0x00
88 #define SYNC_DRAW_ONLY_DURING_RETRACE_BLANKING 0x10
89 
90 #define SYNC_STATIC_RAM_NO_REFRESH 0x00
91 #define SYNC_DYNAMIC_RAM_REFRESH 0x04
92 
102 
104 VOID
106 {
107  WRITE_PORT_UCHAR(Port, SyncParameters->Flags & 0x3F);
108  WRITE_PORT_UCHAR(Port, SyncParameters->ScreenWidthChars - 2);
109  WRITE_PORT_UCHAR(Port, (SyncParameters->VerticalSyncWidth & 0x07) << 5 |
110  (SyncParameters->HorizontalSyncWidth - 1));
111  WRITE_PORT_UCHAR(Port, ((SyncParameters->HorizontalFrontPorchWidth - 1) << 2) |
112  ((SyncParameters->VerticalSyncWidth & 0x18) >> 3));
113  WRITE_PORT_UCHAR(Port, SyncParameters->HorizontalBackPorchWidth - 1);
115  WRITE_PORT_UCHAR(Port, SyncParameters->ScreenWidthLines & 0xFF);
116  WRITE_PORT_UCHAR(Port, (SyncParameters->VerticalBackPorchWidth << 2) |
117  ((SyncParameters->ScreenWidthLines & 0x300) >> 8));
118 }
119 
120 #define GDC_COMMAND_SYNC_OFF 0x0F
121 #define GDC_COMMAND_WRITE 0x20
122 #define GDC_COMMAND_DMAW 0x24
123 
124 #define GDC_COMMAND_ZOOM 0x46
125 typedef struct _ZOOMPARAM
126 {
130 
132 VOID
134 {
135  WRITE_PORT_UCHAR(Port, ZoomParameters->DisplayZoomFactor << 4 | ZoomParameters->WritingZoomFactor);
136 }
137 
138 #define GDC_COMMAND_PITCH 0x47
139 typedef struct _PITCHPARAM
140 {
143 
145 VOID
147 {
148  WRITE_PORT_UCHAR(Port, PitchParameters->WordsPerScanline);
149 }
150 
151 #define GDC_COMMAND_CSRW 0x49
152 typedef struct _CSRWPARAM
153 {
157 
159 VOID
161 {
162  ASSERT(CursorParameters->CursorAddress < 0xF00000);
163  ASSERT(CursorParameters->DotAddress < 0x10);
164 
165  WRITE_PORT_UCHAR(Port, CursorParameters->CursorAddress & 0xFF);
166  WRITE_PORT_UCHAR(Port, (CursorParameters->CursorAddress >> 8) & 0xFF);
167  WRITE_PORT_UCHAR(Port, (CursorParameters->DotAddress << 4) |
168  ((CursorParameters->CursorAddress >> 16) & 0x03));
169 }
170 
171 #define GDC_COMMAND_MASK 0x4A
172 
173 #define GDC_COMMAND_CSRFORM 0x4B
174 typedef struct _CSRFORMPARAM
175 {
183 
185 VOID
187 {
188  WRITE_PORT_UCHAR(Port, ((CursorParameters->Show & 0x01) << 7) |
189  (CursorParameters->LinesPerRow - 1));
190  WRITE_PORT_UCHAR(Port, ((CursorParameters->BlinkRate & 0x03) << 6) |
191  ((!CursorParameters->Blink & 0x01) << 5) | CursorParameters->StartScanLine);
192  WRITE_PORT_UCHAR(Port, (CursorParameters->EndScanLine << 3) | ((CursorParameters->BlinkRate & 0x1C) >> 2));
193 }
194 
195 #define GDC_COMMAND_FIGS 0x4C
196 #define GDC_COMMAND_GCHRD 0x68
197 #define GDC_COMMAND_START 0x6B
198 #define GDC_COMMAND_FIGD 0x6C
199 #define GDC_COMMAND_SLAVE 0x6E
200 #define GDC_COMMAND_MASTER 0x6F
201 
202 #define GDC_COMMAND_PRAM 0x70
203 typedef struct _PRAMPARAM
204 {
210 
212 VOID
214 {
215  WRITE_PORT_UCHAR(Port, RamParameters->StartingAddress & 0xFF);
216  WRITE_PORT_UCHAR(Port, (RamParameters->StartingAddress >> 8) & 0xFF);
217  WRITE_PORT_UCHAR(Port, ((RamParameters->Length & 0x0F) << 4) | ((RamParameters->StartingAddress >> 16) & 0x03));
218  WRITE_PORT_UCHAR(Port, ((RamParameters->WideDisplay & 0x01) << 7) | ((RamParameters->ImageBit & 0x01) << 6) |
219  ((RamParameters->Length >> 4) & 0x3F));
220 }
221 
222 #define GDC_COMMAND_TEXTW 0x78
223 #define GDC_COMMAND_READ 0xA0
224 #define GDC_COMMAND_DMAR 0xA4
225 #define GDC_COMMAND_LPRD 0xC0
226 #define GDC_COMMAND_CURD 0xE0
227 
228 /* Master GDC *****************************************************************/
229 
230 #define GDC1_IO_i_STATUS 0x60
231 #define GDC1_IO_i_DATA 0x62
232 #define GDC1_IO_i_MODE_FLIPFLOP1 0x68
233 
234 #define GDC1_IO_o_PARAM 0x60
235 #define GDC1_IO_o_COMMAND 0x62
236 #define GDC1_IO_o_VSYNC 0x64 /* CRT interrupt reset */
237 
238 #define GDC1_IO_o_MODE_FLIPFLOP1 0x68
239  #define GDC1_MODE_VERTICAL_LINE 0x00 /* Character attribute */
240  #define GDC1_MODE_SIMPLE_GRAPHICS 0x01
241  #define GRAPH_MODE_COLORED 0x02
242  #define GRAPH_MODE_MONOCHROME 0x03
243  #define GDC1_MODE_COLS_80 0x04
244  #define GDC1_MODE_COLS_40 0x05
245  #define GDC1_MODE_ANK_6_8 0x06
246  #define GDC1_MODE_ANK_7_13 0x07
247  #define GDC2_MODE_ODD_RLINE_SHOW 0x08
248  #define GDC2_MODE_ODD_RLINE_HIDE 0x09
249  #define GDC1_MODE_KCG_CODE 0x0A /* CG access during V-SYNC */
250  #define GDC1_MODE_KCG_BITMAP 0x0B
251  #define GDC1_NVRAM_PROTECT 0x0C
252  #define GDC1_NVRAM_UNPROTECT 0x0D /* Memory at TextVramSegment:(3FE2-3FFEh) */
253  #define GRAPH_MODE_DISPLAY_DISABLE 0x0E
254  #define GRAPH_MODE_DISPLAY_ENABLE 0x0F
255 
256 #define GDC1_IO_o_BORDER_COLOR 0x6C /* PC-H98 */
257 
258 /* Slave GDC ******************************************************************/
259 
260 #define GDC2_IO_i_STATUS 0xA0
261 #define GDC2_IO_i_DATA 0xA2
262 #define GDC2_IO_i_VIDEO_PAGE 0xA4
263 #define GDC2_IO_i_VIDEO_PAGE_ACCESS 0xA6
264 #define GDC2_IO_i_PALETTE_INDEX 0xA8
265 #define GDC2_IO_i_GREEN 0xAA
266 #define GDC2_IO_i_RED 0xAC
267 #define GDC2_IO_i_BLUE 0xAE
268 #define GDC2_IO_i_MODE_FLIPFLOP2 0x6A
269 #define GDC2_IO_i_MODE_FLIPFLOP3 0x6E
270 
271 #define GDC2_IO_o_PARAM 0xA0
272 #define GDC2_IO_o_COMMAND 0xA2
273 #define GDC2_IO_o_VIDEO_PAGE 0xA4 /* Video page to display (invalid in 480 height mode) */
274 #define GDC2_IO_o_VIDEO_PAGE_ACCESS 0xA6 /* Video page to CPU access */
275 #define GDC2_IO_o_PALETTE_INDEX 0xA8
276 #define GDC2_IO_o_GREEN 0xAA
277 #define GDC2_IO_o_RED 0xAC
278 #define GDC2_IO_o_BLUE 0xAE
279 
280 #define GDC2_IO_o_MODE_FLIPFLOP2 0x6A
281  #define GDC2_MODE_COLORS_8 0x00
282  #define GDC2_MODE_COLORS_16 0x01
283  #define GDC2_MODE_GRCG 0x04
284  #define GDC2_MODE_EGC 0x05
285  #define GDC2_EGC_FF_PROTECT 0x06
286  #define GDC2_EGC_FF_UNPROTECT 0x07 /* Unprotect the EGC F/F registers */
287  #define GDC2_MODE_PEGC_DISABLE 0x20
288  #define GDC2_MODE_PEGC_ENABLE 0x21
289  // #define GDC2_MODE_ 0x26
290  // #define GDC2_MODE_ 0x27
291  // #define GDC2_MODE_ 0x28
292  // #define GDC2_MODE_ 0x29
293  // #define GDC2_MODE_ 0x2A
294  // #define GDC2_MODE_ 0x2B
295  // #define GDC2_MODE_ 0x2C
296  // #define GDC2_MODE_ 0x2D
297  #define GDC2_MODE_CRT 0x40
298  #define GDC2_MODE_LCD 0x41
299  // #define GDC2_MODE_VRAM_PLANAR 0x62 /* PC-H98 */
300  // #define GDC2_MODE_VRAM_PACKED 0x63
301  #define GDC2_MODE_LINES_400 0x68 /* 128 kB VRAM boundary */
302  #define GDC2_MODE_LINES_800 0x69 /* 256 kB VRAM boundary */
303  // #define GDC2_MODE_ 0x6C
304  // #define GDC2_MODE_ 0x6D
305  #define GDC2_CLOCK1_2_5MHZ 0x82
306  #define GDC2_CLOCK1_5MHZ 0x83
307  #define GDC2_CLOCK2_2_5MHZ 0x84
308  #define GDC2_CLOCK2_5MHZ 0x85
309 
310 #define GDC2_IO_o_MODE_FLIPFLOP3 0x6E
311  // #define GDC2_MODE_ 0x02
312  // #define GDC2_MODE_ 0x03
313  // #define GDC2_MODE_ 0x08
314  // #define GDC2_MODE_ 0x09
315  // #define GDC2_MODE_ 0x0A
316  // #define GDC2_MODE_ 0x0B
317  // #define GDC2_MODE_ 0x0C
318  // #define GDC2_MODE_ 0x0D
319  // #define GDC2_MODE_ 0x0E
320  // #define GDC2_MODE_ 0x0F
321  // #define GDC2_MODE_ 0x14
322  // #define GDC2_MODE_ 0x15
323 
325 VOID
327 {
329  NOTHING;
330 
332 }
333 
335 VOID
337 {
339  NOTHING;
340 
342 }
343 
344 /* Miscellaneous **************************************************************/
345 
346 #define GRAPH_IO_i_STATUS 0x9A0
347  #define GRAPH_STATUS_SET 0x01
348  #define GRAPH_GDC_CLOCK2_5MHZ 0x02
349 
350 #define GRAPH_IO_o_STATUS_SELECT 0x9A0
351  #define GRAPH_STATUS_GDC_CLOCK1_5MHZ 0x09
352  #define GRAPH_STATUS_PEGC 0x0A
353 
354 #define GRAPH_IO_i_DPMS 0x9A2
355 #define GRAPH_IO_o_DPMS 0x9A2
356  #define GRAPH_DPMS_HSYNC_MASK 0x40
357  #define GRAPH_DPMS_VSYNC_MASK 0x80
358 
359 #define GRAPH_IO_i_HORIZONTAL_SCAN_RATE 0x9A8
360 #define GRAPH_IO_o_HORIZONTAL_SCAN_RATE 0x9A8
361  #define GRAPH_HF_24KHZ 0x00
362  #define GRAPH_HF_31KHZ 0x01
363 
364 #define GRAPH_IO_i_RELAY 0xFAC
365  #define GRAPH_RELAY_0 0x01
366  #define GRAPH_RELAY_1 0x02
367 
368 #define GRAPH_IO_o_RELAY 0xFAC
369  /* Relay 0 */
370  #define GRAPH_VID_SRC_INTERNAL 0x00
371  #define GRAPH_VID_SRC_EXTERNAL 0x01
372  /* Relay 1 */
373  #define GRAPH_SRC_GDC 0x00
374  #define GRAPH_SRC_WAB 0x02
375 
376 /* CRT Controller *************************************************************/
377 
378 #define CRTC_IO_o_SCANLINE_START 0x70
379 #define CRTC_IO_o_SCANLINE_END 0x72
380 #define CRTC_IO_o_SCANLINE_BLANK_AT 0x74
381 #define CRTC_IO_o_SCANLINES 0x76
382 #define CRTC_IO_o_SUR 0x78
383 #define CRTC_IO_o_SDR 0x7A
384 
385 /* GRCG (Graphic Charger) *****************************************************/
386 
387 #define GRCG_IO_i_MODE 0x7C
388 #define GRCG_IO_o_MODE 0x7C
389  #define GRCG_DISABLE 0x00
390  #define GRCG_ENABLE 0x80
391  #define GRCG_MODE_TILE_DIRECT_WRITE 0x80
392  #define GRCG_MODE_TILE_COMPARE_READ 0x80
393  #define GRCG_MODE_READ_MODIFY_WRITE 0xC0
394 
395 #define GRCG_IO_o_TILE_PATTERN 0x7E
396 
397 /* CG Window ******************************************************************/
398 
399 #define KCG_IO_o_CHARCODE_HIGH 0xA1
400 #define KCG_IO_o_CHARCODE_LOW 0xA3
401 #define KCG_IO_o_LINE 0xA5
402 #define KCG_IO_o_PATTERN 0xA9
403 
404 #define KCG_IO_i_PATTERN 0xA9
405 
406 /* EGC blitter ****************************************************************/
407 
408 #define EGC_IO_o_PLANE_ACCESS 0x4A0
409 #define EGC_IO_o_PATTERN_DATA_PLANE_READ 0x4A2
410 #define EGC_IO_o_READ_WRITE_MODE 0x4A4
411 #define EGC_IO_o_FG_COLOR 0x4A6
412 #define EGC_IO_o_MASK 0x4A8
413 #define EGC_IO_o_BG_COLOR 0x4AA
414 #define EGC_IO_o_BIT_ADDRESS 0x4AC
415 #define EGC_IO_o_BIT_LENGTH 0x4AE
416 
417 #define PEGC_MMIO_BANK_0 0x004
418 #define PEGC_MMIO_BANK_1 0x006
419 
420 #define PEGC_MMIO_MODE 0x100
421  #define PEGC_MODE_PACKED 0x00
422  #define PEGC_MODE_PLANAR 0x01
423 
424 #define PEGC_MMIO_FRAMEBUFFER 0x102
425  #define PEGC_FB_UNMAP 0x00
426  #define PEGC_FB_MAP 0x01
427  #define PEGC_FB_UNKNOWN1 0x02
428  #define PEGC_FB_UNKNOWN2 0x03
429 
430 #define PEGC_MMIO_PLANE_ACCESS 0x104
431 #define PEGC_MMIO_ROP 0x108
432 #define PEGC_MMIO_DATA_SELECT 0x10A
433 #define PEGC_MMIO_MASK 0x10C
434 #define PEGC_MMIO_BIT_LENGTH 0x110
435 #define PEGC_MMIO_BIT_ADDRESS 0x112
436 #define PEGC_MMIO_FG_COLOR 0x114
437 #define PEGC_MMIO_BG_COLOR 0x118
438 #define PEGC_MMIO_ROP_PATTERN 0x120
CPPORT Port[4]
Definition: headless.c:34
struct _PRAMPARAM PRAMPARAM
BOOLEAN ImageBit
Definition: video.h:207
USHORT Length
Definition: video.h:206
ULONG StartingAddress
Definition: video.h:205
UCHAR StartScanLine
Definition: video.h:180
UCHAR VerticalFrontPorchWidth
Definition: video.h:98
#define READ_PORT_UCHAR(p)
Definition: pc98vid.h:21
unsigned char * PUCHAR
Definition: retypes.h:3
struct _PITCHPARAM PITCHPARAM
struct _PITCHPARAM * PPITCHPARAM
Definition: shell.h:41
struct _SYNCPARAM * PSYNCPARAM
FORCEINLINE VOID WRITE_GDC1_COMMAND(UCHAR Command)
Definition: video.h:326
FORCEINLINE VOID WRITE_GDC_ZOOM(PUCHAR Port, PZOOMPARAM ZoomParameters)
Definition: video.h:133
BOOLEAN WideDisplay
Definition: video.h:208
UCHAR VerticalBackPorchWidth
Definition: video.h:100
struct _CSRFORMPARAM CSRFORMPARAM
FORCEINLINE VOID WRITE_GDC_PITCH(PUCHAR Port, PPITCHPARAM PitchParameters)
Definition: video.h:146
struct _CSRWPARAM * PCSRWPARAM
UCHAR WritingZoomFactor
Definition: video.h:128
UCHAR HorizontalSyncWidth
Definition: video.h:94
FORCEINLINE VOID WRITE_GDC_CSRFORM(PUCHAR Port, PCSRFORMPARAM CursorParameters)
Definition: video.h:186
struct _CSRWPARAM CSRWPARAM
unsigned char BOOLEAN
#define FORCEINLINE
Definition: ntbasedef.h:216
UCHAR DisplayZoomFactor
Definition: video.h:127
UCHAR EndScanLine
Definition: video.h:181
UCHAR ScreenWidthChars
Definition: video.h:93
FORCEINLINE VOID WRITE_GDC2_COMMAND(UCHAR Command)
Definition: video.h:336
ULONG CursorAddress
Definition: video.h:154
#define GDC1_IO_i_STATUS
Definition: video.h:230
UCHAR HorizontalBackPorchWidth
Definition: video.h:97
struct _PRAMPARAM * PPRAMPARAM
ASSERT((InvokeOnSuccess||InvokeOnError||InvokeOnCancel) ?(CompletionRoutine !=NULL) :TRUE)
unsigned char UCHAR
Definition: xmlstorage.h:181
#define GDC2_IO_o_COMMAND
Definition: video.h:272
#define WRITE_PORT_UCHAR(p, d)
Definition: pc98vid.h:20
FORCEINLINE VOID WRITE_GDC_SYNC(PUCHAR Port, PSYNCPARAM SyncParameters)
Definition: video.h:105
#define GDC_STATUS_FIFO_EMPTY
Definition: video.h:38
#define NOTHING
Definition: env_spec_w32.h:461
struct _SYNCPARAM SYNCPARAM
USHORT ScreenWidthLines
Definition: video.h:99
UCHAR Flags
Definition: video.h:78
BOOLEAN Show
Definition: video.h:176
FORCEINLINE VOID WRITE_GDC_CSRW(PUCHAR Port, PCSRWPARAM CursorParameters)
Definition: video.h:160
UCHAR VerticalSyncWidth
Definition: video.h:95
ULONG WordsPerScanline
Definition: video.h:141
unsigned short USHORT
Definition: pedump.c:61
struct _ZOOMPARAM ZOOMPARAM
UCHAR DotAddress
Definition: video.h:155
struct _CSRFORMPARAM * PCSRFORMPARAM
unsigned int ULONG
Definition: retypes.h:1
struct _ZOOMPARAM * PZOOMPARAM
UCHAR BlinkRate
Definition: video.h:178
BOOLEAN Blink
Definition: video.h:177
FORCEINLINE VOID WRITE_GDC_PRAM(PUCHAR Port, PPRAMPARAM RamParameters)
Definition: video.h:213
#define GDC1_IO_o_COMMAND
Definition: video.h:235
UCHAR HorizontalFrontPorchWidth
Definition: video.h:96
#define GDC2_IO_i_STATUS
Definition: video.h:260
UCHAR LinesPerRow
Definition: video.h:179