14#define UART_PL01x_DR (LlbHwVersaUartBase + 0x00)
15#define UART_PL01x_RSR (LlbHwVersaUartBase + 0x04)
16#define UART_PL01x_ECR (LlbHwVersaUartBase + 0x04)
17#define UART_PL01x_FR (LlbHwVersaUartBase + 0x18)
18#define UART_PL011_IBRD (LlbHwVersaUartBase + 0x24)
19#define UART_PL011_FBRD (LlbHwVersaUartBase + 0x28)
20#define UART_PL011_LCRH (LlbHwVersaUartBase + 0x2C)
21#define UART_PL011_CR (LlbHwVersaUartBase + 0x30)
22#define UART_PL011_IMSC (LlbHwVersaUartBase + 0x38)
27#define UART_PL011_LCRH_WLEN_8 0x60
28#define UART_PL011_LCRH_FEN 0x10
33#define UART_PL011_CR_UARTEN 0x01
34#define UART_PL011_CR_TXE 0x100
35#define UART_PL011_CR_RXE 0x200
40#define UART_PL01x_FR_RXFE 0x10
41#define UART_PL01x_FR_TXFF 0x20
58 Divider = ClockRate / (16 * Baudrate);
62 Fraction = (8 *
Remainder / Baudrate) >> 1;
63 Fraction += (8 *
Remainder / Baudrate) & 1;
#define WRITE_REGISTER_ULONG(r, v)
#define READ_REGISTER_ULONG(r)
ULONG NTAPI LlbHwGetPClk(VOID)
VOID NTAPI LlbHwUartSendChar(IN CHAR Char)
ULONG NTAPI LlbHwGetUartBase(IN ULONG Port)
BOOLEAN NTAPI LlbHwUartTxReady(VOID)
#define UART_PL011_LCRH_FEN
static const ULONG LlbHwVersaUartBase
#define UART_PL011_CR_RXE
VOID NTAPI LlbHwVersaUartInitialize(VOID)
#define UART_PL011_LCRH_WLEN_8
#define UART_PL011_CR_TXE
#define UART_PL01x_FR_TXFF
#define UART_PL011_CR_UARTEN
_In_ LARGE_INTEGER _Out_opt_ PLARGE_INTEGER Remainder