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ReactOS 0.4.17-dev-1343-g8fe3cee
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Macros | |
| #define | ARM64_MIDR_EL1 ARM64_SYSREG(3, 0, 0, 0, 0) |
| #define | ARM64_MPIDR_EL1 ARM64_SYSREG(3, 0, 0, 0, 5) |
| #define | ARM64_ID_AA64PFR0_EL1 ARM64_SYSREG(3, 0, 0, 4, 0) |
| #define | ARM64_ID_AA64DFR0_EL1 ARM64_SYSREG(3, 0, 0, 5, 0) |
| #define | ARM64_ID_AA64ISAR0_EL1 ARM64_SYSREG(3, 0, 0, 6, 0) |
| #define | ARM64_ID_AA64MMFR0_EL1 ARM64_SYSREG(3, 0, 0, 7, 0) |
| #define | ARM64_CTR_EL0 ARM64_SYSREG(3, 3, 0, 0, 1) |
| #define | ARM64_SCTLR_EL1 ARM64_SYSREG(3, 0, 1, 0, 0) |
| #define | ARM64_CPACR_EL1 ARM64_SYSREG(3, 0, 1, 0, 2) |
| #define | ARM64_TTBR0_EL1 ARM64_SYSREG(3, 0, 2, 0, 0) |
| #define | ARM64_TTBR1_EL1 ARM64_SYSREG(3, 0, 2, 0, 1) |
| #define | ARM64_TCR_EL1 ARM64_SYSREG(3, 0, 2, 0, 2) |
| #define | ARM64_DAIF ARM64_SYSREG(3, 3, 4, 2, 1) |
| #define | ARM64_ESR_EL1 ARM64_SYSREG(3, 0, 5, 2, 0) |
| #define | ARM64_FAR_EL1 ARM64_SYSREG(3, 0, 6, 0, 0) |
| #define | ARM64_PAR_EL1 ARM64_SYSREG(3, 0, 7, 4, 0) |
| #define | ARM64_MAIR_EL1 ARM64_SYSREG(3, 0, 10, 2, 0) |
| #define | ARM64_VBAR_EL1 ARM64_SYSREG(3, 0, 12, 0, 0) |
| #define | ARM64_CONTEXTIDR_EL1 ARM64_SYSREG(3, 0, 13, 0, 1) |
| #define | ARM64_TPIDR_EL1 ARM64_SYSREG(3, 0, 13, 0, 4) |
| #define | ARM64_TPIDRRO_EL0_REG ARM64_SYSREG(3, 3, 13, 0, 3) |
| #define | ARM64_CNTFRQ_EL0 ARM64_SYSREG(3, 3, 14, 0, 0) |
| #define | ARM64_CNTV_TVAL_EL0 ARM64_SYSREG(3, 3, 14, 3, 0) |
| #define | ARM64_CNTV_CTL_EL0 ARM64_SYSREG(3, 3, 14, 3, 1) |
| #define | ARM64_CNTV_CVAL_EL0 ARM64_SYSREG(3, 3, 14, 3, 2) |
| #define | ARM64_CNTKCTL_EL1 ARM64_SYSREG(3, 0, 14, 1, 0) |
| #define | ARM64_PSR_F 0x40 |
| #define | ARM64_PSR_I 0x80 |
| #define | ARM64_PSR_A 0x100 |
| #define | ARM64_PSR_D 0x200 |
| #define | ARM64_PSR_MODE_MASK 0xF |
| #define | ARM64_PSR_MODE_EL0T 0x0 |
| #define | ARM64_PSR_MODE_EL1H 0x5 |
| #define | KeArm64ReadRegister(Register) ((ULONG64)_ReadStatusReg(Register)) |
| #define | KeArm64WriteRegister(Register, Value) _WriteStatusReg((Register), (__int64)(Value)) |
| #define ARM64_CNTFRQ_EL0 ARM64_SYSREG(3, 3, 14, 0, 0) |
Definition at line 31 of file intrin_i.h.
| #define ARM64_CNTKCTL_EL1 ARM64_SYSREG(3, 0, 14, 1, 0) |
Definition at line 35 of file intrin_i.h.
| #define ARM64_CNTV_CTL_EL0 ARM64_SYSREG(3, 3, 14, 3, 1) |
Definition at line 33 of file intrin_i.h.
| #define ARM64_CNTV_CVAL_EL0 ARM64_SYSREG(3, 3, 14, 3, 2) |
Definition at line 34 of file intrin_i.h.
| #define ARM64_CNTV_TVAL_EL0 ARM64_SYSREG(3, 3, 14, 3, 0) |
Definition at line 32 of file intrin_i.h.
| #define ARM64_CONTEXTIDR_EL1 ARM64_SYSREG(3, 0, 13, 0, 1) |
Definition at line 28 of file intrin_i.h.
| #define ARM64_CPACR_EL1 ARM64_SYSREG(3, 0, 1, 0, 2) |
Definition at line 18 of file intrin_i.h.
| #define ARM64_CTR_EL0 ARM64_SYSREG(3, 3, 0, 0, 1) |
Definition at line 16 of file intrin_i.h.
| #define ARM64_DAIF ARM64_SYSREG(3, 3, 4, 2, 1) |
Definition at line 22 of file intrin_i.h.
| #define ARM64_ESR_EL1 ARM64_SYSREG(3, 0, 5, 2, 0) |
Definition at line 23 of file intrin_i.h.
| #define ARM64_FAR_EL1 ARM64_SYSREG(3, 0, 6, 0, 0) |
Definition at line 24 of file intrin_i.h.
| #define ARM64_ID_AA64DFR0_EL1 ARM64_SYSREG(3, 0, 0, 5, 0) |
Definition at line 13 of file intrin_i.h.
| #define ARM64_ID_AA64ISAR0_EL1 ARM64_SYSREG(3, 0, 0, 6, 0) |
Definition at line 14 of file intrin_i.h.
| #define ARM64_ID_AA64MMFR0_EL1 ARM64_SYSREG(3, 0, 0, 7, 0) |
Definition at line 15 of file intrin_i.h.
| #define ARM64_ID_AA64PFR0_EL1 ARM64_SYSREG(3, 0, 0, 4, 0) |
Definition at line 12 of file intrin_i.h.
| #define ARM64_MAIR_EL1 ARM64_SYSREG(3, 0, 10, 2, 0) |
Definition at line 26 of file intrin_i.h.
| #define ARM64_MIDR_EL1 ARM64_SYSREG(3, 0, 0, 0, 0) |
Definition at line 10 of file intrin_i.h.
| #define ARM64_MPIDR_EL1 ARM64_SYSREG(3, 0, 0, 0, 5) |
Definition at line 11 of file intrin_i.h.
| #define ARM64_PAR_EL1 ARM64_SYSREG(3, 0, 7, 4, 0) |
Definition at line 25 of file intrin_i.h.
| #define ARM64_PSR_A 0x100 |
Definition at line 40 of file intrin_i.h.
| #define ARM64_PSR_D 0x200 |
Definition at line 41 of file intrin_i.h.
| #define ARM64_PSR_F 0x40 |
Definition at line 38 of file intrin_i.h.
| #define ARM64_PSR_I 0x80 |
Definition at line 39 of file intrin_i.h.
| #define ARM64_PSR_MODE_EL0T 0x0 |
Definition at line 43 of file intrin_i.h.
| #define ARM64_PSR_MODE_EL1H 0x5 |
Definition at line 44 of file intrin_i.h.
| #define ARM64_PSR_MODE_MASK 0xF |
Definition at line 42 of file intrin_i.h.
| #define ARM64_SCTLR_EL1 ARM64_SYSREG(3, 0, 1, 0, 0) |
Definition at line 17 of file intrin_i.h.
| #define ARM64_TCR_EL1 ARM64_SYSREG(3, 0, 2, 0, 2) |
Definition at line 21 of file intrin_i.h.
| #define ARM64_TPIDR_EL1 ARM64_SYSREG(3, 0, 13, 0, 4) |
Definition at line 29 of file intrin_i.h.
| #define ARM64_TPIDRRO_EL0_REG ARM64_SYSREG(3, 3, 13, 0, 3) |
Definition at line 30 of file intrin_i.h.
| #define ARM64_TTBR0_EL1 ARM64_SYSREG(3, 0, 2, 0, 0) |
Definition at line 19 of file intrin_i.h.
| #define ARM64_TTBR1_EL1 ARM64_SYSREG(3, 0, 2, 0, 1) |
Definition at line 20 of file intrin_i.h.
| #define ARM64_VBAR_EL1 ARM64_SYSREG(3, 0, 12, 0, 0) |
Definition at line 27 of file intrin_i.h.
Definition at line 46 of file intrin_i.h.
Definition at line 47 of file intrin_i.h.
Referenced by KeFlushProcessTb().
Referenced by KeInvalidateTlbEntry().
Referenced by KeSweepICache().
| FORCEINLINE VOID KeSetCurrentIrql | ( | _In_ KIRQL | Irql | ) |
Definition at line 51 of file intrin_i.h.