ReactOS Fundraising Campaign 2012
 
€ 4,410 / € 30,000

Information | Donate

Home | Info | Community | Development | myReactOS | Contact Us

Navigation
  1. Home
  2. Community
  3. Development
  4. myReactOS
  5. Fundraiser 2012

Doxygen
  1. Main Page
  2. Alphabetical List
  3. Data Structures
  4. Directories
  5. File List
  6. Data Fields
  7. Globals
  8. Related Pages

Search

ReactOS Development > Doxygen

hardware.h
Go to the documentation of this file.
00001 #pragma once
00002 
00003 #include <ntddk.h>
00004 
00005 
00006 //
00007 // Host Controller Capability Registers
00008 //
00009 #define EHCI_CAPLENGTH                  0x00
00010 #define EHCI_HCIVERSION                 0x02
00011 #define EHCI_HCSPARAMS                  0x04
00012 #define EHCI_HCCPARAMS                  0x08
00013 #define EHCI_HCSP_PORTROUTE             0x0c
00014 
00015 
00016 //
00017 // Extended Capabilities
00018 //
00019 #define EHCI_ECP_SHIFT                  8
00020 #define EHCI_ECP_MASK                   0xff
00021 #define EHCI_LEGSUP_CAPID_MASK          0xff
00022 #define EHCI_LEGSUP_CAPID               0x01
00023 #define EHCI_LEGSUP_OSOWNED             (1 << 24)
00024 #define EHCI_LEGSUP_BIOSOWNED           (1 << 16)
00025 
00026 
00027 //
00028 // EHCI Operational Registers
00029 //
00030 #define EHCI_USBCMD                     0x00
00031 #define EHCI_USBSTS                     0x04
00032 #define EHCI_USBINTR                    0x08
00033 #define EHCI_FRINDEX                    0x0C
00034 #define EHCI_CTRLDSSEGMENT              0x10
00035 #define EHCI_PERIODICLISTBASE           0x14
00036 #define EHCI_ASYNCLISTBASE              0x18
00037 #define EHCI_CONFIGFLAG                 0x40
00038 #define EHCI_PORTSC                     0x44
00039 
00040 //
00041 // Interrupt Register Flags
00042 //
00043 #define EHCI_USBINTR_INTE               0x01
00044 #define EHCI_USBINTR_ERR                0x02
00045 #define EHCI_USBINTR_PC                 0x04
00046 #define EHCI_USBINTR_FLROVR             0x08
00047 #define EHCI_USBINTR_HSERR              0x10
00048 #define EHCI_USBINTR_ASYNC              0x20
00049 // Bits 6:31 Reserved
00050 
00051 //
00052 // Status Register Flags
00053 //
00054 #define EHCI_STS_INT                    0x01
00055 #define EHCI_STS_ERR                    0x02
00056 #define EHCI_STS_PCD                    0x04
00057 #define EHCI_STS_FLR                    0x08
00058 #define EHCI_STS_FATAL                  0x10
00059 #define EHCI_STS_IAA                    0x20
00060 // Bits 11:6 Reserved
00061 #define EHCI_STS_HALT                   0x1000
00062 #define EHCI_STS_RECL                   0x2000
00063 #define EHCI_STS_PSS                    0x4000
00064 #define EHCI_STS_ASS                    0x8000
00065 #define EHCI_ERROR_INT                  (EHCI_STS_FATAL | EHCI_STS_ERR)
00066 
00067 //
00068 // Port Register Flags
00069 //
00070 #define EHCI_PRT_CONNECTED              0x01
00071 #define EHCI_PRT_CONNECTSTATUSCHANGE    0x02
00072 #define EHCI_PRT_ENABLED                0x04
00073 #define EHCI_PRT_ENABLEDSTATUSCHANGE    0x08
00074 #define EHCI_PRT_OVERCURRENTACTIVE      0x10
00075 #define EHCI_PRT_OVERCURRENTCHANGE      0x20
00076 #define EHCI_PRT_FORCERESUME            0x40
00077 #define EHCI_PRT_SUSPEND                0x80
00078 #define EHCI_PRT_RESET                  0x100
00079 #define EHCI_PRT_LINESTATUSA            0x400
00080 #define EHCI_PRT_LINESTATUSB            0x800
00081 #define EHCI_PRT_POWER                  0x1000
00082 #define EHCI_PRT_RELEASEOWNERSHIP       0x2000
00083 
00084 #define EHCI_PORTSC_DATAMASK    0xffffffd1
00085 
00086 #define EHCI_IS_LOW_SPEED(x) (((x) & EHCI_PRT_LINESTATUSA) && !((x) & EHCI_PRT_LINESTATUSB))
00087 //
00088 // Terminate Pointer used for QueueHeads and Element Transfer Descriptors to mark Pointers as the end
00089 //
00090 #define TERMINATE_POINTER       0x01
00091 
00092 //
00093 // QUEUE ELEMENT TRANSFER DESCRIPTOR, defines and structs
00094 //
00095 
00096 //
00097 // Token Flags
00098 //
00099 #define PID_CODE_OUT_TOKEN      0x00
00100 #define PID_CODE_IN_TOKEN       0x01
00101 #define PID_CODE_SETUP_TOKEN    0x02
00102 
00103 #define DO_START_SPLIT          0x00
00104 #define DO_COMPLETE_SPLIT       0x01
00105 
00106 #define PING_STATE_DO_OUT       0x00
00107 #define PING_STATE_DO_PING      0x01
00108 
00109 typedef struct _PERIODICFRAMELIST
00110 {
00111     PULONG VirtualAddr;
00112     PHYSICAL_ADDRESS PhysicalAddr;
00113     ULONG Size;
00114 } PERIODICFRAMELIST, *PPERIODICFRAMELIST;
00115 
00116 //
00117 // QUEUE ELEMENT TRANSFER DESCRIPTOR TOKEN
00118 //
00119 typedef struct _QETD_TOKEN_BITS
00120 {
00121     ULONG PingState:1;
00122     ULONG SplitTransactionState:1;
00123     ULONG MissedMicroFrame:1;
00124     ULONG TransactionError:1;
00125     ULONG BabbleDetected:1;
00126     ULONG DataBufferError:1;
00127     ULONG Halted:1;
00128     ULONG Active:1;
00129     ULONG PIDCode:2;
00130     ULONG ErrorCounter:2;
00131     ULONG CurrentPage:3;
00132     ULONG InterruptOnComplete:1;
00133     ULONG TotalBytesToTransfer:15;
00134     ULONG DataToggle:1;
00135 } QETD_TOKEN_BITS, *PQETD_TOKEN_BITS;
00136 
00137 //
00138 // QUEUE ELEMENT TRANSFER DESCRIPTOR
00139 //
00140 typedef struct _QUEUE_TRANSFER_DESCRIPTOR
00141 {
00142     //Hardware
00143     ULONG NextPointer;
00144     ULONG AlternateNextPointer;
00145     union
00146     {
00147         QETD_TOKEN_BITS Bits;
00148         ULONG DWord;
00149     } Token;
00150     ULONG BufferPointer[5];
00151     ULONG ExtendedBufferPointer[5];
00152 
00153     //Software
00154     ULONG PhysicalAddr;
00155     LIST_ENTRY DescriptorEntry;
00156     ULONG TotalBytesToTransfer;
00157 } QUEUE_TRANSFER_DESCRIPTOR, *PQUEUE_TRANSFER_DESCRIPTOR;
00158 
00159 C_ASSERT(FIELD_OFFSET(QUEUE_TRANSFER_DESCRIPTOR, PhysicalAddr) == 0x34);
00160 
00161 //
00162 // EndPointSpeeds Flags and END_POINT_CHARACTERISTICS
00163 //
00164 #define QH_ENDPOINT_FULLSPEED       0x00
00165 #define QH_ENDPOINT_LOWSPEED        0x01
00166 #define QH_ENDPOINT_HIGHSPEED       0x02
00167 typedef struct _END_POINT_CHARACTERISTICS
00168 {
00169     ULONG DeviceAddress:7;
00170     ULONG InactiveOnNextTransaction:1;
00171     ULONG EndPointNumber:4;
00172     ULONG EndPointSpeed:2;
00173     ULONG QEDTDataToggleControl:1;
00174     ULONG HeadOfReclamation:1;
00175     ULONG MaximumPacketLength:11;
00176     ULONG ControlEndPointFlag:1;
00177     ULONG NakCountReload:4;
00178 } END_POINT_CHARACTERISTICS, *PEND_POINT_CHARACTERISTICS;
00179 
00180 //
00181 // Capabilities
00182 //
00183 typedef struct _END_POINT_CAPABILITIES
00184 {
00185     ULONG InterruptScheduleMask:8;
00186     ULONG SplitCompletionMask:8;
00187     ULONG HubAddr:6;
00188     ULONG PortNumber:6;
00189     ULONG NumberOfTransactionPerFrame:2;
00190 } END_POINT_CAPABILITIES, *PEND_POINT_CAPABILITIES;
00191 
00192 //
00193 // QUEUE HEAD Flags and Struct
00194 //
00195 #define QH_TYPE_IDT             0x00
00196 #define QH_TYPE_QH              0x02
00197 #define QH_TYPE_SITD            0x04
00198 #define QH_TYPE_FSTN            0x06
00199 
00200 typedef struct _QUEUE_HEAD
00201 {
00202     //Hardware
00203     ULONG HorizontalLinkPointer;
00204     END_POINT_CHARACTERISTICS EndPointCharacteristics;
00205     END_POINT_CAPABILITIES EndPointCapabilities;
00206     // TERMINATE_POINTER not valid for this member
00207     ULONG CurrentLinkPointer;
00208     // TERMINATE_POINTER valid
00209     ULONG NextPointer;
00210     // TERMINATE_POINTER valid, bits 1:4 is NAK_COUNTERd
00211     ULONG AlternateNextPointer;
00212     // Only DataToggle, InterruptOnComplete, ErrorCounter, PingState valid
00213     union
00214     {
00215         QETD_TOKEN_BITS Bits;
00216         ULONG DWord;
00217     } Token;
00218     ULONG BufferPointer[5];
00219     ULONG ExtendedBufferPointer[5];
00220 
00221     //Software
00222     ULONG PhysicalAddr;
00223     LIST_ENTRY LinkedQueueHeads;
00224     LIST_ENTRY TransferDescriptorListHead;
00225     PVOID NextQueueHead;
00226     PVOID Request;
00227 } QUEUE_HEAD, *PQUEUE_HEAD;
00228 
00229 C_ASSERT(sizeof(END_POINT_CHARACTERISTICS) == 4);
00230 C_ASSERT(sizeof(END_POINT_CAPABILITIES) == 4);
00231 
00232 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, HorizontalLinkPointer) == 0x00);
00233 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, EndPointCharacteristics) == 0x04);
00234 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, EndPointCapabilities) == 0x08);
00235 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, CurrentLinkPointer) == 0xC);
00236 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, NextPointer) == 0x10);
00237 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, AlternateNextPointer) == 0x14);
00238 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, Token) == 0x18);
00239 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, BufferPointer) == 0x1C);
00240 C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, PhysicalAddr) == 0x44);
00241 
00242 
00243 //
00244 // Command register content
00245 //
00246 typedef struct _EHCI_USBCMD_CONTENT
00247 {
00248     ULONG Run : 1;
00249     ULONG HCReset : 1;
00250     ULONG FrameListSize : 2;
00251     ULONG PeriodicEnable : 1;
00252     ULONG AsyncEnable : 1;
00253     ULONG DoorBell : 1;
00254     ULONG LightReset : 1;
00255     ULONG AsyncParkCount : 2;
00256     ULONG Reserved : 1;
00257     ULONG AsyncParkEnable : 1;
00258     ULONG Reserved1 : 4;
00259     ULONG IntThreshold : 8;
00260     ULONG Reserved2 : 8;
00261 } EHCI_USBCMD_CONTENT, *PEHCI_USBCMD_CONTENT;
00262 
00263 typedef struct _EHCI_HCS_CONTENT
00264 {
00265     ULONG PortCount : 4;
00266     ULONG PortPowerControl: 1;
00267     ULONG Reserved : 2;
00268     ULONG PortRouteRules : 1;
00269     ULONG PortPerCHC : 4;
00270     ULONG CHCCount : 4;
00271     ULONG PortIndicator : 1;
00272     ULONG Reserved2 : 3;
00273     ULONG DbgPortNum : 4;
00274     ULONG Reserved3 : 8;
00275 
00276 } EHCI_HCS_CONTENT, *PEHCI_HCS_CONTENT;
00277 
00278 typedef struct _EHCI_HCC_CONTENT
00279 {
00280     ULONG CurAddrBits : 1;
00281     ULONG VarFrameList : 1;
00282     ULONG ParkMode : 1;
00283     ULONG Reserved : 1;
00284     ULONG IsoSchedThreshold : 4;
00285     ULONG EECPCapable : 8;
00286     ULONG Reserved2 : 16;
00287 
00288 } EHCI_HCC_CONTENT, *PEHCI_HCC_CONTENT;
00289 
00290 typedef struct _EHCI_CAPS {
00291     UCHAR Length;
00292     UCHAR Reserved;
00293     USHORT HCIVersion;
00294     union
00295     {
00296         EHCI_HCS_CONTENT HCSParams;
00297         ULONG HCSParamsLong;
00298     };
00299     union
00300     {
00301         EHCI_HCC_CONTENT HCCParams;
00302         ULONG HCCParamsLong;
00303     };
00304     UCHAR PortRoute [15];
00305 } EHCI_CAPS, *PEHCI_CAPS;
00306 
00307 typedef struct
00308 {
00309     ULONG PortStatus;
00310     ULONG PortChange;
00311 }EHCI_PORT_STATUS;
00312 
00313 #define EHCI_INTERRUPT_ENTRIES_COUNT    (10 + 1)
00314 #define EHCI_VFRAMELIST_ENTRIES_COUNT    128
00315 #define EHCI_FRAMELIST_ENTRIES_COUNT     1024
00316 
00317 #define MAX_AVAILABLE_BANDWIDTH 125 // Microseconds
00318 
00319 #define EHCI_QH_CAPS_MULT_SHIFT 30          // Transactions per Micro-Frame
00320 #define EHCI_QH_CAPS_MULT_MASK 0x03
00321 #define EHCI_QH_CAPS_PORT_SHIFT 23          // Hub Port (Split-Transaction)
00322 #define EHCI_QH_CAPS_PORT_MASK 0x7f
00323 #define EHCI_QH_CAPS_HUB_SHIFT 16           // Hub Address (Split-Transaction)
00324 #define EHCI_QH_CAPS_HUB_MASK  0x7f
00325 #define EHCI_QH_CAPS_SCM_SHIFT  8           // Split Completion Mask
00326 #define EHCI_QH_CAPS_SCM_MASK   0xff
00327 #define EHCI_QH_CAPS_ISM_SHIFT  0           // Interrupt Schedule Mask
00328 #define EHCI_QH_CAPS_ISM_MASK  0xff
Generated on Sun May 27 2012 04:19:13 for ReactOS by doxygen 1.7.6.1
ReactOS is a registered trademark or a trademark of ReactOS Foundation in the United States and other countries.