ReactOS 0.4.15-dev-7842-g558ab78
mm.h
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1/*
2 * kernel internal memory management definitions for x86
3 */
4#pragma once
5
6#ifdef _X86PAE_
7#define _MI_PAGING_LEVELS 3
8#define _MI_HAS_NO_EXECUTE 1
9#else
10#define _MI_PAGING_LEVELS 2
11#define _MI_HAS_NO_EXECUTE 0
12#endif
13
14/* Memory layout base addresses */
15#define MI_USER_PROBE_ADDRESS (PVOID)0x7FFF0000
16#define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0x80000000
17#ifndef _X86PAE_
18#define HYPER_SPACE 0xC0400000
19#define HYPER_SPACE_END 0xC07FFFFF
20#else
21#define HYPER_SPACE 0xC0800000
22#define HYPER_SPACE_END 0xC0BFFFFF
23#endif
24#define MI_SYSTEM_CACHE_WS_START (PVOID)0xC0C00000
25#define MI_SYSTEM_CACHE_START (PVOID)0xC1000000
26#define MI_PAGED_POOL_START (PVOID)0xE1000000
27#define MI_NONPAGED_POOL_END (PVOID)0xFFBE0000
28#define MI_DEBUG_MAPPING (PVOID)0xFFBFF000
29#define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFF
30
31/* Misc address definitions */
32#define MM_HIGHEST_VAD_ADDRESS \
33 (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
34#define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE
35#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
36 MI_HYPERSPACE_PTES * PAGE_SIZE)
37#define MI_DUMMY_PTE (PMMPTE)((ULONG_PTR)MI_MAPPING_RANGE_END + \
38 PAGE_SIZE)
39#define MI_VAD_BITMAP (PMMPTE)((ULONG_PTR)MI_DUMMY_PTE + \
40 PAGE_SIZE)
41#define MI_WORKING_SET_LIST (PMMPTE)((ULONG_PTR)MI_VAD_BITMAP + \
42 PAGE_SIZE)
43
44/* Memory sizes */
45#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT)
46#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT)
47#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT)
48#define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT)
49#define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB)
50#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128 * _1MB)
51#define MI_MAX_NONPAGED_POOL_SIZE (128 * _1MB)
52#define MI_SYSTEM_VIEW_SIZE (32 * _1MB)
53#define MI_SESSION_VIEW_SIZE (48 * _1MB)
54#define MI_SESSION_POOL_SIZE (16 * _1MB)
55#define MI_SESSION_IMAGE_SIZE (8 * _1MB)
56#define MI_SESSION_WORKING_SET_SIZE (4 * _1MB)
57#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
58 MI_SESSION_POOL_SIZE + \
59 MI_SESSION_IMAGE_SIZE + \
60 MI_SESSION_WORKING_SET_SIZE)
61#define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
62#define MI_ALLOCATION_FRAGMENT (64 * _1KB)
63#define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
64
65/* Misc constants */
66#define MM_PTE_SOFTWARE_PROTECTION_BITS 5
67#define MI_MIN_SECONDARY_COLORS 8
68#define MI_SECONDARY_COLORS 64
69#define MI_MAX_SECONDARY_COLORS 1024
70#define MI_MAX_FREE_PAGE_LISTS 4
71#define MI_HYPERSPACE_PTES (256 - 1)
72#define MI_ZERO_PTES (32)
73#define MI_MAX_ZERO_BITS 21
74#define SESSION_POOL_LOOKASIDES 26
75
76/* MMPTE related defines */
77#define MM_EMPTY_PTE_LIST ((ULONG)0xFFFFF)
78#define MM_EMPTY_LIST ((ULONG_PTR)-1)
79
80
81/* Easy accessing PFN in PTE */
82#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
83
84/* Macros for portable PTE modification */
85#define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
86#define MI_MAKE_CLEAN_PAGE(x) ((x)->u.Hard.Dirty = 0)
87#define MI_MAKE_ACCESSED_PAGE(x) ((x)->u.Hard.Accessed = 1)
88#define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1)
89#define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1)
90#define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0)
91#define MI_IS_PAGE_LARGE(x) ((x)->u.Hard.LargePage == 1)
92#if !defined(CONFIG_SMP)
93#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
94#else
95#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1)
96#endif
97#define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
98#ifdef _X86PAE_
99#define MI_IS_PAGE_EXECUTABLE(x) ((x)->u.Hard.NoExecute == 0)
100#else
101#define MI_IS_PAGE_EXECUTABLE(x) TRUE
102#endif
103#define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1)
104#define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
105#if !defined(CONFIG_SMP)
106#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1)
107#else
108#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
109#endif
110
111
112/* Macros to identify the page fault reason from the error code */
113#define MI_IS_NOT_PRESENT_FAULT(FaultCode) !BooleanFlagOn(FaultCode, 0x00000001)
114#define MI_IS_WRITE_ACCESS(FaultCode) BooleanFlagOn(FaultCode, 0x00000002)
115// 0x00000004: user-mode access.
116// 0x00000008: reserved bit violation.
117#define MI_IS_INSTRUCTION_FETCH(FaultCode) BooleanFlagOn(FaultCode, 0x00000010)
118// 0x00000020: protection-key violation.
119// 0x00000040: shadow-stack access.
120// Bits 7-14: reserved.
121// 0x00008000: violation of SGX-specific access-control requirements.
122// Bits 16-31: reserved.
123
124/* On x86, these two are the same */
125#define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE
126
127/* Translating virtual addresses to physical addresses
128 (See: "Intel® 64 and IA-32 Architectures Software Developer’s Manual
129 Volume 3A: System Programming Guide, Part 1, CHAPTER 4 PAGING")
130 Page directory (PD) and Page table (PT) definitions
131 Page directory entry (PDE) and Page table entry (PTE) definitions
132*/
133
134/* Maximum number of page directories pages */
135#ifndef _X86PAE_
136#define PD_COUNT 1 /* Only one page directory page */
137#else
138#define PD_COUNT (1 << 2) /* The two most significant bits in the VA */
139#endif
140
141/* PAE not yet implemented. */
143
144/* The number of PTEs on one page of the PT */
145#define PTE_PER_PAGE (PAGE_SIZE / sizeof(MMPTE))
146
147/* The number of PDEs on one page of the PD */
148#define PDE_PER_PAGE (PAGE_SIZE / sizeof(MMPDE))
149
150/* Maximum number of PDEs */
151#define PDE_PER_SYSTEM (PD_COUNT * PDE_PER_PAGE)
152
153/* TODO: It seems this constant is not needed for x86 */
154#define PPE_PER_PAGE 1
155
156/* Maximum number of pages for 4 GB of virtual space */
157#define MI_MAX_PAGES ((1ull << 32) / PAGE_SIZE)
158
159/* Base addresses for page tables */
160#define PTE_BASE (ULONG_PTR)0xC0000000
161#define PTE_TOP (ULONG_PTR)(PTE_BASE + (MI_MAX_PAGES * sizeof(MMPTE)) - 1)
162#define PTE_MASK (PTE_TOP - PTE_BASE)
163
164#define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(NULL)
165
166/* Base addreses for page directories */
167#define PDE_BASE (ULONG_PTR)MiPteToPde(PTE_BASE)
168#define PDE_TOP (ULONG_PTR)(PDE_BASE + (PDE_PER_SYSTEM * sizeof(MMPDE)) - 1)
169#define PDE_MASK (PDE_TOP - PDE_BASE)
170
171/* The size of the virtual memory area that is mapped using a single PDE */
172#define PDE_MAPPED_VA (PTE_PER_PAGE * PAGE_SIZE)
173
174/* Maps the virtual address to the corresponding PTE */
175#define MiAddressToPte(Va) \
176 ((PMMPTE)(PTE_BASE + ((((ULONG_PTR)(Va)) / PAGE_SIZE) * sizeof(MMPTE))))
177
178/* Maps the virtual address to the corresponding PDE */
179#define MiAddressToPde(Va) \
180 ((PMMPDE)(PDE_BASE + ((MiAddressToPdeOffset(Va)) * sizeof(MMPDE))))
181
182/* Takes the PTE index (for one PD page) from the virtual address */
183#define MiAddressToPteOffset(Va) \
184 ((((ULONG_PTR)(Va)) & (PDE_MAPPED_VA - 1)) / PAGE_SIZE)
185
186/* Takes the PDE offset (within all PDs pages) from the virtual address */
187#define MiAddressToPdeOffset(Va) (((ULONG_PTR)(Va)) / PDE_MAPPED_VA)
188
189/* TODO: Free this variable (for offset from the pointer to the PDE) */
190#define MiGetPdeOffset MiAddressToPdeOffset
191
192/* Convert a PTE/PDE into a corresponding address */
193#define MiPteToAddress(_Pte) ((PVOID)((ULONG)(_Pte) << 10))
194#define MiPdeToAddress(_Pde) ((PVOID)((ULONG)(_Pde) << 20))
195
196/* Translate between P*Es */
197#define MiPdeToPte(_Pde) ((PMMPTE)MiPteToAddress(_Pde))
198#define MiPteToPde(_Pte) ((PMMPDE)MiAddressToPte(_Pte))
199
200/* Check P*E boundaries */
201#define MiIsPteOnPdeBoundary(PointerPte) \
202 ((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
203
204//
205// Decodes a Prototype PTE into the underlying PTE
206//
207#define MiProtoPteToPte(x) \
208 (PMMPTE)((ULONG_PTR)MmPagedPoolStart + \
209 (((x)->u.Proto.ProtoAddressHigh << 9) | (x)->u.Proto.ProtoAddressLow << 2))
210
211//
212// Decodes a Prototype PTE into the underlying PTE
213//
214#define MiSubsectionPteToSubsection(x) \
215 ((x)->u.Subsect.WhichPool == PagedPool) ? \
216 (PMMPTE)((ULONG_PTR)MmSubsectionBase + \
217 (((x)->u.Subsect.SubsectionAddressHigh << 7) | \
218 (x)->u.Subsect.SubsectionAddressLow << 3)) : \
219 (PMMPTE)((ULONG_PTR)MmNonPagedPoolEnd - \
220 (((x)->u.Subsect.SubsectionAddressHigh << 7) | \
221 (x)->u.Subsect.SubsectionAddressLow << 3))
#define C_ASSERT(e)
Definition: intsafe.h:73
#define PD_COUNT
Definition: mm.h:136