ReactOS
0.4.16-dev-197-g92996da
mm.h
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/*
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* kernel internal memory management definitions for x86
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*/
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#pragma once
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#ifdef _X86PAE_
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#define _MI_PAGING_LEVELS 3
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#define _MI_HAS_NO_EXECUTE 1
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#else
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#define _MI_PAGING_LEVELS 2
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#define _MI_HAS_NO_EXECUTE 0
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#endif
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/* Memory layout base addresses */
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#define MI_USER_PROBE_ADDRESS (PVOID)0x7FFF0000
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#define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0x80000000
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#ifndef _X86PAE_
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#define HYPER_SPACE 0xC0400000
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#define HYPER_SPACE_END 0xC07FFFFF
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#else
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#define HYPER_SPACE 0xC0800000
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#define HYPER_SPACE_END 0xC0BFFFFF
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#endif
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#define MI_SYSTEM_CACHE_WS_START (PVOID)0xC0C00000
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#define MI_SYSTEM_CACHE_START (PVOID)0xC1000000
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#define MI_PAGED_POOL_START (PVOID)0xE1000000
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#define MI_NONPAGED_POOL_END (PVOID)0xFFBE0000
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#define MI_DEBUG_MAPPING (PVOID)0xFFBFF000
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#define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFF
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/* Misc address definitions */
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#define MM_HIGHEST_VAD_ADDRESS \
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(PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
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#define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE
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#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
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MI_HYPERSPACE_PTES * PAGE_SIZE)
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#define MI_DUMMY_PTE (PMMPTE)((ULONG_PTR)MI_MAPPING_RANGE_END + \
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PAGE_SIZE)
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#define MI_VAD_BITMAP (PMMPTE)((ULONG_PTR)MI_DUMMY_PTE + \
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PAGE_SIZE)
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#define MI_WORKING_SET_LIST (PMMPTE)((ULONG_PTR)MI_VAD_BITMAP + \
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PAGE_SIZE)
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/* Memory sizes */
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#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT)
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#define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB)
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#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128 * _1MB)
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#define MI_MAX_NONPAGED_POOL_SIZE (128 * _1MB)
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#define MI_SYSTEM_VIEW_SIZE (32 * _1MB)
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#define MI_SESSION_VIEW_SIZE (48 * _1MB)
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#define MI_SESSION_POOL_SIZE (16 * _1MB)
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#define MI_SESSION_IMAGE_SIZE (8 * _1MB)
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#define MI_SESSION_WORKING_SET_SIZE (4 * _1MB)
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#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
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MI_SESSION_POOL_SIZE + \
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MI_SESSION_IMAGE_SIZE + \
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MI_SESSION_WORKING_SET_SIZE)
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#define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
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#define MI_ALLOCATION_FRAGMENT (64 * _1KB)
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#define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
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/* Misc constants */
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#define MM_PTE_SOFTWARE_PROTECTION_BITS 5
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#define MI_MIN_SECONDARY_COLORS 8
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#define MI_SECONDARY_COLORS 64
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#define MI_MAX_SECONDARY_COLORS 1024
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#define MI_MAX_FREE_PAGE_LISTS 4
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#define MI_HYPERSPACE_PTES (256 - 1)
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#define MI_ZERO_PTES (32)
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#define MI_MAX_ZERO_BITS 21
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#define SESSION_POOL_LOOKASIDES 26
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/* MMPTE related defines */
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#define MM_EMPTY_PTE_LIST ((ULONG)0xFFFFF)
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#define MM_EMPTY_LIST ((ULONG_PTR)-1)
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/* Easy accessing PFN in PTE */
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#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
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/* Macros for portable PTE modification */
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#define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
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#define MI_MAKE_CLEAN_PAGE(x) ((x)->u.Hard.Dirty = 0)
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#define MI_MAKE_ACCESSED_PAGE(x) ((x)->u.Hard.Accessed = 1)
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#define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1)
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#define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1)
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#define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0)
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#define MI_IS_PAGE_LARGE(x) ((x)->u.Hard.LargePage == 1)
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#if !defined(CONFIG_SMP)
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#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
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#else
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#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1)
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#endif
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#define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
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#ifdef _X86PAE_
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#define MI_IS_PAGE_EXECUTABLE(x) ((x)->u.Hard.NoExecute == 0)
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#else
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#define MI_IS_PAGE_EXECUTABLE(x) TRUE
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#endif
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#define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1)
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#define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
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#if !defined(CONFIG_SMP)
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#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1)
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#else
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#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
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#endif
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/* Macros to identify the page fault reason from the error code */
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#define MI_IS_NOT_PRESENT_FAULT(FaultCode) !BooleanFlagOn(FaultCode, 0x00000001)
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#define MI_IS_WRITE_ACCESS(FaultCode) BooleanFlagOn(FaultCode, 0x00000002)
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// 0x00000004: user-mode access.
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// 0x00000008: reserved bit violation.
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#define MI_IS_INSTRUCTION_FETCH(FaultCode) BooleanFlagOn(FaultCode, 0x00000010)
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// 0x00000020: protection-key violation.
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// 0x00000040: shadow-stack access.
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// Bits 7-14: reserved.
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// 0x00008000: violation of SGX-specific access-control requirements.
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// Bits 16-31: reserved.
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/* On x86, these two are the same */
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#define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE
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/* Translating virtual addresses to physical addresses
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(See: "Intel® 64 and IA-32 Architectures Software Developer’s Manual
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Volume 3A: System Programming Guide, Part 1, CHAPTER 4 PAGING")
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Page directory (PD) and Page table (PT) definitions
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Page directory entry (PDE) and Page table entry (PTE) definitions
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*/
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/* Maximum number of page directories pages */
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#ifndef _X86PAE_
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#define PD_COUNT 1
/* Only one page directory page */
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#else
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#define PD_COUNT (1 << 2)
/* The two most significant bits in the VA */
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#endif
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/* PAE not yet implemented. */
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C_ASSERT
(
PD_COUNT
== 1);
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/* The number of PTEs on one page of the PT */
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#define PTE_PER_PAGE (PAGE_SIZE / sizeof(MMPTE))
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/* The number of PDEs on one page of the PD */
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#define PDE_PER_PAGE (PAGE_SIZE / sizeof(MMPDE))
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/* Maximum number of PDEs */
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#define PDE_PER_SYSTEM (PD_COUNT * PDE_PER_PAGE)
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/* TODO: It seems this constant is not needed for x86 */
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#define PPE_PER_PAGE 1
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/* Maximum number of pages for 4 GB of virtual space */
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#define MI_MAX_PAGES ((1ull << 32) / PAGE_SIZE)
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/* Base addresses for page tables */
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#define PTE_BASE (ULONG_PTR)0xC0000000
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#define PTE_TOP (ULONG_PTR)(PTE_BASE + (MI_MAX_PAGES * sizeof(MMPTE)) - 1)
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#define PTE_MASK (PTE_TOP - PTE_BASE)
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#define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(NULL)
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/* Base addreses for page directories */
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#define PDE_BASE (ULONG_PTR)MiPteToPde(PTE_BASE)
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#define PDE_TOP (ULONG_PTR)(PDE_BASE + (PDE_PER_SYSTEM * sizeof(MMPDE)) - 1)
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#define PDE_MASK (PDE_TOP - PDE_BASE)
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/* The size of the virtual memory area that is mapped using a single PDE */
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#define PDE_MAPPED_VA (PTE_PER_PAGE * PAGE_SIZE)
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/* Maps the virtual address to the corresponding PTE */
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#define MiAddressToPte(Va) \
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((PMMPTE)(PTE_BASE + ((((ULONG_PTR)(Va)) / PAGE_SIZE) * sizeof(MMPTE))))
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/* Maps the virtual address to the corresponding PDE */
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#define MiAddressToPde(Va) \
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((PMMPDE)(PDE_BASE + ((MiAddressToPdeOffset(Va)) * sizeof(MMPDE))))
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/* Takes the PTE index (for one PD page) from the virtual address */
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#define MiAddressToPteOffset(Va) \
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((((ULONG_PTR)(Va)) & (PDE_MAPPED_VA - 1)) / PAGE_SIZE)
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/* Takes the PDE offset (within all PDs pages) from the virtual address */
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#define MiAddressToPdeOffset(Va) (((ULONG_PTR)(Va)) / PDE_MAPPED_VA)
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/* TODO: Free this variable (for offset from the pointer to the PDE) */
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#define MiGetPdeOffset MiAddressToPdeOffset
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/* Convert a PTE/PDE into a corresponding address */
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#define MiPteToAddress(_Pte) ((PVOID)((ULONG)(_Pte) << 10))
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#define MiPdeToAddress(_Pde) ((PVOID)((ULONG)(_Pde) << 20))
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/* Translate between P*Es */
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#define MiPdeToPte(_Pde) ((PMMPTE)MiPteToAddress(_Pde))
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#define MiPteToPde(_Pte) ((PMMPDE)MiAddressToPte(_Pte))
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/* Check P*E boundaries */
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#define MiIsPteOnPdeBoundary(PointerPte) \
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((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
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//
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// Decodes a Prototype PTE into the underlying PTE
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//
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#define MiProtoPteToPte(x) \
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(PMMPTE)((ULONG_PTR)MmPagedPoolStart + \
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(((x)->u.Proto.ProtoAddressHigh << 9) | (x)->u.Proto.ProtoAddressLow << 2))
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//
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// Decodes a Prototype PTE into the underlying PTE
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//
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#define MiSubsectionPteToSubsection(x) \
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((x)->u.Subsect.WhichPool == PagedPool) ? \
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(PMMPTE)((ULONG_PTR)MmSubsectionBase + \
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(((x)->u.Subsect.SubsectionAddressHigh << 7) | \
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(x)->u.Subsect.SubsectionAddressLow << 3)) : \
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(PMMPTE)((ULONG_PTR)MmNonPagedPoolEnd - \
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(((x)->u.Subsect.SubsectionAddressHigh << 7) | \
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(x)->u.Subsect.SubsectionAddressLow << 3))
C_ASSERT
#define C_ASSERT(e)
Definition:
intsafe.h:73
PD_COUNT
#define PD_COUNT
Definition:
mm.h:136
ntoskrnl
include
internal
i386
mm.h
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