ReactOS  0.4.14-dev-342-gdc047f9
mm.h
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1 /*
2  * kernel internal memory management definitions for x86
3  */
4 #pragma once
5 
6 #ifdef _PAE_
7 #define _MI_PAGING_LEVELS 3
8 #define _MI_HAS_NO_EXECUTE 1
9 #else
10 #define _MI_PAGING_LEVELS 2
11 #define _MI_HAS_NO_EXECUTE 0
12 #endif
13 
14 /* Memory layout base addresses */
15 #define MI_USER_PROBE_ADDRESS (PVOID)0x7FFF0000
16 #define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0x80000000
17 #ifndef PAE
18 #define HYPER_SPACE 0xC0400000
19 #define HYPER_SPACE_END 0xC07FFFFF
20 #else
21 #define HYPER_SPACE 0xC0800000
22 #define HYPER_SPACE_END 0xC0BFFFFF
23 #endif
24 #define MI_SYSTEM_CACHE_WS_START (PVOID)0xC0C00000
25 #define MI_SYSTEM_CACHE_START (PVOID)0xC1000000
26 #define MI_PAGED_POOL_START (PVOID)0xE1000000
27 #define MI_NONPAGED_POOL_END (PVOID)0xFFBE0000
28 #define MI_DEBUG_MAPPING (PVOID)0xFFBFF000
29 #define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFF
30 
31 /* FIXME: These are different for PAE */
32 #define PTE_BASE 0xC0000000
33 #define PDE_BASE 0xC0300000
34 #define PDE_TOP 0xC0300FFF
35 #define PTE_TOP 0xC03FFFFF
36 
37 #define PTE_PER_PAGE 0x400
38 #define PDE_PER_PAGE 0x400
39 #define PPE_PER_PAGE 1
40 
41 /* Misc address definitions */
42 #define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(NULL)
43 #define MM_HIGHEST_VAD_ADDRESS \
44  (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
45 #define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE
46 #define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
47  MI_HYPERSPACE_PTES * PAGE_SIZE)
48 #define MI_DUMMY_PTE (PMMPTE)((ULONG_PTR)MI_MAPPING_RANGE_END + \
49  PAGE_SIZE)
50 #define MI_VAD_BITMAP (PMMPTE)((ULONG_PTR)MI_DUMMY_PTE + \
51  PAGE_SIZE)
52 #define MI_WORKING_SET_LIST (PMMPTE)((ULONG_PTR)MI_VAD_BITMAP + \
53  PAGE_SIZE)
54 
55 /* Memory sizes */
56 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT)
57 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT)
58 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT)
59 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT)
60 #define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB)
61 #define MI_MAX_INIT_NONPAGED_POOL_SIZE (128 * _1MB)
62 #define MI_MAX_NONPAGED_POOL_SIZE (128 * _1MB)
63 #define MI_SYSTEM_VIEW_SIZE (32 * _1MB)
64 #define MI_SESSION_VIEW_SIZE (48 * _1MB)
65 #define MI_SESSION_POOL_SIZE (16 * _1MB)
66 #define MI_SESSION_IMAGE_SIZE (8 * _1MB)
67 #define MI_SESSION_WORKING_SET_SIZE (4 * _1MB)
68 #define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
69  MI_SESSION_POOL_SIZE + \
70  MI_SESSION_IMAGE_SIZE + \
71  MI_SESSION_WORKING_SET_SIZE)
72 #define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
73 #define MI_ALLOCATION_FRAGMENT (64 * _1KB)
74 #define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
75 
76 /* Misc constants */
77 #define MM_PTE_SOFTWARE_PROTECTION_BITS 5
78 #define MI_MIN_SECONDARY_COLORS 8
79 #define MI_SECONDARY_COLORS 64
80 #define MI_MAX_SECONDARY_COLORS 1024
81 #define MI_MAX_FREE_PAGE_LISTS 4
82 #define MI_HYPERSPACE_PTES (256 - 1)
83 #define MI_ZERO_PTES (32)
84 #define MI_MAX_ZERO_BITS 21
85 #define SESSION_POOL_LOOKASIDES 26
86 
87 /* MMPTE related defines */
88 #define MM_EMPTY_PTE_LIST ((ULONG)0xFFFFF)
89 #define MM_EMPTY_LIST ((ULONG_PTR)-1)
90 
91 
92 /* Easy accessing PFN in PTE */
93 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
94 
95 /* Macros for portable PTE modification */
96 #define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
97 #define MI_MAKE_CLEAN_PAGE(x) ((x)->u.Hard.Dirty = 0)
98 #define MI_MAKE_ACCESSED_PAGE(x) ((x)->u.Hard.Accessed = 1)
99 #define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1)
100 #define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1)
101 #define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0)
102 #define MI_IS_PAGE_LARGE(x) ((x)->u.Hard.LargePage == 1)
103 #if !defined(CONFIG_SMP)
104 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
105 #else
106 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1)
107 #endif
108 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
109 #ifdef _PAE_
110 #define MI_IS_PAGE_EXECUTABLE(x) ((x)->u.Hard.NoExecute == 0)
111 #else
112 #define MI_IS_PAGE_EXECUTABLE(x) TRUE
113 #endif
114 #define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1)
115 #define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
116 #if !defined(CONFIG_SMP)
117 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1)
118 #else
119 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
120 #endif
121 
122 
123 /* Macros to identify the page fault reason from the error code */
124 #define MI_IS_NOT_PRESENT_FAULT(FaultCode) !BooleanFlagOn(FaultCode, 0x1)
125 #define MI_IS_WRITE_ACCESS(FaultCode) BooleanFlagOn(FaultCode, 0x2)
126 #define MI_IS_INSTRUCTION_FETCH(FaultCode) BooleanFlagOn(FaultCode, 0x10)
127 
128 /* On x86, these two are the same */
129 #define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE
130 
131 /* Convert an address to a corresponding PTE */
132 #define MiAddressToPte(x) \
133  ((PMMPTE)(((((ULONG)(x)) >> 12) << 2) + PTE_BASE))
134 
135 /* Convert an address to a corresponding PDE */
136 #define MiAddressToPde(x) \
137  ((PMMPDE)(((((ULONG)(x)) >> 22) << 2) + PDE_BASE))
138 
139 /* Convert an address to a corresponding PTE offset/index */
140 #define MiAddressToPteOffset(x) \
141  ((((ULONG)(x)) << 10) >> 22)
142 
143 /* Convert an address to a corresponding PDE offset/index */
144 #define MiAddressToPdeOffset(x) \
145  (((ULONG)(x)) / (1024 * PAGE_SIZE))
146 #define MiGetPdeOffset MiAddressToPdeOffset
147 
148 /* Convert a PTE/PDE into a corresponding address */
149 #define MiPteToAddress(_Pte) ((PVOID)((ULONG)(_Pte) << 10))
150 #define MiPdeToAddress(_Pde) ((PVOID)((ULONG)(_Pde) << 20))
151 
152 /* Translate between P*Es */
153 #define MiPdeToPte(_Pde) ((PMMPTE)MiPteToAddress(_Pde))
154 #define MiPteToPde(_Pte) ((PMMPDE)MiAddressToPte(_Pte))
155 
156 /* Check P*E boundaries */
157 #define MiIsPteOnPdeBoundary(PointerPte) \
158  ((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
159 
160 //
161 // Decodes a Prototype PTE into the underlying PTE
162 //
163 #define MiProtoPteToPte(x) \
164  (PMMPTE)((ULONG_PTR)MmPagedPoolStart + \
165  (((x)->u.Proto.ProtoAddressHigh << 9) | (x)->u.Proto.ProtoAddressLow << 2))
166 
167 //
168 // Decodes a Prototype PTE into the underlying PTE
169 //
170 #define MiSubsectionPteToSubsection(x) \
171  ((x)->u.Subsect.WhichPool == PagedPool) ? \
172  (PMMPTE)((ULONG_PTR)MmSubsectionBase + \
173  (((x)->u.Subsect.SubsectionAddressHigh << 7) | \
174  (x)->u.Subsect.SubsectionAddressLow << 3)) : \
175  (PMMPTE)((ULONG_PTR)MmNonPagedPoolEnd - \
176  (((x)->u.Subsect.SubsectionAddressHigh << 7) | \
177  (x)->u.Subsect.SubsectionAddressLow << 3))