ReactOS  0.4.15-dev-313-g8fde48b
mm.h
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1 /*
2  * kernel internal memory management definitions for x86
3  */
4 #pragma once
5 
6 #ifdef _X86PAE_
7 #define _MI_PAGING_LEVELS 3
8 #define _MI_HAS_NO_EXECUTE 1
9 #else
10 #define _MI_PAGING_LEVELS 2
11 #define _MI_HAS_NO_EXECUTE 0
12 #endif
13 
14 /* Memory layout base addresses */
15 #define MI_USER_PROBE_ADDRESS (PVOID)0x7FFF0000
16 #define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0x80000000
17 #ifndef _X86PAE_
18 #define HYPER_SPACE 0xC0400000
19 #define HYPER_SPACE_END 0xC07FFFFF
20 #else
21 #define HYPER_SPACE 0xC0800000
22 #define HYPER_SPACE_END 0xC0BFFFFF
23 #endif
24 #define MI_SYSTEM_CACHE_WS_START (PVOID)0xC0C00000
25 #define MI_SYSTEM_CACHE_START (PVOID)0xC1000000
26 #define MI_PAGED_POOL_START (PVOID)0xE1000000
27 #define MI_NONPAGED_POOL_END (PVOID)0xFFBE0000
28 #define MI_DEBUG_MAPPING (PVOID)0xFFBFF000
29 #define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFF
30 
31 /* Misc address definitions */
32 #define MM_HIGHEST_VAD_ADDRESS \
33  (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
34 #define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE
35 #define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
36  MI_HYPERSPACE_PTES * PAGE_SIZE)
37 #define MI_DUMMY_PTE (PMMPTE)((ULONG_PTR)MI_MAPPING_RANGE_END + \
38  PAGE_SIZE)
39 #define MI_VAD_BITMAP (PMMPTE)((ULONG_PTR)MI_DUMMY_PTE + \
40  PAGE_SIZE)
41 #define MI_WORKING_SET_LIST (PMMPTE)((ULONG_PTR)MI_VAD_BITMAP + \
42  PAGE_SIZE)
43 
44 /* Memory sizes */
45 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT)
46 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT)
47 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT)
48 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT)
49 #define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB)
50 #define MI_MAX_INIT_NONPAGED_POOL_SIZE (128 * _1MB)
51 #define MI_MAX_NONPAGED_POOL_SIZE (128 * _1MB)
52 #define MI_SYSTEM_VIEW_SIZE (32 * _1MB)
53 #define MI_SESSION_VIEW_SIZE (48 * _1MB)
54 #define MI_SESSION_POOL_SIZE (16 * _1MB)
55 #define MI_SESSION_IMAGE_SIZE (8 * _1MB)
56 #define MI_SESSION_WORKING_SET_SIZE (4 * _1MB)
57 #define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
58  MI_SESSION_POOL_SIZE + \
59  MI_SESSION_IMAGE_SIZE + \
60  MI_SESSION_WORKING_SET_SIZE)
61 #define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
62 #define MI_ALLOCATION_FRAGMENT (64 * _1KB)
63 #define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
64 
65 /* Misc constants */
66 #define MM_PTE_SOFTWARE_PROTECTION_BITS 5
67 #define MI_MIN_SECONDARY_COLORS 8
68 #define MI_SECONDARY_COLORS 64
69 #define MI_MAX_SECONDARY_COLORS 1024
70 #define MI_MAX_FREE_PAGE_LISTS 4
71 #define MI_HYPERSPACE_PTES (256 - 1)
72 #define MI_ZERO_PTES (32)
73 #define MI_MAX_ZERO_BITS 21
74 #define SESSION_POOL_LOOKASIDES 26
75 
76 /* MMPTE related defines */
77 #define MM_EMPTY_PTE_LIST ((ULONG)0xFFFFF)
78 #define MM_EMPTY_LIST ((ULONG_PTR)-1)
79 
80 
81 /* Easy accessing PFN in PTE */
82 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
83 
84 /* Macros for portable PTE modification */
85 #define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
86 #define MI_MAKE_CLEAN_PAGE(x) ((x)->u.Hard.Dirty = 0)
87 #define MI_MAKE_ACCESSED_PAGE(x) ((x)->u.Hard.Accessed = 1)
88 #define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1)
89 #define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1)
90 #define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0)
91 #define MI_IS_PAGE_LARGE(x) ((x)->u.Hard.LargePage == 1)
92 #if !defined(CONFIG_SMP)
93 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
94 #else
95 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1)
96 #endif
97 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
98 #ifdef _X86PAE_
99 #define MI_IS_PAGE_EXECUTABLE(x) ((x)->u.Hard.NoExecute == 0)
100 #else
101 #define MI_IS_PAGE_EXECUTABLE(x) TRUE
102 #endif
103 #define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1)
104 #define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
105 #if !defined(CONFIG_SMP)
106 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1)
107 #else
108 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
109 #endif
110 
111 
112 /* Macros to identify the page fault reason from the error code */
113 #define MI_IS_NOT_PRESENT_FAULT(FaultCode) !BooleanFlagOn(FaultCode, 0x1)
114 #define MI_IS_WRITE_ACCESS(FaultCode) BooleanFlagOn(FaultCode, 0x2)
115 #define MI_IS_INSTRUCTION_FETCH(FaultCode) BooleanFlagOn(FaultCode, 0x10)
116 
117 /* On x86, these two are the same */
118 #define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE
119 
120 /* Translating virtual addresses to physical addresses
121  (See: "Intel® 64 and IA-32 Architectures Software Developer’s Manual
122  Volume 3A: System Programming Guide, Part 1, CHAPTER 4 PAGING")
123  Page directory (PD) and Page table (PT) definitions
124  Page directory entry (PDE) and Page table entry (PTE) definitions
125 */
126 
127 /* Maximum number of page directories pages */
128 #ifndef _X86PAE_
129 #define PD_COUNT 1 /* Only one page directory page */
130 #else
131 #define PD_COUNT (1 << 2) /* The two most significant bits in the VA */
132 #endif
133 
134 /* PAE not yet implemented. */
135 C_ASSERT(PD_COUNT == 1);
136 
137 /* The number of PTEs on one page of the PT */
138 #define PTE_PER_PAGE (PAGE_SIZE / sizeof(MMPTE))
139 
140 /* The number of PDEs on one page of the PD */
141 #define PDE_PER_PAGE (PAGE_SIZE / sizeof(MMPDE))
142 
143 /* Maximum number of PDEs */
144 #define PDE_PER_SYSTEM (PD_COUNT * PDE_PER_PAGE)
145 
146 /* TODO: It seems this constant is not needed for x86 */
147 #define PPE_PER_PAGE 1
148 
149 /* Maximum number of pages for 4 GB of virtual space */
150 #define MI_MAX_PAGES ((1ull << 32) / PAGE_SIZE)
151 
152 /* Base addresses for page tables */
153 #define PTE_BASE (ULONG_PTR)0xC0000000
154 #define PTE_TOP (ULONG_PTR)(PTE_BASE + (MI_MAX_PAGES * sizeof(MMPTE)) - 1)
155 #define PTE_MASK (PTE_TOP - PTE_BASE)
156 
157 #define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(NULL)
158 
159 /* Base addreses for page directories */
160 #define PDE_BASE (ULONG_PTR)MiPteToPde(PTE_BASE)
161 #define PDE_TOP (ULONG_PTR)(PDE_BASE + (PDE_PER_SYSTEM * sizeof(MMPDE)) - 1)
162 #define PDE_MASK (PDE_TOP - PDE_BASE)
163 
164 /* The size of the virtual memory area that is mapped using a single PDE */
165 #define PDE_MAPPED_VA (PTE_PER_PAGE * PAGE_SIZE)
166 
167 /* Maps the virtual address to the corresponding PTE */
168 #define MiAddressToPte(Va) \
169  ((PMMPTE)(PTE_BASE + ((((ULONG_PTR)(Va)) / PAGE_SIZE) * sizeof(MMPTE))))
170 
171 /* Maps the virtual address to the corresponding PDE */
172 #define MiAddressToPde(Va) \
173  ((PMMPDE)(PDE_BASE + ((MiAddressToPdeOffset(Va)) * sizeof(MMPDE))))
174 
175 /* Takes the PTE index (for one PD page) from the virtual address */
176 #define MiAddressToPteOffset(Va) \
177  ((((ULONG_PTR)(Va)) & (PDE_MAPPED_VA - 1)) / PAGE_SIZE)
178 
179 /* Takes the PDE offset (within all PDs pages) from the virtual address */
180 #define MiAddressToPdeOffset(Va) (((ULONG_PTR)(Va)) / PDE_MAPPED_VA)
181 
182 /* TODO: Free this variable (for offset from the pointer to the PDE) */
183 #define MiGetPdeOffset MiAddressToPdeOffset
184 
185 /* Convert a PTE/PDE into a corresponding address */
186 #define MiPteToAddress(_Pte) ((PVOID)((ULONG)(_Pte) << 10))
187 #define MiPdeToAddress(_Pde) ((PVOID)((ULONG)(_Pde) << 20))
188 
189 /* Translate between P*Es */
190 #define MiPdeToPte(_Pde) ((PMMPTE)MiPteToAddress(_Pde))
191 #define MiPteToPde(_Pte) ((PMMPDE)MiAddressToPte(_Pte))
192 
193 /* Check P*E boundaries */
194 #define MiIsPteOnPdeBoundary(PointerPte) \
195  ((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
196 
197 //
198 // Decodes a Prototype PTE into the underlying PTE
199 //
200 #define MiProtoPteToPte(x) \
201  (PMMPTE)((ULONG_PTR)MmPagedPoolStart + \
202  (((x)->u.Proto.ProtoAddressHigh << 9) | (x)->u.Proto.ProtoAddressLow << 2))
203 
204 //
205 // Decodes a Prototype PTE into the underlying PTE
206 //
207 #define MiSubsectionPteToSubsection(x) \
208  ((x)->u.Subsect.WhichPool == PagedPool) ? \
209  (PMMPTE)((ULONG_PTR)MmSubsectionBase + \
210  (((x)->u.Subsect.SubsectionAddressHigh << 7) | \
211  (x)->u.Subsect.SubsectionAddressLow << 3)) : \
212  (PMMPTE)((ULONG_PTR)MmNonPagedPoolEnd - \
213  (((x)->u.Subsect.SubsectionAddressHigh << 7) | \
214  (x)->u.Subsect.SubsectionAddressLow << 3))
C_ASSERT(PD_COUNT==1)
#define PD_COUNT
Definition: mm.h:129