ReactOS
0.4.17-dev-1190-g4c812f4
mm.h
Go to the documentation of this file.
1
/*
2
* kernel internal memory management definitions for x86
3
*/
4
#pragma once
5
6
#include <
internal/x86x64/mm.h
>
7
8
#ifdef _X86PAE_
9
#define _MI_PAGING_LEVELS 3
10
#define _MI_HAS_NO_EXECUTE 1
11
#else
12
#define _MI_PAGING_LEVELS 2
13
#define _MI_HAS_NO_EXECUTE 0
14
#endif
15
16
/* Memory layout base addresses */
17
#define MI_USER_PROBE_ADDRESS (PVOID)0x7FFF0000
18
#define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0x80000000
19
#ifndef _X86PAE_
20
#define HYPER_SPACE 0xC0400000
21
#define HYPER_SPACE_END 0xC07FFFFF
22
#else
23
#define HYPER_SPACE 0xC0800000
24
#define HYPER_SPACE_END 0xC0BFFFFF
25
#endif
26
#define MI_SYSTEM_CACHE_WS_START (PVOID)0xC0C00000
27
#define MI_SYSTEM_CACHE_START (PVOID)0xC1000000
28
#define MI_PAGED_POOL_START (PVOID)0xE1000000
29
#define MI_NONPAGED_POOL_END (PVOID)0xFFBE0000
30
#define MI_DEBUG_MAPPING (PVOID)0xFFBFF000
31
#define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFF
32
33
/* Misc address definitions */
34
#define MM_HIGHEST_VAD_ADDRESS \
35
(PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
36
#define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE
37
#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
38
MI_HYPERSPACE_PTES * PAGE_SIZE)
39
#define MI_DUMMY_PTE (PMMPTE)((ULONG_PTR)MI_MAPPING_RANGE_END + \
40
PAGE_SIZE)
41
#define MI_VAD_BITMAP (PMMPTE)((ULONG_PTR)MI_DUMMY_PTE + \
42
PAGE_SIZE)
43
#define MI_WORKING_SET_LIST (PMMPTE)((ULONG_PTR)MI_VAD_BITMAP + \
44
PAGE_SIZE)
45
46
/* Memory sizes */
47
#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT)
48
#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT)
49
#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT)
50
#define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT)
51
#define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB)
52
#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128 * _1MB)
53
#define MI_MAX_NONPAGED_POOL_SIZE (128 * _1MB)
54
#define MI_SYSTEM_VIEW_SIZE (32 * _1MB)
55
#define MI_SESSION_VIEW_SIZE (48 * _1MB)
56
#define MI_SESSION_POOL_SIZE (16 * _1MB)
57
#define MI_SESSION_IMAGE_SIZE (8 * _1MB)
58
#define MI_SESSION_WORKING_SET_SIZE (4 * _1MB)
59
#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
60
MI_SESSION_POOL_SIZE + \
61
MI_SESSION_IMAGE_SIZE + \
62
MI_SESSION_WORKING_SET_SIZE)
63
#define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
64
#define MI_ALLOCATION_FRAGMENT (64 * _1KB)
65
#define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
66
67
/* Misc constants */
68
#define MM_PTE_SOFTWARE_PROTECTION_BITS 5
69
#define MI_MIN_SECONDARY_COLORS 8
70
#define MI_SECONDARY_COLORS 64
71
#define MI_MAX_SECONDARY_COLORS 1024
72
#define MI_MAX_FREE_PAGE_LISTS 4
73
#define MI_HYPERSPACE_PTES (256 - 1)
74
#define MI_ZERO_PTES (32)
75
#define MI_MAX_ZERO_BITS 21
76
#define SESSION_POOL_LOOKASIDES 26
77
78
/* MMPTE related defines */
79
#define MM_EMPTY_PTE_LIST ((ULONG)0xFFFFF)
80
#define MM_EMPTY_LIST ((ULONG_PTR)-1)
81
82
83
/* Easy accessing PFN in PTE */
84
#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
85
86
/* Macros for portable PTE modification */
87
#define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
88
#define MI_MAKE_CLEAN_PAGE(x) ((x)->u.Hard.Dirty = 0)
89
#define MI_MAKE_ACCESSED_PAGE(x) ((x)->u.Hard.Accessed = 1)
90
#define MI_IS_PAGE_LARGE(x) ((x)->u.Hard.LargePage == 1)
91
#if !defined(CONFIG_SMP)
92
#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
93
#else
94
#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1)
95
#endif
96
#define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
97
#ifdef _X86PAE_
98
#define MI_IS_PAGE_EXECUTABLE(x) ((x)->u.Hard.NoExecute == 0)
99
#else
100
#define MI_IS_PAGE_EXECUTABLE(x) TRUE
101
#endif
102
#define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1)
103
#define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
104
#if !defined(CONFIG_SMP)
105
#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1)
106
#else
107
#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
108
#endif
109
110
111
/* Macros to identify the page fault reason from the error code */
112
#define MI_IS_NOT_PRESENT_FAULT(FaultCode) !BooleanFlagOn(FaultCode, 0x00000001)
113
#define MI_IS_WRITE_ACCESS(FaultCode) BooleanFlagOn(FaultCode, 0x00000002)
114
// 0x00000004: user-mode access.
115
// 0x00000008: reserved bit violation.
116
#define MI_IS_INSTRUCTION_FETCH(FaultCode) BooleanFlagOn(FaultCode, 0x00000010)
117
// 0x00000020: protection-key violation.
118
// 0x00000040: shadow-stack access.
119
// Bits 7-14: reserved.
120
// 0x00008000: violation of SGX-specific access-control requirements.
121
// Bits 16-31: reserved.
122
123
/* On x86, these two are the same */
124
#define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE
125
126
/* Translating virtual addresses to physical addresses
127
(See: "Intel® 64 and IA-32 Architectures Software Developer’s Manual
128
Volume 3A: System Programming Guide, Part 1, CHAPTER 4 PAGING")
129
Page directory (PD) and Page table (PT) definitions
130
Page directory entry (PDE) and Page table entry (PTE) definitions
131
*/
132
133
/* Maximum number of page directories pages */
134
#ifndef _X86PAE_
135
#define PD_COUNT 1
/* Only one page directory page */
136
#else
137
#define PD_COUNT (1 << 2)
/* The two most significant bits in the VA */
138
#endif
139
140
/* PAE not yet implemented. */
141
C_ASSERT
(
PD_COUNT
== 1);
142
143
/* The number of PTEs on one page of the PT */
144
#define PTE_PER_PAGE (PAGE_SIZE / sizeof(MMPTE))
145
146
/* The number of PDEs on one page of the PD */
147
#define PDE_PER_PAGE (PAGE_SIZE / sizeof(MMPDE))
148
149
/* Maximum number of PDEs */
150
#define PDE_PER_SYSTEM (PD_COUNT * PDE_PER_PAGE)
151
152
/* TODO: It seems this constant is not needed for x86 */
153
#define PPE_PER_PAGE 1
154
155
/* Maximum number of pages for 4 GB of virtual space */
156
#define MI_MAX_PAGES ((1ull << 32) / PAGE_SIZE)
157
158
/* Base addresses for page tables */
159
#define PTE_BASE (ULONG_PTR)0xC0000000
160
#define PTE_TOP (ULONG_PTR)(PTE_BASE + (MI_MAX_PAGES * sizeof(MMPTE)) - 1)
161
#define PTE_MASK (PTE_TOP - PTE_BASE)
162
163
#define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(NULL)
164
165
/* Base addreses for page directories */
166
#define PDE_BASE (ULONG_PTR)MiPteToPde(PTE_BASE)
167
#define PDE_TOP (ULONG_PTR)(PDE_BASE + (PDE_PER_SYSTEM * sizeof(MMPDE)) - 1)
168
#define PDE_MASK (PDE_TOP - PDE_BASE)
169
170
/* The size of the virtual memory area that is mapped using a single PDE */
171
#define PDE_MAPPED_VA (PTE_PER_PAGE * PAGE_SIZE)
172
173
/* Maps the virtual address to the corresponding PTE */
174
#define MiAddressToPte(Va) \
175
((PMMPTE)(PTE_BASE + ((((ULONG_PTR)(Va)) / PAGE_SIZE) * sizeof(MMPTE))))
176
177
/* Maps the virtual address to the corresponding PDE */
178
#define MiAddressToPde(Va) \
179
((PMMPDE)(PDE_BASE + ((MiAddressToPdeOffset(Va)) * sizeof(MMPDE))))
180
181
/* Takes the PTE index (for one PD page) from the virtual address */
182
#define MiAddressToPteOffset(Va) \
183
((((ULONG_PTR)(Va)) & (PDE_MAPPED_VA - 1)) / PAGE_SIZE)
184
185
/* Takes the PDE offset (within all PDs pages) from the virtual address */
186
#define MiAddressToPdeOffset(Va) (((ULONG_PTR)(Va)) / PDE_MAPPED_VA)
187
188
/* TODO: Free this variable (for offset from the pointer to the PDE) */
189
#define MiGetPdeOffset MiAddressToPdeOffset
190
191
/* Convert a PTE/PDE into a corresponding address */
192
#define MiPteToAddress(_Pte) ((PVOID)((ULONG)(_Pte) << 10))
193
#define MiPdeToAddress(_Pde) ((PVOID)((ULONG)(_Pde) << 20))
194
195
/* Translate between P*Es */
196
#define MiPdeToPte(_Pde) ((PMMPTE)MiPteToAddress(_Pde))
197
#define MiPteToPde(_Pte) ((PMMPDE)MiAddressToPte(_Pte))
198
199
/* Check P*E boundaries */
200
#define MiIsPteOnPdeBoundary(PointerPte) \
201
((((ULONG_PTR)(PointerPte)) & (PAGE_SIZE - 1)) == 0)
202
203
//
204
// Decodes a Prototype PTE into the underlying PTE
205
//
206
#define MiProtoPteToPte(x) \
207
(PMMPTE)((ULONG_PTR)MmPagedPoolStart + \
208
(((x)->u.Proto.ProtoAddressHigh << 9) | (x)->u.Proto.ProtoAddressLow << 2))
209
210
//
211
// Decodes a Prototype PTE into the underlying PTE
212
//
213
#define MiSubsectionPteToSubsection(x) \
214
((x)->u.Subsect.WhichPool == PagedPool) ? \
215
(PMMPTE)((ULONG_PTR)MmSubsectionBase + \
216
(((x)->u.Subsect.SubsectionAddressHigh << 7) | \
217
(x)->u.Subsect.SubsectionAddressLow << 3)) : \
218
(PMMPTE)((ULONG_PTR)MmNonPagedPoolEnd - \
219
(((x)->u.Subsect.SubsectionAddressHigh << 7) | \
220
(x)->u.Subsect.SubsectionAddressLow << 3))
C_ASSERT
#define C_ASSERT(e)
Definition:
intsafe.h:73
PD_COUNT
#define PD_COUNT
Definition:
mm.h:135
mm.h
ntoskrnl
include
internal
i386
mm.h
Generated on Tue Oct 20 2026 06:20:14 for ReactOS by
1.9.6
1.9.6 1.9.6