xhcihw.h File Reference
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Classes | |
| struct | _XHCI_TRB |
| struct | _XHCI_ERST_ENTRY |
| struct | _XHCI_SLOT_CONTEXT |
| struct | _XHCI_SLOT_CONTEXT64 |
| struct | _XHCI_ENDPOINT_CONTEXT |
| struct | _XHCI_ENDPOINT_CONTEXT64 |
| struct | _XHCI_INPUT_CONTROL_CONTEXT |
| struct | _XHCI_INPUT_CONTROL_CONTEXT64 |
| struct | _XHCI_STREAM_CONTEXT |
Macro Definition Documentation
◆ USB3_URB_RESERVED_RESOURCES
◆ XHCI_CAP_DBOFF
◆ XHCI_CAP_HCCPARAMS1
◆ XHCI_CAP_HCCPARAMS2
◆ XHCI_CAP_HCSPARAMS1
◆ XHCI_CAP_HCSPARAMS2
◆ XHCI_CAP_HCSPARAMS3
◆ XHCI_CAP_LENGTH_VERSION
◆ XHCI_CAP_RTSOFF
◆ XHCI_CAPLENGTH_MASK
◆ XHCI_CMD_BLOCK_SET_ADDRESS
◆ XHCI_CMD_DECONFIGURE
◆ XHCI_CMD_SLOT_TYPE_SHIFT
◆ XHCI_CMD_STREAM_ID_SHIFT
◆ XHCI_CMD_SUSPEND
◆ XHCI_CMD_TRANSFER_STATE_PRESERVE
◆ XHCI_COMPLETION_PARAMETER_MASK
◆ XHCI_CONFIG_MAX_SLOTS_MASK
◆ XHCI_CONTEXT_SIZE_32
◆ XHCI_CONTEXT_SIZE_64
◆ XHCI_CRCR_ABORT
◆ XHCI_CRCR_POINTER_MASK
◆ XHCI_CRCR_RING_CYCLE
◆ XHCI_CRCR_RUNNING
◆ XHCI_CRCR_STOP
◆ XHCI_DBC_DCST
◆ XHCI_DBC_DCST_PORT_SHIFT
◆ XHCI_DCBAA_ENTRIES
◆ XHCI_DEQUEUE_CYCLE
◆ XHCI_DEQUEUE_FLAGS_MASK
◆ XHCI_DEQUEUE_SCT_SHIFT
◆ XHCI_DEVICE_CONTEXT_COUNT
| #define XHCI_DEVICE_CONTEXT_COUNT 32 |
◆ XHCI_DNCTRL_FUNCTION_WAKE
◆ XHCI_DOORBELL_STRIDE
◆ XHCI_ENDPOINT_STATE_DISABLED
◆ XHCI_ENDPOINT_STATE_ERROR
◆ XHCI_ENDPOINT_STATE_HALTED
◆ XHCI_ENDPOINT_STATE_RUNNING
◆ XHCI_ENDPOINT_STATE_STOPPED
◆ XHCI_ENDPOINT_TYPE_BULK_IN
◆ XHCI_ENDPOINT_TYPE_BULK_OUT
◆ XHCI_ENDPOINT_TYPE_CONTROL
◆ XHCI_ENDPOINT_TYPE_INTERRUPT_IN
◆ XHCI_ENDPOINT_TYPE_INTERRUPT_OUT
◆ XHCI_ENDPOINT_TYPE_ISOCH_IN
◆ XHCI_ENDPOINT_TYPE_ISOCH_OUT
◆ XHCI_ERDP
◆ XHCI_ERDP_BUSY
◆ XHCI_ERDP_SEGMENT_MASK
◆ XHCI_ERSTBA
◆ XHCI_ERSTSZ
◆ XHCI_EVENT_DATA_TYPE_MASK
◆ XHCI_EVENT_PORT_ID_SHIFT
◆ XHCI_EXTCAP_DEBUG
◆ XHCI_EXTCAP_ID_MASK
◆ XHCI_EXTCAP_LEGACY
◆ XHCI_EXTCAP_NEXT_MASK
◆ XHCI_EXTCAP_NEXT_SHIFT
◆ XHCI_EXTCAP_SUPPORTED_PROTOCOL
◆ XHCI_EXTCAP_USB4_TUNNELING
◆ XHCI_HCC1_AC64
◆ XHCI_HCC1_CFC
◆ XHCI_HCC1_CSZ
◆ XHCI_HCC1_MAX_PSA_MASK
◆ XHCI_HCC1_MAX_PSA_SHIFT
◆ XHCI_HCC1_XECP_SHIFT
◆ XHCI_HCC2_CMC
◆ XHCI_HCC2_ETC
◆ XHCI_HCC2_LEC
◆ XHCI_HCIVERSION_MAJOR_SHIFT
◆ XHCI_HCIVERSION_MINOR_SHIFT
◆ XHCI_HCS1_MAX_INTRS_MASK
◆ XHCI_HCS1_MAX_INTRS_SHIFT
◆ XHCI_HCS1_MAX_PORTS_SHIFT
◆ XHCI_HCS1_MAX_SLOTS_MASK
◆ XHCI_HCS2_ERST_MAX_MASK
◆ XHCI_HCS2_ERST_MAX_SHIFT
◆ XHCI_HCS2_IST_MASK
◆ XHCI_HCS2_SCRATCH_HI_MASK
◆ XHCI_HCS2_SCRATCH_HI_SHIFT
◆ XHCI_HCS2_SCRATCH_LO_SHIFT
◆ XHCI_HCS2_SPR
◆ XHCI_HCS3_U1_LATENCY_MASK
◆ XHCI_HCS3_U2_LATENCY_SHIFT
◆ XHCI_IMAN
◆ XHCI_IMAN_ENABLE
◆ XHCI_IMAN_PENDING
◆ XHCI_IMOD
◆ XHCI_IMOD_INTERVAL_50US
◆ XHCI_INPUT_CONTEXT_COUNT
◆ XHCI_INTERRUPTER_STRIDE
◆ XHCI_ISOCH_FRAME_ID_MASK
◆ XHCI_ISOCH_FRAME_ID_SHIFT
◆ XHCI_ISOCH_TBC_SHIFT
◆ XHCI_ISOCH_TLBPC_SHIFT
◆ XHCI_LEGCTLSTS_KEEP_MASK
| #define XHCI_LEGCTLSTS_KEEP_MASK 0x1FFFDFFF |
◆ XHCI_LEGSUP_BIOS_OWNED_BYTE
◆ XHCI_LEGSUP_CTLSTS
◆ XHCI_LEGSUP_OS_OWNED_BYTE
◆ XHCI_LEGSUP_OWNED
◆ XHCI_LINK_TOGGLE_CYCLE
◆ XHCI_MFINDEX_MASK
◆ XHCI_NOTIFICATION_DATA_MASK
◆ XHCI_NOTIFICATION_DATA_SHIFT
◆ XHCI_NOTIFICATION_FUNCTION_WAKE
◆ XHCI_NOTIFICATION_TYPE_MASK
◆ XHCI_NOTIFICATION_TYPE_SHIFT
◆ XHCI_OP_CONFIG
◆ XHCI_OP_CRCR
◆ XHCI_OP_DCBAAP
◆ XHCI_OP_DNCTRL
◆ XHCI_OP_PAGESIZE
◆ XHCI_OP_PORT_BASE
◆ XHCI_OP_PORT_STRIDE
◆ XHCI_OP_USBCMD
◆ XHCI_OP_USBSTS
◆ XHCI_PAGESIZE_4K
◆ XHCI_PLS_RESUME
◆ XHCI_PORT_HLPMC
◆ XHCI_PORT_LI
◆ XHCI_PORT_PMSC
◆ XHCI_PORT_SC
◆ XHCI_PORTHLPMC_BESLD_MASK
◆ XHCI_PORTHLPMC_BESLD_SHIFT
◆ XHCI_PORTHLPMC_HIRDM_MASK
◆ XHCI_PORTHLPMC_L1_TIMEOUT_MASK
◆ XHCI_PORTHLPMC_L1_TIMEOUT_SHIFT
◆ XHCI_PORTLI_ERROR_COUNT_MASK
◆ XHCI_PORTLI_RX_LANES_MASK
◆ XHCI_PORTLI_RX_LANES_SHIFT
◆ XHCI_PORTLI_TX_LANES_MASK
◆ XHCI_PORTLI_TX_LANES_SHIFT
◆ XHCI_PORTPMSC_BESL_MASK
◆ XHCI_PORTPMSC_BESL_SHIFT
◆ XHCI_PORTPMSC_FLA
◆ XHCI_PORTPMSC_HLE
◆ XHCI_PORTPMSC_L1_SLOT_MASK
◆ XHCI_PORTPMSC_L1_SLOT_SHIFT
◆ XHCI_PORTPMSC_RWE
◆ XHCI_PORTPMSC_TEST_MASK
◆ XHCI_PORTPMSC_TEST_SHIFT
◆ XHCI_PORTPMSC_U1_TIMEOUT_MASK
◆ XHCI_PORTPMSC_U2_TIMEOUT_MASK
◆ XHCI_PORTPMSC_U2_TIMEOUT_SHIFT
◆ XHCI_PORTSC_CAS
◆ XHCI_PORTSC_CCS
◆ XHCI_PORTSC_CEC
◆ XHCI_PORTSC_CSC
◆ XHCI_PORTSC_DR
◆ XHCI_PORTSC_LWS
◆ XHCI_PORTSC_OCA
◆ XHCI_PORTSC_OCC
◆ XHCI_PORTSC_PEC
◆ XHCI_PORTSC_PED
◆ XHCI_PORTSC_PIC_MASK
◆ XHCI_PORTSC_PIC_SHIFT
◆ XHCI_PORTSC_PLC
◆ XHCI_PORTSC_PLS_MASK
◆ XHCI_PORTSC_PLS_SHIFT
◆ XHCI_PORTSC_PP
◆ XHCI_PORTSC_PR
◆ XHCI_PORTSC_PRC
◆ XHCI_PORTSC_PRESERVE
| #define XHCI_PORTSC_PRESERVE (XHCI_PORTSC_PP | XHCI_PORTSC_PIC_MASK | XHCI_PORTSC_WAKE_MASK) |
◆ XHCI_PORTSC_SPEED_MASK
◆ XHCI_PORTSC_SPEED_SHIFT
◆ XHCI_PORTSC_TUNNELED
◆ XHCI_PORTSC_WAKE_MASK
◆ XHCI_PORTSC_WAKE_SHIFT
◆ XHCI_PORTSC_WPR
◆ XHCI_PORTSC_WRC
◆ XHCI_PROTOCOL_BLC
◆ XHCI_PROTOCOL_COUNT_MASK
◆ XHCI_PROTOCOL_COUNT_SHIFT
◆ XHCI_PROTOCOL_HLC
◆ XHCI_PROTOCOL_HSO
◆ XHCI_PROTOCOL_IHI
◆ XHCI_PROTOCOL_MAJOR_SHIFT
◆ XHCI_PROTOCOL_MHD_MASK
◆ XHCI_PROTOCOL_MHD_SHIFT
◆ XHCI_PROTOCOL_MINOR_SHIFT
◆ XHCI_PROTOCOL_NAME
◆ XHCI_PROTOCOL_NAME_USB
◆ XHCI_PROTOCOL_OFFSET_MASK
◆ XHCI_PROTOCOL_PORTS
◆ XHCI_PROTOCOL_PSI
◆ XHCI_PROTOCOL_PSIC_SHIFT
◆ XHCI_PROTOCOL_REVISION
◆ XHCI_PSI_EXPONENT_MASK
◆ XHCI_PSI_EXPONENT_SHIFT
◆ XHCI_PSI_ID_MASK
◆ XHCI_PSI_MANTISSA_SHIFT
◆ XHCI_PSI_TYPE_ASYMMETRIC_RX
◆ XHCI_PSI_TYPE_ASYMMETRIC_TX
◆ XHCI_PSI_TYPE_MASK
◆ XHCI_PSI_TYPE_SHIFT
◆ XHCI_PSI_TYPE_SYMMETRIC
◆ XHCI_RT_MFINDEX
◆ XHCI_RUNTIME_INTERRUPTER_BASE
◆ XHCI_SCT_PRIMARY_RING
◆ XHCI_SLOT_STATE_ADDRESSED
◆ XHCI_SLOT_STATE_CONFIGURED
◆ XHCI_SLOT_STATE_DEFAULT
◆ XHCI_SLOT_STATE_DISABLED
◆ XHCI_SPEED_FULL
◆ XHCI_SPEED_HIGH
◆ XHCI_SPEED_LOW
◆ XHCI_SPEED_SUPER
◆ XHCI_STREAM_EDTLA_MASK
◆ XHCI_TRANSFER_EVENT_ED
◆ XHCI_TRANSFER_EVENT_LENGTH_MASK
◆ XHCI_TRB_BEI
◆ XHCI_TRB_CHAIN
◆ XHCI_TRB_CODE_SHIFT
◆ XHCI_TRB_CYCLE
◆ XHCI_TRB_DIR_IN
◆ XHCI_TRB_ENDPOINT_MASK
◆ XHCI_TRB_ENDPOINT_SHIFT
◆ XHCI_TRB_ENT
◆ XHCI_TRB_IDT
◆ XHCI_TRB_INTERRUPTER_MASK
◆ XHCI_TRB_INTERRUPTER_SHIFT
◆ XHCI_TRB_IOC
◆ XHCI_TRB_LENGTH_MASK
◆ XHCI_TRB_SLOT_SHIFT
◆ XHCI_TRB_TD_SIZE_SHIFT
◆ XHCI_TRB_TRT_IN
◆ XHCI_TRB_TRT_NO_DATA
◆ XHCI_TRB_TRT_OUT
◆ XHCI_TRB_TRT_SHIFT
◆ XHCI_TRB_TYPE_MASK
◆ XHCI_TRB_TYPE_SHIFT
◆ XHCI_USB4_CAP_PORTSC_TUNNEL_VALID
◆ XHCI_USBCMD_CME
◆ XHCI_USBCMD_CRS
◆ XHCI_USBCMD_CSS
◆ XHCI_USBCMD_ETE
◆ XHCI_USBCMD_EWE
◆ XHCI_USBCMD_HCRST
◆ XHCI_USBCMD_HSEE
◆ XHCI_USBCMD_INTE
◆ XHCI_USBCMD_RS
◆ XHCI_USBSTS_CNR
◆ XHCI_USBSTS_EINT
◆ XHCI_USBSTS_HCE
◆ XHCI_USBSTS_HCH
◆ XHCI_USBSTS_HSE
◆ XHCI_USBSTS_PCD
◆ XHCI_USBSTS_RSS
◆ XHCI_USBSTS_SRE
◆ XHCI_USBSTS_SSS
◆ XHCI_VENDOR_PORT_TUNNEL_ACTIVE
◆ XHCI_VENDOR_PORT_TUNNEL_BASE
◆ XHCI_VENDOR_PORT_TUNNEL_STRIDE
◆ XHCI_VENDOR_TUNNEL_STATUS
◆ XHCI_VENDOR_TUNNEL_STATUS_ACTIVE
Typedef Documentation
◆ PXHCI_ENDPOINT_CONTEXT
◆ PXHCI_ENDPOINT_CONTEXT64
◆ PXHCI_ERST_ENTRY
| typedef struct _XHCI_ERST_ENTRY * PXHCI_ERST_ENTRY |
◆ PXHCI_INPUT_CONTROL_CONTEXT
◆ PXHCI_INPUT_CONTROL_CONTEXT64
◆ PXHCI_SLOT_CONTEXT
| typedef struct _XHCI_SLOT_CONTEXT * PXHCI_SLOT_CONTEXT |
◆ PXHCI_SLOT_CONTEXT64
| typedef struct _XHCI_SLOT_CONTEXT64 * PXHCI_SLOT_CONTEXT64 |
◆ PXHCI_STREAM_CONTEXT
| typedef struct _XHCI_STREAM_CONTEXT * PXHCI_STREAM_CONTEXT |
◆ PXHCI_TRB
◆ XHCI_ENDPOINT_CONTEXT
Endpoint Context (xHCI 6.2.3). TRDequeuePointer carries DCS in bit 0.
◆ XHCI_ENDPOINT_CONTEXT64
◆ XHCI_ERST_ENTRY
| typedef struct _XHCI_ERST_ENTRY XHCI_ERST_ENTRY |
Event ring segment table entry (xHCI 6.5)
◆ XHCI_INPUT_CONTROL_CONTEXT
Input Control Context (xHCI 6.2.5.1). Bit n of either mask is DCI n, bit 0 the slot.
◆ XHCI_INPUT_CONTROL_CONTEXT64
◆ XHCI_SLOT_CONTEXT
Slot Context (xHCI 6.2.2)
◆ XHCI_SLOT_CONTEXT64
◆ XHCI_STREAM_CONTEXT
Stream Context (xHCI 6.2.4.1). Dword2 holds the Stopped EDTLA in bits 23:0.
◆ XHCI_TRB
Every TRB is 16 bytes. Dword 3 bit 0 is the cycle bit, bits 15:10 the type.
Enumeration Type Documentation
◆ XhciCompletionCode
|
strong |
Definition at line 109 of file xhcihw.h.
110{
111 Invalid = 0,
112 Success = 1,
113 DataBufferError = 2,
114 BabbleDetected = 3,
115 UsbTransactionError = 4,
116 TrbError = 5,
117 StallError = 6,
118 ResourceError = 7,
119 BandwidthError = 8,
120 NoSlotsAvailable = 9,
121 InvalidStreamType = 10,
122 SlotNotEnabled = 11,
123 EndpointNotEnabled = 12,
124 ShortPacket = 13,
125 RingUnderrun = 14,
126 RingOverrun = 15,
127 VfEventRingFull = 16,
128 ParameterError = 17,
129 BandwidthOverrun = 18,
130 ContextStateError = 19,
131 NoPingResponse = 20,
132 EventRingFull = 21,
133 IncompatibleDevice = 22,
134 MissedService = 23,
135 CommandRingStopped = 24,
136 CommandAborted = 25,
137 Stopped = 26,
138 StoppedLengthInvalid = 27,
139 StoppedShortPacket = 28,
140 MaxExitLatencyTooLarge = 29,
141 IsochBufferOverrun = 31,
142 EventLost = 32,
143 UndefinedError = 33,
144 InvalidStreamId = 34,
145 SecondaryBandwidthError = 35,
146 SplitTransactionError = 36,
147 VendorQuirk199 = 199
148};
@ InvalidStreamType
@ CommandRingStopped
@ DataBufferError
@ ParameterError
@ EndpointNotEnabled
@ ShortPacket
@ SecondaryBandwidthError
@ EventRingFull
@ RingUnderrun
@ Invalid
@ Success
@ StoppedLengthInvalid
@ NoPingResponse
@ IsochBufferOverrun
@ BandwidthError
@ UsbTransactionError
@ VendorQuirk199
@ NoSlotsAvailable
@ MissedService
@ ContextStateError
@ VfEventRingFull
@ SlotNotEnabled
@ BabbleDetected
@ UndefinedError
@ MaxExitLatencyTooLarge
@ RingOverrun
@ BandwidthOverrun
@ TrbError
@ ResourceError
@ StallError
@ InvalidStreamId
@ Stopped
@ EventLost
@ StoppedShortPacket
@ IncompatibleDevice
@ CommandAborted
@ SplitTransactionError
◆ XhciTrbType
|
strong |
Definition at line 67 of file xhcihw.h.
68{
69 Normal = 1,
70 SetupStage = 2,
71 DataStage = 3,
72 StatusStage = 4,
73 Isoch = 5,
74 Link = 6,
75 EventData = 7,
76 NoOp = 8,
77 EnableSlot = 9,
78 DisableSlot = 10,
79 AddressDevice = 11,
80 ConfigureEndpoint = 12,
81 EvaluateContext = 13,
82 ResetEndpoint = 14,
83 StopEndpoint = 15,
84 SetTrDequeuePointer = 16,
85 ResetDevice = 17,
86 ForceEvent = 18,
87 NegotiateBandwidth = 19,
88 SetLatencyToleranceValue = 20,
89 GetPortBandwidth = 21,
90 ForceHeader = 22,
91 NoOpCommand = 23,
92 TransferEvent = 32,
93 CommandCompletionEvent = 33,
94 PortStatusChangeEvent = 34,
95 BandwidthRequestEvent = 35,
96 DoorbellEvent = 36,
97 HostControllerEvent = 37,
98 DeviceNotificationEvent = 38,
99 MfindexWrapEvent = 39,
100
101 /* Vendor defined, used for firmware version queries */
102 VendorCommandCompletionEvent = 48,
103 VendorFirmwareVersion = 49,
104 VendorFirmwareVersionAlt = 51,
105 VendorFirmwareVersionAltSetup = 52
106};
Definition: uiautomation.c:17163
@ EvaluateContext
@ DisableSlot
@ DeviceNotificationEvent
@ SetLatencyToleranceValue
@ DataStage
@ VendorFirmwareVersionAlt
@ ResetDevice
@ ResetEndpoint
@ StopEndpoint
@ ForceHeader
@ SetupStage
@ NoOp
@ MfindexWrapEvent
@ CommandCompletionEvent
@ VendorFirmwareVersionAltSetup
@ Normal
@ Link
@ StatusStage
@ BandwidthRequestEvent
@ VendorFirmwareVersion
@ NegotiateBandwidth
@ ForceEvent
@ EnableSlot
@ PortStatusChangeEvent
@ GetPortBandwidth
@ HostControllerEvent
@ Isoch
@ TransferEvent
@ ConfigureEndpoint
@ SetTrDequeuePointer
@ NoOpCommand
@ VendorCommandCompletionEvent
@ DoorbellEvent
@ AddressDevice
Function Documentation
◆ C_ASSERT() [1/9]
| C_ASSERT | ( | sizeof(XHCI_ENDPOINT_CONTEXT) | = =XHCI_CONTEXT_SIZE_32 | ) |
◆ C_ASSERT() [2/9]
| C_ASSERT | ( | sizeof(XHCI_ENDPOINT_CONTEXT64) | = =XHCI_CONTEXT_SIZE_64 | ) |
◆ C_ASSERT() [3/9]
| C_ASSERT | ( | sizeof(XHCI_ERST_ENTRY) | = =16 | ) |
◆ C_ASSERT() [4/9]
| C_ASSERT | ( | sizeof(XHCI_INPUT_CONTROL_CONTEXT) | = =XHCI_CONTEXT_SIZE_32 | ) |
◆ C_ASSERT() [5/9]
| C_ASSERT | ( | sizeof(XHCI_INPUT_CONTROL_CONTEXT64) | = =XHCI_CONTEXT_SIZE_64 | ) |
◆ C_ASSERT() [6/9]
| C_ASSERT | ( | sizeof(XHCI_SLOT_CONTEXT) | = =XHCI_CONTEXT_SIZE_32 | ) |
◆ C_ASSERT() [7/9]
| C_ASSERT | ( | sizeof(XHCI_SLOT_CONTEXT64) | = =XHCI_CONTEXT_SIZE_64 | ) |
◆ C_ASSERT() [8/9]
| C_ASSERT | ( | sizeof(XHCI_STREAM_CONTEXT) | = =16 | ) |
◆ C_ASSERT() [9/9]
◆ XhciTrbCompletionCode()
Definition at line 42 of file xhcihw.h.
44{
46}
Referenced by XhciBulkRing::Ed0Event(), XhciIsochRing::Ed0Event(), XhciBulkRing::Ed1Event(), XhciIsochRing::Ed1Event(), XhciControlRing::LocateTrb(), XhciCommandRing::OnCompletionEvent(), XhciControlRing::OnEventDataEvent(), XhciEndpoint::OnTransferEvent(), XhciUsbDevice::OnTransferEvent(), XhciControlRing::OnTrbEvent(), XhciBulkScanSegment(), XhciDispatchEvent(), and XhciRouteTransferEvent().
◆ XhciTrbPointer()
Definition at line 60 of file xhcihw.h.
62{
64}
Referenced by XhciBulkRing::Ed0Event(), XhciIsochRing::Ed0Event(), XhciBulkRing::Ed1Event(), XhciIsochRing::Ed1Event(), XhciCommandRing::HandleRingStopped(), XhciBulkRing::IsLikelyDuplicate(), XhciControlRing::LocateTrb(), XhciCommandRing::OnCompletionEvent(), XhciControlRing::OnEventDataEvent(), XhciEndpoint::OnTransferEvent(), XhciBulkRing::OnTransferEvent(), XhciControlRing::OnTransferEvent(), XhciControlRing::OnTrbEvent(), XhciTransferRing::OnUntargetedTransferEvent(), XhciControlRing::TagFromEvent(), XhciBulkScanSegment(), and XhciBulkStageBytes().
◆ XhciTrbSlotId()
Definition at line 51 of file xhcihw.h.
53{
55}
Referenced by XhciBulkRing::Ed1Event(), XhciSlotTable::OnDeviceNotificationEvent(), XhciUsbDevice::OnEnableSlotDone(), XhciControlRing::OnEventDataEvent(), XhciTransferRing::OnUntargetedTransferEvent(), XhciDispatchEvent(), and XhciRouteTransferEvent().
◆ XhciTrbType()
| FORCEINLINE ULONG NTAPI XhciTrbType | ( | _In_ const XHCI_TRB * | Trb | ) |
