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cvconst.h
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00001 /* 00002 * File cvconst.h - MS debug information 00003 * 00004 * Copyright (C) 2004, Eric Pouech 00005 * 00006 * This library is free software; you can redistribute it and/or 00007 * modify it under the terms of the GNU Lesser General Public 00008 * License as published by the Free Software Foundation; either 00009 * version 2.1 of the License, or (at your option) any later version. 00010 * 00011 * This library is distributed in the hope that it will be useful, 00012 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 00014 * Lesser General Public License for more details. 00015 * 00016 * You should have received a copy of the GNU Lesser General Public 00017 * License along with this library; if not, write to the Free Software 00018 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA 00019 */ 00020 00021 /* information in this file is highly derived from MSDN DIA information pages */ 00022 00023 /* symbols & types enumeration */ 00024 enum SymTagEnum 00025 { 00026 SymTagNull, 00027 SymTagExe, 00028 SymTagCompiland, 00029 SymTagCompilandDetails, 00030 SymTagCompilandEnv, 00031 SymTagFunction, 00032 SymTagBlock, 00033 SymTagData, 00034 SymTagAnnotation, 00035 SymTagLabel, 00036 SymTagPublicSymbol, 00037 SymTagUDT, 00038 SymTagEnum, 00039 SymTagFunctionType, 00040 SymTagPointerType, 00041 SymTagArrayType, 00042 SymTagBaseType, 00043 SymTagTypedef, 00044 SymTagBaseClass, 00045 SymTagFriend, 00046 SymTagFunctionArgType, 00047 SymTagFuncDebugStart, 00048 SymTagFuncDebugEnd, 00049 SymTagUsingNamespace, 00050 SymTagVTableShape, 00051 SymTagVTable, 00052 SymTagCustom, 00053 SymTagThunk, 00054 SymTagCustomType, 00055 SymTagManagedType, 00056 SymTagDimension, 00057 SymTagMax 00058 }; 00059 00060 enum BasicType 00061 { 00062 btNoType = 0, 00063 btVoid = 1, 00064 btChar = 2, 00065 btWChar = 3, 00066 btInt = 6, 00067 btUInt = 7, 00068 btFloat = 8, 00069 btBCD = 9, 00070 btBool = 10, 00071 btLong = 13, 00072 btULong = 14, 00073 btCurrency = 25, 00074 btDate = 26, 00075 btVariant = 27, 00076 btComplex = 28, 00077 btBit = 29, 00078 btBSTR = 30, 00079 btHresult = 31, 00080 }; 00081 00082 /* kind of UDT */ 00083 enum UdtKind 00084 { 00085 UdtStruct, 00086 UdtClass, 00087 UdtUnion 00088 }; 00089 00090 /* where a SymTagData is */ 00091 enum LocationType 00092 { 00093 LocIsNull, 00094 LocIsStatic, 00095 LocIsTLS, 00096 LocIsRegRel, 00097 LocIsThisRel, 00098 LocIsEnregistered, 00099 LocIsBitField, 00100 LocIsSlot, 00101 LocIsIlRel, 00102 LocInMetaData, 00103 LocIsConstant 00104 }; 00105 00106 /* kind of SymTagData */ 00107 enum DataKind 00108 { 00109 DataIsUnknown, 00110 DataIsLocal, 00111 DataIsStaticLocal, 00112 DataIsParam, 00113 DataIsObjectPtr, 00114 DataIsFileStatic, 00115 DataIsGlobal, 00116 DataIsMember, 00117 DataIsStaticMember, 00118 DataIsConstant 00119 }; 00120 00121 /* values for registers (on different CPUs) */ 00122 enum CV_HREG_e 00123 { 00124 /* those values are common to all supported CPUs (and CPU independent) */ 00125 CV_ALLREG_ERR = 30000, 00126 CV_ALLREG_TEB = 30001, 00127 CV_ALLREG_TIMER = 30002, 00128 CV_ALLREG_EFAD1 = 30003, 00129 CV_ALLREG_EFAD2 = 30004, 00130 CV_ALLREG_EFAD3 = 30005, 00131 CV_ALLREG_VFRAME = 30006, 00132 CV_ALLREG_HANDLE = 30007, 00133 CV_ALLREG_PARAMS = 30008, 00134 CV_ALLREG_LOCALS = 30009, 00135 00136 /* Intel x86 CPU */ 00137 CV_REG_NONE = 0, 00138 CV_REG_AL = 1, 00139 CV_REG_CL = 2, 00140 CV_REG_DL = 3, 00141 CV_REG_BL = 4, 00142 CV_REG_AH = 5, 00143 CV_REG_CH = 6, 00144 CV_REG_DH = 7, 00145 CV_REG_BH = 8, 00146 CV_REG_AX = 9, 00147 CV_REG_CX = 10, 00148 CV_REG_DX = 11, 00149 CV_REG_BX = 12, 00150 CV_REG_SP = 13, 00151 CV_REG_BP = 14, 00152 CV_REG_SI = 15, 00153 CV_REG_DI = 16, 00154 CV_REG_EAX = 17, 00155 CV_REG_ECX = 18, 00156 CV_REG_EDX = 19, 00157 CV_REG_EBX = 20, 00158 CV_REG_ESP = 21, 00159 CV_REG_EBP = 22, 00160 CV_REG_ESI = 23, 00161 CV_REG_EDI = 24, 00162 CV_REG_ES = 25, 00163 CV_REG_CS = 26, 00164 CV_REG_SS = 27, 00165 CV_REG_DS = 28, 00166 CV_REG_FS = 29, 00167 CV_REG_GS = 30, 00168 CV_REG_IP = 31, 00169 CV_REG_FLAGS = 32, 00170 CV_REG_EIP = 33, 00171 CV_REG_EFLAGS = 34, 00172 00173 /* <pcode> */ 00174 CV_REG_TEMP = 40, 00175 CV_REG_TEMPH = 41, 00176 CV_REG_QUOTE = 42, 00177 CV_REG_PCDR3 = 43, /* this includes PCDR4 to PCDR7 */ 00178 CV_REG_CR0 = 80, /* this includes CR1 to CR4 */ 00179 CV_REG_DR0 = 90, /* this includes DR1 to DR7 */ 00180 /* </pcode> */ 00181 00182 CV_REG_GDTR = 110, 00183 CV_REG_GDTL = 111, 00184 CV_REG_IDTR = 112, 00185 CV_REG_IDTL = 113, 00186 CV_REG_LDTR = 114, 00187 CV_REG_TR = 115, 00188 00189 CV_REG_PSEUDO1 = 116, /* this includes Pseudo02 to Pseudo09 */ 00190 CV_REG_ST0 = 128, /* this includes ST1 to ST7 */ 00191 CV_REG_CTRL = 136, 00192 CV_REG_STAT = 137, 00193 CV_REG_TAG = 138, 00194 CV_REG_FPIP = 139, 00195 CV_REG_FPCS = 140, 00196 CV_REG_FPDO = 141, 00197 CV_REG_FPDS = 142, 00198 CV_REG_ISEM = 143, 00199 CV_REG_FPEIP = 144, 00200 CV_REG_FPEDO = 145, 00201 CV_REG_MM0 = 146, /* this includes MM1 to MM7 */ 00202 CV_REG_XMM0 = 154, /* this includes XMM1 to XMM7 */ 00203 CV_REG_XMM00 = 162, 00204 CV_REG_XMM0L = 194, /* this includes XMM1L to XMM7L */ 00205 CV_REG_XMM0H = 202, /* this includes XMM1H to XMM7H */ 00206 CV_REG_MXCSR = 211, 00207 CV_REG_EDXEAX = 212, 00208 CV_REG_EMM0L = 220, 00209 CV_REG_EMM0H = 228, 00210 CV_REG_MM00 = 236, 00211 CV_REG_MM01 = 237, 00212 CV_REG_MM10 = 238, 00213 CV_REG_MM11 = 239, 00214 CV_REG_MM20 = 240, 00215 CV_REG_MM21 = 241, 00216 CV_REG_MM30 = 242, 00217 CV_REG_MM31 = 243, 00218 CV_REG_MM40 = 244, 00219 CV_REG_MM41 = 245, 00220 CV_REG_MM50 = 246, 00221 CV_REG_MM51 = 247, 00222 CV_REG_MM60 = 248, 00223 CV_REG_MM61 = 249, 00224 CV_REG_MM70 = 250, 00225 CV_REG_MM71 = 251, 00226 00227 /* Motorola 68K CPU */ 00228 CV_R68_D0 = 0, /* this includes D1 to D7 too */ 00229 CV_R68_A0 = 8, /* this includes A1 to A7 too */ 00230 CV_R68_CCR = 16, 00231 CV_R68_SR = 17, 00232 CV_R68_USP = 18, 00233 CV_R68_MSP = 19, 00234 CV_R68_SFC = 20, 00235 CV_R68_DFC = 21, 00236 CV_R68_CACR = 22, 00237 CV_R68_VBR = 23, 00238 CV_R68_CAAR = 24, 00239 CV_R68_ISP = 25, 00240 CV_R68_PC = 26, 00241 CV_R68_FPCR = 28, 00242 CV_R68_FPSR = 29, 00243 CV_R68_FPIAR = 30, 00244 CV_R68_FP0 = 32, /* this includes FP1 to FP7 */ 00245 CV_R68_MMUSR030 = 41, 00246 CV_R68_MMUSR = 42, 00247 CV_R68_URP = 43, 00248 CV_R68_DTT0 = 44, 00249 CV_R68_DTT1 = 45, 00250 CV_R68_ITT0 = 46, 00251 CV_R68_ITT1 = 47, 00252 CV_R68_PSR = 51, 00253 CV_R68_PCSR = 52, 00254 CV_R68_VAL = 53, 00255 CV_R68_CRP = 54, 00256 CV_R68_SRP = 55, 00257 CV_R68_DRP = 56, 00258 CV_R68_TC = 57, 00259 CV_R68_AC = 58, 00260 CV_R68_SCC = 59, 00261 CV_R68_CAL = 60, 00262 CV_R68_TT0 = 61, 00263 CV_R68_TT1 = 62, 00264 CV_R68_BAD0 = 64, /* this includes BAD1 to BAD7 */ 00265 CV_R68_BAC0 = 72, /* this includes BAC1 to BAC7 */ 00266 00267 /* MIPS 4000 CPU */ 00268 CV_M4_NOREG = CV_REG_NONE, 00269 CV_M4_IntZERO = 10, 00270 CV_M4_IntAT = 11, 00271 CV_M4_IntV0 = 12, 00272 CV_M4_IntV1 = 13, 00273 CV_M4_IntA0 = 14, /* this includes IntA1 to IntA3 */ 00274 CV_M4_IntT0 = 18, /* this includes IntT1 to IntT7 */ 00275 CV_M4_IntS0 = 26, /* this includes IntS1 to IntS7 */ 00276 CV_M4_IntT8 = 34, 00277 CV_M4_IntT9 = 35, 00278 CV_M4_IntKT0 = 36, 00279 CV_M4_IntKT1 = 37, 00280 CV_M4_IntGP = 38, 00281 CV_M4_IntSP = 39, 00282 CV_M4_IntS8 = 40, 00283 CV_M4_IntRA = 41, 00284 CV_M4_IntLO = 42, 00285 CV_M4_IntHI = 43, 00286 CV_M4_Fir = 50, 00287 CV_M4_Psr = 51, 00288 CV_M4_FltF0 = 60, /* this includes FltF1 to Flt31 */ 00289 CV_M4_FltFsr = 92, 00290 00291 /* Alpha AXP CPU */ 00292 CV_ALPHA_NOREG = CV_REG_NONE, 00293 CV_ALPHA_FltF0 = 10, /* this includes FltF1 to FltF31 */ 00294 CV_ALPHA_IntV0 = 42, 00295 CV_ALPHA_IntT0 = 43, /* this includes T1 to T7 */ 00296 CV_ALPHA_IntS0 = 51, /* this includes S1 to S5 */ 00297 CV_ALPHA_IntFP = 57, 00298 CV_ALPHA_IntA0 = 58, /* this includes A1 to A5 */ 00299 CV_ALPHA_IntT8 = 64, 00300 CV_ALPHA_IntT9 = 65, 00301 CV_ALPHA_IntT10 = 66, 00302 CV_ALPHA_IntT11 = 67, 00303 CV_ALPHA_IntRA = 68, 00304 CV_ALPHA_IntT12 = 69, 00305 CV_ALPHA_IntAT = 70, 00306 CV_ALPHA_IntGP = 71, 00307 CV_ALPHA_IntSP = 72, 00308 CV_ALPHA_IntZERO = 73, 00309 CV_ALPHA_Fpcr = 74, 00310 CV_ALPHA_Fir = 75, 00311 CV_ALPHA_Psr = 76, 00312 CV_ALPHA_FltFsr = 77, 00313 CV_ALPHA_SoftFpcr = 78, 00314 00315 /* Motorola & IBM PowerPC CPU */ 00316 CV_PPC_GPR0 = 1, /* this includes GPR1 to GPR31 */ 00317 CV_PPC_CR = 33, 00318 CV_PPC_CR0 = 34, /* this includes CR1 to CR7 */ 00319 CV_PPC_FPR0 = 42, /* this includes FPR1 to FPR31 */ 00320 00321 CV_PPC_FPSCR = 74, 00322 CV_PPC_MSR = 75, 00323 CV_PPC_SR0 = 76, /* this includes SR1 to SR15 */ 00324 /* some PPC registers missing */ 00325 00326 /* Hitachi SH3 CPU */ 00327 CV_SH3_NOREG = CV_REG_NONE, 00328 CV_SH3_IntR0 = 10, /* this include R1 to R13 */ 00329 CV_SH3_IntFp = 24, 00330 CV_SH3_IntSp = 25, 00331 CV_SH3_Gbr = 38, 00332 CV_SH3_Pr = 39, 00333 CV_SH3_Mach = 40, 00334 CV_SH3_Macl = 41, 00335 CV_SH3_Pc = 50, 00336 CV_SH3_Sr = 51, 00337 CV_SH3_BarA = 60, 00338 CV_SH3_BasrA = 61, 00339 CV_SH3_BamrA = 62, 00340 CV_SH3_BbrA = 63, 00341 CV_SH3_BarB = 64, 00342 CV_SH3_BasrB = 65, 00343 CV_SH3_BamrB = 66, 00344 CV_SH3_BbrB = 67, 00345 CV_SH3_BdrB = 68, 00346 CV_SH3_BdmrB = 69, 00347 CV_SH3_Brcr = 70, 00348 CV_SH_Fpscr = 75, 00349 CV_SH_Fpul = 76, 00350 CV_SH_FpR0 = 80, /* this includes FpR1 to FpR15 */ 00351 CV_SH_XFpR0 = 96, /* this includes XFpR1 to XXFpR15 */ 00352 00353 /* ARM CPU */ 00354 CV_ARM_NOREG = CV_REG_NONE, 00355 CV_ARM_R0 = 10, /* this includes R1 to R12 */ 00356 CV_ARM_SP = 23, 00357 CV_ARM_LR = 24, 00358 CV_ARM_PC = 25, 00359 CV_ARM_CPSR = 26, 00360 00361 /* Intel IA64 CPU */ 00362 CV_IA64_NOREG = CV_REG_NONE, 00363 CV_IA64_Br0 = 512, /* this includes Br1 to Br7 */ 00364 CV_IA64_P0 = 704, /* this includes P1 to P63 */ 00365 CV_IA64_Preds = 768, 00366 CV_IA64_IntH0 = 832, /* this includes H1 to H15 */ 00367 CV_IA64_Ip = 1016, 00368 CV_IA64_Umask = 1017, 00369 CV_IA64_Cfm = 1018, 00370 CV_IA64_Psr = 1019, 00371 CV_IA64_Nats = 1020, 00372 CV_IA64_Nats2 = 1021, 00373 CV_IA64_Nats3 = 1022, 00374 CV_IA64_IntR0 = 1024, /* this includes R1 to R127 */ 00375 CV_IA64_FltF0 = 2048, /* this includes FltF1 to FltF127 */ 00376 /* some IA64 registers missing */ 00377 00378 /* TriCore CPU */ 00379 CV_TRI_NOREG = CV_REG_NONE, 00380 CV_TRI_D0 = 10, /* includes D1 to D15 */ 00381 CV_TRI_A0 = 26, /* includes A1 to A15 */ 00382 CV_TRI_E0 = 42, 00383 CV_TRI_E2 = 43, 00384 CV_TRI_E4 = 44, 00385 CV_TRI_E6 = 45, 00386 CV_TRI_E8 = 46, 00387 CV_TRI_E10 = 47, 00388 CV_TRI_E12 = 48, 00389 CV_TRI_E14 = 49, 00390 CV_TRI_EA0 = 50, 00391 CV_TRI_EA2 = 51, 00392 CV_TRI_EA4 = 52, 00393 CV_TRI_EA6 = 53, 00394 CV_TRI_EA8 = 54, 00395 CV_TRI_EA10 = 55, 00396 CV_TRI_EA12 = 56, 00397 CV_TRI_EA14 = 57, 00398 /* some TriCode registers missing */ 00399 00400 /* AM33 (and the likes) CPU */ 00401 CV_AM33_NOREG = CV_REG_NONE, 00402 CV_AM33_E0 = 10, /* this includes E1 to E7 */ 00403 CV_AM33_A0 = 20, /* this includes A1 to A3 */ 00404 CV_AM33_D0 = 30, /* this includes D1 to D3 */ 00405 CV_AM33_FS0 = 40, /* this includes FS1 to FS31 */ 00406 00407 /* Mitsubishi M32R CPU */ 00408 CV_M32R_NOREG = CV_REG_NONE, 00409 CV_M32R_R0 = 10, /* this includes R1 to R11 */ 00410 CV_M32R_R12 = 22, 00411 CV_M32R_R13 = 23, 00412 CV_M32R_R14 = 24, 00413 CV_M32R_R15 = 25, 00414 CV_M32R_PSW = 26, 00415 CV_M32R_CBR = 27, 00416 CV_M32R_SPI = 28, 00417 CV_M32R_SPU = 29, 00418 CV_M32R_SPO = 30, 00419 CV_M32R_BPC = 31, 00420 CV_M32R_ACHI = 32, 00421 CV_M32R_ACLO = 33, 00422 CV_M32R_PC = 34, 00423 00424 /* AMD/Intel x86_64 CPU */ 00425 CV_AMD64_NONE = CV_REG_NONE, 00426 CV_AMD64_AL = CV_REG_AL, 00427 CV_AMD64_CL = CV_REG_CL, 00428 CV_AMD64_DL = CV_REG_DL, 00429 CV_AMD64_BL = CV_REG_BL, 00430 CV_AMD64_AH = CV_REG_AH, 00431 CV_AMD64_CH = CV_REG_CH, 00432 CV_AMD64_DH = CV_REG_DH, 00433 CV_AMD64_BH = CV_REG_BH, 00434 CV_AMD64_AX = CV_REG_AX, 00435 CV_AMD64_CX = CV_REG_CX, 00436 CV_AMD64_DX = CV_REG_DX, 00437 CV_AMD64_BX = CV_REG_BX, 00438 CV_AMD64_SP = CV_REG_SP, 00439 CV_AMD64_BP = CV_REG_BP, 00440 CV_AMD64_SI = CV_REG_SI, 00441 CV_AMD64_DI = CV_REG_DI, 00442 CV_AMD64_EAX = CV_REG_EAX, 00443 CV_AMD64_ECX = CV_REG_ECX, 00444 CV_AMD64_EDX = CV_REG_EDX, 00445 CV_AMD64_EBX = CV_REG_EBX, 00446 CV_AMD64_ESP = CV_REG_ESP, 00447 CV_AMD64_EBP = CV_REG_EBP, 00448 CV_AMD64_ESI = CV_REG_ESI, 00449 CV_AMD64_EDI = CV_REG_EDI, 00450 CV_AMD64_ES = CV_REG_ES, 00451 CV_AMD64_CS = CV_REG_CS, 00452 CV_AMD64_SS = CV_REG_SS, 00453 CV_AMD64_DS = CV_REG_DS, 00454 CV_AMD64_FS = CV_REG_FS, 00455 CV_AMD64_GS = CV_REG_GS, 00456 CV_AMD64_FLAGS = CV_REG_FLAGS, 00457 CV_AMD64_RIP = CV_REG_EIP, 00458 CV_AMD64_EFLAGS = CV_REG_EFLAGS, 00459 00460 /* <pcode> */ 00461 CV_AMD64_TEMP = CV_REG_TEMP, 00462 CV_AMD64_TEMPH = CV_REG_TEMPH, 00463 CV_AMD64_QUOTE = CV_REG_QUOTE, 00464 CV_AMD64_PCDR3 = CV_REG_PCDR3, /* this includes PCDR4 to PCDR7 */ 00465 CV_AMD64_CR0 = CV_REG_CR0, /* this includes CR1 to CR4 */ 00466 CV_AMD64_DR0 = CV_REG_DR0, /* this includes DR1 to DR7 */ 00467 /* </pcode> */ 00468 00469 CV_AMD64_GDTR = CV_REG_GDTR, 00470 CV_AMD64_GDTL = CV_REG_GDTL, 00471 CV_AMD64_IDTR = CV_REG_IDTR, 00472 CV_AMD64_IDTL = CV_REG_IDTL, 00473 CV_AMD64_LDTR = CV_REG_LDTR, 00474 CV_AMD64_TR = CV_REG_TR, 00475 00476 CV_AMD64_PSEUDO1 = CV_REG_PSEUDO1, /* this includes Pseudo02 to Pseudo09 */ 00477 CV_AMD64_ST0 = CV_REG_ST0, /* this includes ST1 to ST7 */ 00478 CV_AMD64_CTRL = CV_REG_CTRL, 00479 CV_AMD64_STAT = CV_REG_STAT, 00480 CV_AMD64_TAG = CV_REG_TAG, 00481 CV_AMD64_FPIP = CV_REG_FPIP, 00482 CV_AMD64_FPCS = CV_REG_FPCS, 00483 CV_AMD64_FPDO = CV_REG_FPDO, 00484 CV_AMD64_FPDS = CV_REG_FPDS, 00485 CV_AMD64_ISEM = CV_REG_ISEM, 00486 CV_AMD64_FPEIP = CV_REG_FPEIP, 00487 CV_AMD64_FPEDO = CV_REG_FPEDO, 00488 CV_AMD64_MM0 = CV_REG_MM0, /* this includes MM1 to MM7 */ 00489 CV_AMD64_XMM0 = CV_REG_XMM0, /* this includes XMM1 to XMM7 */ 00490 CV_AMD64_XMM00 = CV_REG_XMM00, 00491 CV_AMD64_XMM0L = CV_REG_XMM0L, /* this includes XMM1L to XMM7L */ 00492 CV_AMD64_XMM0H = CV_REG_XMM0H, /* this includes XMM1H to XMM7H */ 00493 CV_AMD64_MXCSR = CV_REG_MXCSR, 00494 CV_AMD64_EDXEAX = CV_REG_EDXEAX, 00495 CV_AMD64_EMM0L = CV_REG_EMM0L, 00496 CV_AMD64_EMM0H = CV_REG_EMM0H, 00497 CV_AMD64_MM00 = CV_REG_MM00, 00498 CV_AMD64_MM01 = CV_REG_MM01, 00499 CV_AMD64_MM10 = CV_REG_MM10, 00500 CV_AMD64_MM11 = CV_REG_MM11, 00501 CV_AMD64_MM20 = CV_REG_MM20, 00502 CV_AMD64_MM21 = CV_REG_MM21, 00503 CV_AMD64_MM30 = CV_REG_MM30, 00504 CV_AMD64_MM31 = CV_REG_MM31, 00505 CV_AMD64_MM40 = CV_REG_MM40, 00506 CV_AMD64_MM41 = CV_REG_MM41, 00507 CV_AMD64_MM50 = CV_REG_MM50, 00508 CV_AMD64_MM51 = CV_REG_MM51, 00509 CV_AMD64_MM60 = CV_REG_MM60, 00510 CV_AMD64_MM61 = CV_REG_MM61, 00511 CV_AMD64_MM70 = CV_REG_MM70, 00512 CV_AMD64_MM71 = CV_REG_MM71, 00513 00514 CV_AMD64_XMM8 = 252, /* this includes XMM9 to XMM15 */ 00515 00516 CV_AMD64_RAX = 328, 00517 CV_AMD64_RBX = 329, 00518 CV_AMD64_RCX = 330, 00519 CV_AMD64_RDX = 331, 00520 CV_AMD64_RSI = 332, 00521 CV_AMD64_RDI = 333, 00522 CV_AMD64_RBP = 334, 00523 CV_AMD64_RSP = 335, 00524 00525 CV_AMD64_R8 = 336, 00526 CV_AMD64_R9 = 337, 00527 CV_AMD64_R10 = 338, 00528 CV_AMD64_R11 = 339, 00529 CV_AMD64_R12 = 340, 00530 CV_AMD64_R13 = 341, 00531 CV_AMD64_R14 = 342, 00532 CV_AMD64_R15 = 343, 00533 00534 /* Wine extension */ 00535 CV_SPARC_NOREG = CV_REG_NONE, 00536 CV_SPARC_G0 = 10, /* includes g0 to g7 */ 00537 CV_SPARC_O0 = 18, /* includes o0 to o7 */ 00538 CV_SPARC_L0 = 26, /* includes l0 to l7 */ 00539 CV_SPARC_I0 = 34, /* includes i0 to i7 */ 00540 CV_SPARC_PSR = 42, 00541 CV_SPARC_PC = 43, 00542 CV_SPARC_NPC = 44, 00543 CV_SPARC_Y = 45, 00544 CV_SPARC_WIM = 46, 00545 CV_SPARC_TBR = 47, 00546 }; 00547 00548 typedef enum 00549 { 00550 THUNK_ORDINAL_NOTYPE, 00551 THUNK_ORDINAL_ADJUSTOR, 00552 THUNK_ORDINAL_VCALL, 00553 THUNK_ORDINAL_PCODE, 00554 THUNK_ORDINAL_LOAD 00555 } THUNK_ORDINAL; 00556 00557 typedef enum CV_call_e 00558 { 00559 CV_CALL_NEAR_C, 00560 CV_CALL_FAR_C, 00561 CV_CALL_NEAR_PASCAL, 00562 CV_CALL_FAR_PASCAL, 00563 CV_CALL_NEAR_FAST, 00564 CV_CALL_FAR_FAST, 00565 CV_CALL_SKIPPED, 00566 CV_CALL_NEAR_STD, 00567 CV_CALL_FAR_STD, 00568 CV_CALL_NEAR_SYS, 00569 CV_CALL_FAR_SYS, 00570 CV_CALL_THISCALL, 00571 CV_CALL_MIPSCALL, 00572 CV_CALL_GENERIC, 00573 CV_CALL_ALPHACALL, 00574 CV_CALL_PPCCALL, 00575 CV_CALL_SHCALL, 00576 CV_CALL_ARMCALL, 00577 CV_CALL_AM33CALL, 00578 CV_CALL_TRICALL, 00579 CV_CALL_SH5CALL, 00580 CV_CALL_M32RCALL, 00581 CV_CALL_RESERVED, 00582 } CV_call_e;
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