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00001 /*
00002  * COPYRIGHT:       See COPYING in the top level directory
00003  * PROJECT:         Serial port driver
00004  * FILE:            drivers/bus/serial/legacy.c
00005  * PURPOSE:         Legacy serial port enumeration
00006  *
00007  * PROGRAMMERS:     Herv� Poussineau (hpoussin@reactos.org)
00008  *                  Mark Junker (mjscod@gmx.de)
00009  */
00010 
00011 #include "serial.h"
00012 
00013 UART_TYPE
00014 SerialDetectUartType(
00015     IN PUCHAR BaseAddress)
00016 {
00017     UCHAR Lcr, TestLcr;
00018     UCHAR OldScr, Scr5A, ScrA5;
00019     BOOLEAN FifoEnabled;
00020     UCHAR NewFifoStatus;
00021 
00022     Lcr = READ_PORT_UCHAR(SER_LCR(BaseAddress));
00023     WRITE_PORT_UCHAR(SER_LCR(BaseAddress), Lcr ^ 0xFF);
00024     TestLcr = READ_PORT_UCHAR(SER_LCR(BaseAddress)) ^ 0xFF;
00025     WRITE_PORT_UCHAR(SER_LCR(BaseAddress), Lcr);
00026 
00027     /* Accessing the LCR must work for a usable serial port */
00028     if (TestLcr != Lcr)
00029         return UartUnknown;
00030 
00031     /* Ensure that all following accesses are done as required */
00032     READ_PORT_UCHAR(SER_RBR(BaseAddress));
00033     READ_PORT_UCHAR(SER_IER(BaseAddress));
00034     READ_PORT_UCHAR(SER_IIR(BaseAddress));
00035     READ_PORT_UCHAR(SER_LCR(BaseAddress));
00036     READ_PORT_UCHAR(SER_MCR(BaseAddress));
00037     READ_PORT_UCHAR(SER_LSR(BaseAddress));
00038     READ_PORT_UCHAR(SER_MSR(BaseAddress));
00039     READ_PORT_UCHAR(SER_SCR(BaseAddress));
00040 
00041     /* Test scratch pad */
00042     OldScr = READ_PORT_UCHAR(SER_SCR(BaseAddress));
00043     WRITE_PORT_UCHAR(SER_SCR(BaseAddress), 0x5A);
00044     Scr5A = READ_PORT_UCHAR(SER_SCR(BaseAddress));
00045     WRITE_PORT_UCHAR(SER_SCR(BaseAddress), 0xA5);
00046     ScrA5 = READ_PORT_UCHAR(SER_SCR(BaseAddress));
00047     WRITE_PORT_UCHAR(SER_SCR(BaseAddress), OldScr);
00048 
00049     /* When non-functional, we have a 8250 */
00050     if (Scr5A != 0x5A || ScrA5 != 0xA5)
00051         return Uart8250;
00052 
00053     /* Test FIFO type */
00054     FifoEnabled = (READ_PORT_UCHAR(SER_IIR(BaseAddress)) & 0x80) != 0;
00055     WRITE_PORT_UCHAR(SER_FCR(BaseAddress), SR_FCR_ENABLE_FIFO);
00056     NewFifoStatus = READ_PORT_UCHAR(SER_IIR(BaseAddress)) & 0xC0;
00057     if (!FifoEnabled)
00058         WRITE_PORT_UCHAR(SER_FCR(BaseAddress), 0);
00059     switch (NewFifoStatus)
00060     {
00061         case 0x00:
00062             return Uart16450;
00063         case 0x40:
00064         case 0x80:
00065             /* Not sure about this but the documentation says that 0x40
00066              * indicates an unusable FIFO but my tests only worked
00067              * with 0x80 */
00068             return Uart16550;
00069     }
00070 
00071     /* FIFO is only functional for 16550A+ */
00072     return Uart16550A;
00073 }
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