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ReactOS Development > Doxygenhwuart.c
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00001 /* 00002 * PROJECT: ReactOS Boot Loader 00003 * LICENSE: BSD - See COPYING.ARM in the top level directory 00004 * FILE: boot/armllb/hw/versatile/hwuart.c 00005 * PURPOSE: LLB UART Initialization Routines for Versatile 00006 * PROGRAMMERS: ReactOS Portable Systems Group 00007 */ 00008 00009 #include "precomp.h" 00010 00011 // 00012 // UART Registers 00013 // 00014 #define UART_PL01x_DR (LlbHwVersaUartBase + 0x00) 00015 #define UART_PL01x_RSR (LlbHwVersaUartBase + 0x04) 00016 #define UART_PL01x_ECR (LlbHwVersaUartBase + 0x04) 00017 #define UART_PL01x_FR (LlbHwVersaUartBase + 0x18) 00018 #define UART_PL011_IBRD (LlbHwVersaUartBase + 0x24) 00019 #define UART_PL011_FBRD (LlbHwVersaUartBase + 0x28) 00020 #define UART_PL011_LCRH (LlbHwVersaUartBase + 0x2C) 00021 #define UART_PL011_CR (LlbHwVersaUartBase + 0x30) 00022 #define UART_PL011_IMSC (LlbHwVersaUartBase + 0x38) 00023 00024 // 00025 // LCR Values 00026 // 00027 #define UART_PL011_LCRH_WLEN_8 0x60 00028 #define UART_PL011_LCRH_FEN 0x10 00029 00030 // 00031 // FCR Values 00032 // 00033 #define UART_PL011_CR_UARTEN 0x01 00034 #define UART_PL011_CR_TXE 0x100 00035 #define UART_PL011_CR_RXE 0x200 00036 00037 // 00038 // LSR Values 00039 // 00040 #define UART_PL01x_FR_RXFE 0x10 00041 #define UART_PL01x_FR_TXFF 0x20 00042 00043 static const ULONG LlbHwVersaUartBase = 0x101F1000; 00044 00045 /* FUNCTIONS ******************************************************************/ 00046 00047 VOID 00048 NTAPI 00049 LlbHwVersaUartInitialize(VOID) 00050 { 00051 ULONG Divider, Remainder, Fraction, ClockRate, Baudrate; 00052 00053 /* Query peripheral rate, hardcore baudrate */ 00054 ClockRate = LlbHwGetPClk(); 00055 Baudrate = 115200; 00056 00057 /* Calculate baudrate clock divider and remainder */ 00058 Divider = ClockRate / (16 * Baudrate); 00059 Remainder = ClockRate % (16 * Baudrate); 00060 00061 /* Calculate the fractional part */ 00062 Fraction = (8 * Remainder / Baudrate) >> 1; 00063 Fraction += (8 * Remainder / Baudrate) & 1; 00064 00065 /* Disable interrupts */ 00066 WRITE_REGISTER_ULONG(UART_PL011_CR, 0); 00067 00068 /* Set the baud rate to 115200 bps */ 00069 WRITE_REGISTER_ULONG(UART_PL011_IBRD, Divider); 00070 WRITE_REGISTER_ULONG(UART_PL011_FBRD, Fraction); 00071 00072 /* Set 8 bits for data, 1 stop bit, no parity, FIFO enabled */ 00073 WRITE_REGISTER_ULONG(UART_PL011_LCRH, 00074 UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN); 00075 00076 /* Clear and enable FIFO */ 00077 WRITE_REGISTER_ULONG(UART_PL011_CR, 00078 UART_PL011_CR_UARTEN | 00079 UART_PL011_CR_TXE | 00080 UART_PL011_CR_RXE); 00081 } 00082 00083 VOID 00084 NTAPI 00085 LlbHwUartSendChar(IN CHAR Char) 00086 { 00087 /* Send the character */ 00088 WRITE_REGISTER_ULONG(UART_PL01x_DR, Char); 00089 } 00090 00091 BOOLEAN 00092 NTAPI 00093 LlbHwUartTxReady(VOID) 00094 { 00095 /* TX output buffer is ready? */ 00096 return ((READ_REGISTER_ULONG(UART_PL01x_FR) & UART_PL01x_FR_TXFF) == 0); 00097 } 00098 00099 ULONG 00100 NTAPI 00101 LlbHwGetUartBase(IN ULONG Port) 00102 { 00103 if (Port == 0) 00104 { 00105 return 0x101F1000; 00106 } 00107 else if (Port == 1) 00108 { 00109 return 0x101F2000; 00110 } 00111 00112 return 0; 00113 } 00114 00115 /* EOF */ Generated on Fri May 25 2012 04:17:06 for ReactOS by
1.7.6.1
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