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ReactOS Development > Doxygen

exintrin.c
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00001 /*
00002  * PROJECT:         ReactOS Kernel
00003  * LICENSE:         BSD - See COPYING.ARM in the top level directory
00004  * FILE:            ntoskrnl/ex/exintrin.c
00005  * PURPOSE:         Exported kernel functions which are now intrinsics
00006  * PROGRAMMERS:     ReactOS Portable Systems Group
00007  */
00008 
00009 /* INCLUDES *******************************************************************/
00010 
00011 #include <ntoskrnl.h>
00012 #define NDEBUG
00013 #include <debug.h>
00014 
00015 #undef InterlockedIncrement
00016 #undef InterlockedDecrement
00017 #undef InterlockedCompareExchange
00018 #undef InterlockedExchangeAdd
00019 #undef InterlockedExchange
00020 
00021 //
00022 // HAL Port to Inlined Port
00023 //
00024 #define H2I(Port) PtrToUshort(Port)
00025 
00026 /* FUNCTIONS ******************************************************************/
00027 
00028 /*
00029  * @implemented
00030  */
00031 LONG
00032 FASTCALL
00033 InterlockedIncrement(IN LONG volatile *Addend)
00034 {
00035     //
00036     // Call the intrinsic
00037     //
00038     return _InterlockedIncrement(Addend);    
00039 }
00040 
00041 /*
00042  * @implemented
00043  */
00044 LONG
00045 FASTCALL
00046 InterlockedDecrement(IN LONG volatile *Addend)
00047 {
00048     //
00049     // Call the intrinsic
00050     //
00051     return _InterlockedDecrement(Addend);
00052 }
00053 
00054 /*
00055  * @implemented
00056  */
00057 LONG
00058 FASTCALL
00059 InterlockedCompareExchange(IN OUT LONG volatile *Destination,
00060                            IN LONG Exchange,
00061                            IN LONG Comperand)
00062 {
00063     //
00064     // Call the intrinsic
00065     //
00066     return _InterlockedCompareExchange(Destination, Exchange, Comperand);
00067 }
00068 
00069 /*
00070  * @implemented
00071  */
00072 LONG
00073 FASTCALL
00074 InterlockedExchange(IN OUT LONG volatile *Destination,
00075                     IN LONG Value)
00076 {
00077     //
00078     // Call the intrinsic
00079     //
00080     return _InterlockedExchange(Destination, Value);
00081 }
00082 
00083 /*
00084  * @implemented
00085  */
00086 LONG
00087 FASTCALL
00088 InterlockedExchangeAdd(IN OUT LONG volatile *Addend,
00089                        IN LONG Increment)
00090 {
00091     //
00092     // Call the intrinsic
00093     //
00094     return _InterlockedExchangeAdd(Addend, Increment);
00095 }
00096 
00097 /*
00098  * @implemented
00099  */
00100 VOID
00101 NTAPI
00102 ProbeForRead(IN CONST VOID *Address,
00103              IN SIZE_T Length,
00104              IN ULONG Alignment)
00105 {
00106     ULONG_PTR Last, Current = (ULONG_PTR)Address;
00107     PAGED_CODE();
00108 
00109     /* Only probe if we have a valid length */
00110     if (Length != 0)
00111     {
00112         /* Sanity check */
00113         ASSERT((Alignment == 1) ||
00114                (Alignment == 2) ||
00115                (Alignment == 4) ||
00116                (Alignment == 8) ||
00117                (Alignment == 16));
00118 
00119         /* Check the alignment */
00120         if ((Current & (Alignment - 1)) != 0)
00121         {
00122             /* Incorrect alignment */
00123             ExRaiseDatatypeMisalignment();
00124         }
00125         
00126         /* Get the end address */
00127         Last = Current + Length - 1;
00128         if ((Last < Current) || (Last >= (ULONG_PTR)MmUserProbeAddress))
00129         {
00130             /* Raise an access violation */
00131             ExRaiseAccessViolation();
00132         }
00133 
00134         /* ProbeForRead doesn't check if memory pages are readable! */
00135     }
00136 }
00137 
00138 /*
00139  * @implemented
00140  */
00141 VOID
00142 NTAPI
00143 ProbeForWrite(IN PVOID Address,
00144               IN SIZE_T Length,
00145               IN ULONG Alignment)
00146 {
00147     ULONG_PTR Last, Current = (ULONG_PTR)Address;
00148     PAGED_CODE();
00149 
00150     /* Only probe if we have a valid length */
00151     if (Length != 0)
00152     {
00153         /* Sanity check */
00154         ASSERT((Alignment == 1) ||
00155                (Alignment == 2) ||
00156                (Alignment == 4) ||
00157                (Alignment == 8) ||
00158                (Alignment == 16));
00159 
00160         /* Check the alignment */
00161         if ((Current & (Alignment - 1)) != 0)
00162         {
00163             /* Incorrect alignment */
00164             ExRaiseDatatypeMisalignment();
00165         }
00166 
00167         /* Get the end address */
00168         Last = Current + Length - 1;
00169         if ((Last < Current) || (Last >= (ULONG_PTR)MmUserProbeAddress))
00170         {
00171             /* Raise an access violation */
00172             ExRaiseAccessViolation();
00173         }
00174 
00175         /* Round down to the last page */
00176         Last = PAGE_ROUND_DOWN(Last) + PAGE_SIZE;
00177         do
00178         {
00179             /* Attempt a write */
00180             *(volatile CHAR*)Current = *(volatile CHAR*)Current;
00181 
00182             /* Go to the next address */
00183             Current = PAGE_ROUND_DOWN(Current) + PAGE_SIZE;
00184         } while (Current != Last);
00185     }
00186 }

Generated on Thu May 24 2012 04:37:29 for ReactOS by doxygen 1.7.6.1

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