ReactOS  0.4.14-dev-98-gb0d4763
hardware.cpp
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1 /*
2  * PROJECT: ReactOS Universal Serial Bus Host Controller Interface
3  * LICENSE: GPL - See COPYING in the top level directory
4  * FILE: drivers/usb/usbuhci/hcd_controller.cpp
5  * PURPOSE: USB UHCI device driver.
6  * PROGRAMMERS:
7  * Michael Martin (michael.martin@reactos.org)
8  * Johannes Anderwald (johannes.anderwald@reactos.org)
9  */
10 
11 #include "usbuhci.h"
12 
13 #define NDEBUG
14 #include <debug.h>
15 
17 
18 BOOLEAN
19 NTAPI
21  IN PKINTERRUPT Interrupt,
23 
24 VOID
25 NTAPI
27  IN PKDPC Dpc,
31 
32 VOID
33 NTAPI
35  IN PKDPC Dpc,
39 
40 
41 VOID
42 NTAPI
44 
45 
46 
47 class CUSBHardwareDevice : public IUHCIHardwareDevice
48 {
49 public:
51 
53  {
55  return m_Ref;
56  }
58  {
60 
61  if (!m_Ref)
62  {
63  delete this;
64  return 0;
65  }
66  return m_Ref;
67  }
68  // com
71 
72  // local
76  VOID GlobalReset();
79 
80  // friend function
88  UCHAR ReadRegister8(ULONG Register);
89  USHORT ReadRegister16(ULONG Register);
90  ULONG ReadRegister32(ULONG Register);
91 
92  // constructor / destructor
93  CUSBHardwareDevice(IUnknown *OuterUnknown){}
94  virtual ~CUSBHardwareDevice(){}
95 
96 protected:
97  LONG m_Ref; // reference count
98  PDRIVER_OBJECT m_DriverObject; // driver object
100  PDEVICE_OBJECT m_FunctionalDeviceObject; // fdo (hcd controller)
101  PDEVICE_OBJECT m_NextDeviceObject; // lower device object
102  KSPIN_LOCK m_Lock; // hardware lock
103  PKINTERRUPT m_Interrupt; // interrupt object
104  KDPC m_IntDpcObject; // dpc object for deferred isr processing
105  PVOID VirtualBase; // virtual base for memory manager
106  PHYSICAL_ADDRESS PhysicalAddress; // physical base for memory manager
107  PULONG m_Base; // UHCI operational port base registers
108  PDMA_ADAPTER m_Adapter; // dma adapter object
109  ULONG m_MapRegisters; // map registers count
110  USHORT m_VendorID; // vendor id
111  USHORT m_DeviceID; // device id
112  PUHCIQUEUE m_UsbQueue; // usb request queue
113  ULONG m_NumberOfPorts; // number of ports
114  PDMAMEMORYMANAGER m_MemoryManager; // memory manager
115  HD_INIT_CALLBACK* m_SCECallBack; // status change callback routine
116  PVOID m_SCEContext; // status change callback routine context
117  //WORK_QUEUE_ITEM m_StatusChangeWorkItem; // work item for status change callback
118  ULONG m_InterruptMask; // interrupt enabled mask
119  ULONG m_PortResetChange; // port reset status
120  PULONG m_FrameList; // frame list
121  PHYSICAL_ADDRESS m_FrameListPhysicalAddress; // frame list physical address
122  PUSHORT m_FrameBandwidth; // frame bandwidth
123  PUHCI_QUEUE_HEAD m_QueueHead[5]; // queue heads
124  PHYSICAL_ADDRESS m_StrayDescriptorPhysicalAddress; // physical address stray descriptor
126  KTIMER m_SCETimer; // SCE timer
127  KDPC m_SCETimerDpc; // timer dpc
128 };
129 
130 //=================================================================================================
131 // COM
132 //
133 NTSTATUS
136  IN REFIID refiid,
137  OUT PVOID* Output)
138 {
139  if (IsEqualGUIDAligned(refiid, IID_IUnknown))
140  {
141  *Output = PVOID(PUNKNOWN(this));
142  PUNKNOWN(*Output)->AddRef();
143  return STATUS_SUCCESS;
144  }
145 
146  return STATUS_UNSUCCESSFUL;
147 }
148 
149 LPCSTR
151 CUSBHardwareDevice::GetUSBType()
152 {
153  return "USBUHCI";
154 }
155 
156 
157 NTSTATUS
163 {
164  BUS_INTERFACE_STANDARD BusInterface;
165  PCI_COMMON_CONFIG PciConfig;
168 
169  DPRINT("CUSBHardwareDevice::Initialize\n");
170 
171  //
172  // Create DMAMemoryManager for use with QueueHeads and Transfer Descriptors.
173  //
175  if (!NT_SUCCESS(Status))
176  {
177  DPRINT1("Failed to create DMAMemoryManager Object\n");
178  return Status;
179  }
180 
181  //
182  // Create the UsbQueue class that will handle the Asynchronous and Periodic Schedules
183  //
185  if (!NT_SUCCESS(Status))
186  {
187  DPRINT1("Failed to create UsbQueue!\n");
188  return Status;
189  }
190 
191  //
192  // store device objects
193  //
198 
199  //
200  // initialize device lock
201  //
203 
204  //
205  // initialize status change work item
206  //
207  //ExInitializeWorkItem(&m_StatusChangeWorkItem, StatusChangeWorkItemRoutine, PVOID(this));
208 
209 
210  // initialize timer
212 
213  // initialize timer dpc
215 
216 
217  m_VendorID = 0;
218  m_DeviceID = 0;
219 
220  Status = GetBusInterface(PhysicalDeviceObject, &BusInterface);
221  if (!NT_SUCCESS(Status))
222  {
223  DPRINT1("Failed to get BusInterface!\n");
224  return Status;
225  }
226 
227  BytesRead = (*BusInterface.GetBusData)(BusInterface.Context,
229  &PciConfig,
230  0,
232 
234  {
235  DPRINT1("Failed to get pci config information!\n");
236  return STATUS_SUCCESS;
237  }
238 
239  m_VendorID = PciConfig.VendorID;
240  m_DeviceID = PciConfig.DeviceID;
241 
242  return STATUS_SUCCESS;
243 }
244 
245 NTSTATUS
246 CUSBHardwareDevice::PnpStart(
247  PCM_RESOURCE_LIST RawResources,
248  PCM_RESOURCE_LIST TranslatedResources)
249 {
250  ULONG Index;
251  PCM_PARTIAL_RESOURCE_DESCRIPTOR ResourceDescriptor;
254 
255  DPRINT("CUSBHardwareDevice::PnpStart\n");
256  for(Index = 0; Index < TranslatedResources->List[0].PartialResourceList.Count; Index++)
257  {
258  //
259  // get resource descriptor
260  //
261  ResourceDescriptor = &TranslatedResources->List[0].PartialResourceList.PartialDescriptors[Index];
262 
263  switch(ResourceDescriptor->Type)
264  {
266  {
269  this);
270 
273  (PVOID)this,
274  NULL,
275  ResourceDescriptor->u.Interrupt.Vector,
276  (KIRQL)ResourceDescriptor->u.Interrupt.Level,
277  (KIRQL)ResourceDescriptor->u.Interrupt.Level,
278  (KINTERRUPT_MODE)(ResourceDescriptor->Flags & CM_RESOURCE_INTERRUPT_LATCHED),
279  (ResourceDescriptor->ShareDisposition != CmResourceShareDeviceExclusive),
280  ResourceDescriptor->u.Interrupt.Affinity,
281  FALSE);
282 
283  if (!NT_SUCCESS(Status))
284  {
285  //
286  // failed to register interrupt
287  //
288  DPRINT1("IoConnect Interrupt failed with %x\n", Status);
289  return Status;
290  }
291  break;
292  }
293  case CmResourceTypePort:
294  {
295  //
296  // Store Resource base
297  //
298  m_Base = (PULONG)(ULONG_PTR)ResourceDescriptor->u.Port.Start.QuadPart; //FIXME
299  DPRINT("UHCI Base %p Length %x\n", m_Base, ResourceDescriptor->u.Port.Length);
300  break;
301  }
302  }
303  }
304 
305  ASSERT(m_Base);
306 
307  //
308  // zero device description
309  //
311 
312  //
313  // initialize device description
314  //
322 
323  //
324  // get dma adapter
325  //
327  if (!m_Adapter)
328  {
329  //
330  // failed to get dma adapter
331  //
332  DPRINT1("Failed to acquire dma adapter\n");
334  }
335 
336  //
337  // Create Common Buffer
338  //
339  VirtualBase = m_Adapter->DmaOperations->AllocateCommonBuffer(m_Adapter,
340  PAGE_SIZE * 4,
342  FALSE);
343  if (!VirtualBase)
344  {
345  DPRINT1("Failed to allocate a common buffer\n");
347  }
348 
349  //
350  // Initialize the DMAMemoryManager
351  //
352  Status = m_MemoryManager->Initialize(this, &m_Lock, PAGE_SIZE * 4, VirtualBase, PhysicalAddress, 32);
353  if (!NT_SUCCESS(Status))
354  {
355  DPRINT1("Failed to initialize the DMAMemoryManager\n");
356  return Status;
357  }
358 
359  //
360  // initializes the controller
361  //
363  if (!NT_SUCCESS(Status))
364  {
365  DPRINT1("Failed to Initialize the controller \n");
366  ASSERT(FALSE);
367  return Status;
368  }
369 
370  //
371  // Initialize the UsbQueue now that we have an AdapterObject.
372  //
374  if (!NT_SUCCESS(Status))
375  {
376  DPRINT1("Failed to Initialize the UsbQueue\n");
377  return Status;
378  }
379 
380  //
381  // Start the controller
382  //
383  DPRINT("Starting Controller\n");
385 
386 
387  //
388  // done
389  //
390  return Status;
391 }
392 
393 NTSTATUS
394 CUSBHardwareDevice::PnpStop(void)
395 {
397  return STATUS_NOT_IMPLEMENTED;
398 }
399 
400 NTSTATUS
401 CUSBHardwareDevice::GetDeviceDetails(
402  OUT OPTIONAL PUSHORT VendorId,
403  OUT OPTIONAL PUSHORT DeviceId,
405  OUT OPTIONAL PULONG Speed)
406 {
407  if (VendorId)
408  {
409  //
410  // get vendor
411  //
412  *VendorId = m_VendorID;
413  }
414 
415  if (DeviceId)
416  {
417  //
418  // get device id
419  //
420  *DeviceId = m_DeviceID;
421  }
422 
423  if (NumberOfPorts)
424  {
425  //
426  // get number of ports
427  //
429  }
430 
431  if (Speed)
432  {
433  //
434  // speed is 0x100
435  //
436  *Speed = 0x100;
437  }
438 
439  return STATUS_SUCCESS;
440 }
441 
442 NTSTATUS CUSBHardwareDevice::GetDMA(
443  OUT struct IDMAMemoryManager **OutDMAMemoryManager)
444 {
445  if (!m_MemoryManager)
446  return STATUS_UNSUCCESSFUL;
447  *OutDMAMemoryManager = m_MemoryManager;
448  return STATUS_SUCCESS;
449 }
450 
451 NTSTATUS
452 CUSBHardwareDevice::GetUSBQueue(
453  OUT struct IUSBQueue **OutUsbQueue)
454 {
455  if (!m_UsbQueue)
456  return STATUS_UNSUCCESSFUL;
457  *OutUsbQueue = m_UsbQueue;
458  return STATUS_SUCCESS;
459 }
460 
461 
462 NTSTATUS
464 {
465  ULONG Index;
466  USHORT Status;
467 
468 
469  //
470  // debug info
471  //
472  DPRINT("[USBUHCI] USBCMD: %x USBSTS %x\n", ReadRegister16(UHCI_USBCMD), ReadRegister16(UHCI_USBSTS));
473 
474  //
475  // Set the run bit in the command register
476  //
478 
479  for(Index = 0; Index < 100; Index++)
480  {
481  //
482  // wait a bit
483  //
485 
486  //
487  // get controller status
488  //
490  DPRINT("[USBUHCI] Status %x\n", Status);
491 
492  if (!(Status & UHCI_USBSTS_HCHALT))
493  {
494  //
495  // controller started
496  //
497  break;
498  }
499  }
500 
501  DPRINT("[USBUHCI] USBCMD: %x USBSTS %x\n", ReadRegister16(UHCI_USBCMD), ReadRegister16(UHCI_USBSTS));
502 
503 
504  if ((Status & UHCI_USBSTS_HCHALT))
505  {
506  //
507  // failed to start controller
508  //
509  DPRINT1("[USBUHCI] Failed to start controller Status %x\n", Status);
510  ASSERT(FALSE);
511  return STATUS_UNSUCCESSFUL;
512  }
513 
514  //
515  // Set the configure bit
516  //
518 
519  for(Index = 0; Index < 2; Index++)
520  {
521  //
522  // get port status
523  //
525 
526  //
527  // clear connection change and port suspend
528  //
530  }
531 
532  DPRINT("[USBUHCI] Controller Started\n");
533  DPRINT("[USBUHCI] Controller Status %x\n", ReadRegister16(UHCI_USBSTS));
534  DPRINT("[USBUHCI] Controller Cmd Status %x\n", ReadRegister16(UHCI_USBCMD));
535  DPRINT("[USBUHCI] Controller Interrupt Status %x\n", ReadRegister16(UHCI_USBINTR));
536  DPRINT("[USBUHCI] Controller Frame %x\n", ReadRegister16(UHCI_FRNUM));
537  DPRINT("[USBUHCI] Controller Port Status 0 %x\n", ReadRegister16(UHCI_PORTSC1));
538  DPRINT("[USBUHCI] Controller Port Status 1 %x\n", ReadRegister16(UHCI_PORTSC1 + 2));
539 
540 
541  // queue timer
542  LARGE_INTEGER Expires;
543  Expires.QuadPart = -10 * 10000;
544 
545  KeSetTimerEx(&m_SCETimer, Expires, 1000, &m_SCETimerDpc);
546 
547  //
548  // done
549  //
550  return STATUS_SUCCESS;
551 }
552 
553 VOID
555 {
557 
558  //
559  // back up start of modify register
560  //
561  ASSERT(m_Base);
563 
564  //
565  // perform global reset
566  //
568 
569  //
570  // delay is 10 ms
571  //
572  Timeout.QuadPart = 10;
573  DPRINT("Waiting %lu milliseconds for global reset\n", Timeout.LowPart);
574 
575  //
576  // convert to 100 ns units (absolute)
577  //
578  Timeout.QuadPart *= -10000;
579 
580  //
581  // perform the wait
582  //
584 
585  //
586  // clear command register
587  //
590 
591 
592  //
593  // restore start of modify register
594  //
596 }
597 
598 NTSTATUS
600 {
602  ULONG Index;
603  BUS_INTERFACE_STANDARD BusInterface;
604  USHORT Value;
606 
607  DPRINT("[USBUHCI] InitializeController\n");
608 
609  //
610  // now disable all interrupts
611  //
613 
614 
615  //
616  // UHCI has two ports
617  //
618  m_NumberOfPorts = 2;
619 
620  //
621  // get bus interface
622  //
624  if (!NT_SUCCESS(Status))
625  {
626  DPRINT1("Failed to get BusInterface!\n");
627  return Status;
628  }
629 
630  //
631  // reclaim ownership from BIOS
632  //
633  Value = 0;
634  BusInterface.GetBusData(BusInterface.Context, PCI_WHICHSPACE_CONFIG, &Value, PCI_LEGSUP, sizeof(USHORT));
635  DPRINT("[USBUHCI] LEGSUP %x\n", Value);
636 
638  BusInterface.SetBusData(BusInterface.Context, PCI_WHICHSPACE_CONFIG, &Value, PCI_LEGSUP, sizeof(USHORT));
639 
640  DPRINT("[USBUHCI] Acquired ownership\n");
641  Value = 0;
642  BusInterface.GetBusData(BusInterface.Context, PCI_WHICHSPACE_CONFIG, &Value, 0x60, sizeof(UCHAR));
643  DPRINT("[USBUHCI] SBRN %x\n", Value);
644 
645  //
646  // perform global reset
647  //
648  GlobalReset();
649 
650  //
651  // reset controller
652  //
654  if (!NT_SUCCESS(Status))
655  {
656  //
657  // failed to reset controller
658  //
659  DPRINT1("[USBUHCI] Failed to reset controller\n");
660  return Status;
661  }
662 
663  //
664  // allocate frame list
665  //
667  if (!NT_SUCCESS(Status))
668  {
669  //
670  // failed to allocate frame list
671  //
672  DPRINT1("[USBUHCI] Failed to allocate frame list with %x\n", Status);
673  return Status;
674  }
675 
676  //
677  // Set base pointer and reset frame number
678  //
681 
682  //
683  // Set the max packet size for bandwidth reclamation to 64 bytes
684  //
686 
687  //
688  // now create queues
689  // 0: interrupt transfers
690  // 1: low speed control transfers
691  // 2: full speed control transfers
692  // 3: bulk transfers
693  // 4: debug queue
694  //
695  for(Index = 0; Index < 5; Index++)
696  {
697  //
698  // create queue head
699  //
701  if (!NT_SUCCESS(Status))
702  {
703  //
704  // failed to allocate queue head
705  //
706  DPRINT1("[USBUHCI] Failed to allocate queue head %x Index %x\n", Status, Index);
707  return Status;
708  }
709 
710  //
711  // store queue head
712  //
716 
717  if (Index > 0)
718  {
719  //
720  // link queue heads
721  //
724  }
725  }
726 
727  DPRINT("Index %d QueueHead %p LinkPhysical %x ElementPhysical %x PhysicalAddress %x Request %p NextElementDescriptor %p\n",
728  0,
729  m_QueueHead[0],
730  m_QueueHead[0]->LinkPhysical,
731  m_QueueHead[0]->ElementPhysical,
733  m_QueueHead[0]->Request,
734  m_QueueHead[0]->NextElementDescriptor);
735  DPRINT("Index %d QueueHead %p LinkPhysical %x ElementPhysical %x PhysicalAddress %x Request %p NextElementDescriptor %p\n",
736  1,
737  m_QueueHead[1],
738  m_QueueHead[1]->LinkPhysical,
739  m_QueueHead[1]->ElementPhysical,
741  m_QueueHead[1]->Request,
742  m_QueueHead[1]->NextElementDescriptor);
743 
744  DPRINT("Index %d QueueHead %p LinkPhysical %x ElementPhysical %x PhysicalAddress %x Request %p NextElementDescriptor %p\n",
745  2,
746  m_QueueHead[2],
747  m_QueueHead[2]->LinkPhysical,
748  m_QueueHead[2]->ElementPhysical,
750  m_QueueHead[2]->Request,
751  m_QueueHead[2]->NextElementDescriptor);
752  DPRINT("Index %d QueueHead %p LinkPhysical %x ElementPhysical %x PhysicalAddress %x Request %p NextElementDescriptor %p\n",
753  3,
754  m_QueueHead[3],
755  m_QueueHead[3]->LinkPhysical,
756  m_QueueHead[3]->ElementPhysical,
758  m_QueueHead[3]->Request,
759  m_QueueHead[3]->NextElementDescriptor);
760  DPRINT("Index %d QueueHead %p LinkPhysical %x ElementPhysical %x PhysicalAddress %x Request %p NextElementDescriptor %p\n",
761  4,
762  m_QueueHead[4],
763  m_QueueHead[4]->LinkPhysical,
764  m_QueueHead[4]->ElementPhysical,
766  m_QueueHead[4]->Request,
767  m_QueueHead[4]->NextElementDescriptor);
768 
769  //
770  // terminate last queue head with stray descriptor
771  //
773  if (!NT_SUCCESS(Status))
774  {
775  //
776  // failed to allocate queue head
777  //
778  DPRINT1("[USBUHCI] Failed to allocate queue head %x Index %x\n", Status, Index);
779  return Status;
780  }
781 #if 0
782  //
783  // init stray descriptor
784  //
788 
789 
790  //
791  // link to last queue head
792  //
795 #endif
796 
797  //
798  // allocate frame bandwidth array
799  //
801  if (!m_FrameBandwidth)
802  {
803  //
804  // no memory
805  //
806  DPRINT1("[USBUHCI] Failed to allocate memory\n");
808  }
809 
810  //
811  // init frame list
812  //
813  for (Index = 0; Index < NUMBER_OF_FRAMES; Index++)
814  {
815  //
816  // store frame list interrupt queue
817  //
820 
821 
822  }
823 
824  //
825  // set enabled interrupt mask
826  //
828 
829  //
830  // now enable interrupts
831  //
833 
834  DPRINT("[USBUHCI] Controller initialized\n");
835  return STATUS_SUCCESS;
836 }
837 
838 NTSTATUS
840 {
841  ASSERT(FALSE);
842  //
843  // failed to reset controller
844  //
845  return STATUS_UNSUCCESSFUL;
846 }
847 
848 NTSTATUS
850 {
851  ULONG Count = 0;
852  USHORT Status;
853 
854  // clear run bit
856 
857  // wait for the controller to stop
859  {
860  DPRINT("[UHCI] Waiting for the controller to halt\n");
862  }
863 
864  // clear configure bit
866 
867  //
868  // reset controller
869  //
871 
872  do
873  {
874  //
875  // wait a bit
876  //
878 
879  //
880  // get status
881  //
883  if (!(Status & UHCI_USBCMD_HCRESET))
884  {
885  //
886  // controller reset completed
887  //
888  return STATUS_SUCCESS;
889  }
890  }while(Count++ < 100);
891 
892  DPRINT1("[USBUHCI] Failed to reset controller Status %x\n", Status);
893  return STATUS_UNSUCCESSFUL;
894 }
895 
896 NTSTATUS
897 CUSBHardwareDevice::ResetPort(
898  IN ULONG PortIndex)
899 {
900  ULONG Port;
901  USHORT Status;
902  ULONG Index;
904 
905  DPRINT("[UHCI] ResetPort Id %lu\n", PortIndex);
906 
907  //
908  // sanity check
909  //
910  ASSERT(PortIndex <= 1);
911 
912  //
913  // get register offset
914  //
915  Port = UHCI_PORTSC1 + PortIndex * 2;
916 
917  //
918  // read port status
919  //
921 
922 
923 
924  //
925  // remove unwanted bits
926  //
928 
929  //
930  // now reset the port
931  //
933 
934  //
935  // delay is 20 ms for port reset
936  //
937  Timeout.QuadPart = 20;
938  DPRINT("Waiting %lu milliseconds for port reset\n", Timeout.LowPart);
939 
940  //
941  // convert to 100 ns units (absolute)
942  //
943  Timeout.QuadPart *= -10000;
944 
945  //
946  // perform the wait
947  //
949 
950  //
951  // re-read status
952  //
954 
955  //
956  // remove unwanted bits
957  //
959 
960  //
961  // clear reset port
962  //
964 
965 
966  //
967  // now wait a bit
968  //
970 
971  for (Index = 0; Index < 100; Index++)
972  {
973  // read port status
975 
976  // remove unwanted bits
978 
979  // enable port
981 
982  //
983  // wait a bit
984  //
986 
987  //
988  // re-read port
989  //
991 
992  if ((Status & UHCI_PORTSC_CURSTAT) == 0)
993  {
994  // no device connected. since we waited long enough we can assume
995  // that the port was reset and no device is connected.
996  break;
997  }
998 
1000  {
1001  // port enabled changed or connection status were set.
1002  // acknowledge either / both and wait again.
1004  continue;
1005  }
1006 
1007  if (Status & UHCI_PORTSC_ENABLED)
1008  {
1009  // the port is enabled
1010  break;
1011  }
1012  }
1013 
1014  m_PortResetChange |= (1 << PortIndex);
1015  DPRINT("[USBUHCI] Port Index %x Status after reset %x\n", PortIndex, ReadRegister16(Port));
1016 
1017  //
1018  // is there a callback
1019  //
1020  if (m_SCECallBack)
1021  {
1022  //
1023  // issue callback
1024  //
1026  }
1027 
1028  return STATUS_SUCCESS;
1029 }
1030 
1031 NTSTATUS
1032 CUSBHardwareDevice::GetPortStatus(
1033  ULONG PortId,
1035  OUT USHORT *PortChange)
1036 {
1037  USHORT Status;
1038 
1039  //
1040  // sanity check
1041  //
1042  if (PortId > 1)
1043  {
1044  //
1045  // invalid index
1046  //
1047  DPRINT1("[UHCI] Invalid PortIndex %lu\n", PortId);
1048  return STATUS_INVALID_PARAMETER;
1049  }
1050 
1051  //
1052  // init status
1053  //
1054  *PortStatus = 0;
1055  *PortChange = 0;
1056 
1057  //
1058  // read port status
1059  //
1060  Status = ReadRegister16(UHCI_PORTSC1 + PortId * 2);
1061  DPRINT("[USBUHCI] PortId %x Status %x\n", PortId, Status);
1062 
1063  // build the status
1065  {
1067  }
1068 
1070  {
1072  }
1073 
1074  if (Status & UHCI_PORTSC_RESET)
1075  {
1077  }
1078 
1080  {
1082  }
1083 
1085  {
1086  *PortChange |= USB_PORT_STATUS_CONNECT;
1087  }
1088 
1090  {
1091  *PortChange |= USB_PORT_STATUS_ENABLE;
1092  }
1093 
1094  if (m_PortResetChange & (1 << PortId))
1095  {
1096  *PortChange |= USB_PORT_STATUS_RESET;
1097  }
1098 
1099  //
1100  // port always has power
1101  //
1103  return STATUS_SUCCESS;
1104 }
1105 
1106 NTSTATUS
1107 CUSBHardwareDevice::ClearPortStatus(
1108  ULONG PortId,
1109  ULONG Feature)
1110 {
1111  ULONG PortRegister;
1113 
1114  DPRINT("CUSBHardwareDevice::ClearPortStatus PortId %x Feature %x\n", PortId, Feature);
1115 
1116  //
1117  // sanity check
1118  //
1119  if (PortId > 1)
1120  {
1121  //
1122  // invalid index
1123  //
1124  DPRINT1("[UHCI] Invalid PortIndex %lu\n", PortId);
1125  return STATUS_INVALID_PARAMETER;
1126  }
1127 
1128  //
1129  // read current status
1130  //
1131  PortRegister = UHCI_PORTSC1 + PortId * 2;
1132  PortStatus = ReadRegister16(PortRegister);
1133  DPRINT("[UHCI] PortStatus %x\n", PortStatus);
1134 
1135  if (Feature == C_PORT_RESET)
1136  {
1137  //
1138  // UHCI is not supporting port reset register bit
1139  //
1140  m_PortResetChange &= ~(1 << PortId);
1141  }
1142  else if (Feature == C_PORT_CONNECTION || Feature == C_PORT_ENABLE)
1143  {
1144  //
1145  // clear port status changes
1146  //
1147  WriteRegister16(PortRegister, PortStatus);
1148  }
1149 
1150  return STATUS_SUCCESS;
1151 }
1152 
1153 
1154 NTSTATUS
1156  ULONG PortId,
1157  ULONG Feature)
1158 {
1159  ULONG PortRegister;
1160 
1161  DPRINT("[UHCI] SetPortFeature PortId %x Feature %x\n", PortId, Feature);
1162 
1163  //
1164  // sanity check
1165  //
1166  if (PortId > 1)
1167  {
1168  //
1169  // invalid index
1170  //
1171  DPRINT1("[UHCI] Invalid PortIndex %lu\n", PortId);
1172  return STATUS_INVALID_PARAMETER;
1173  }
1174 
1175  PortRegister = UHCI_PORTSC1 + PortId * 2;
1176 
1177  if (Feature == PORT_RESET)
1178  {
1179  //
1180  // reset port
1181  //
1182  return ResetPort(PortId);
1183  }
1184  else if (Feature == PORT_ENABLE)
1185  {
1186  //
1187  // reset port
1188  //
1189  WriteRegister16(PortRegister, ReadRegister16(PortRegister) | UHCI_PORTSC_ENABLED);
1190  }
1191  else if (Feature == PORT_POWER)
1192  {
1193  //
1194  // port power is no op, it is always enabled
1195  //
1196  }
1197 
1198  return STATUS_SUCCESS;
1199 }
1200 
1201 
1202 
1203 VOID
1204 CUSBHardwareDevice::SetStatusChangeEndpointCallBack(
1205  PVOID CallBack,
1206  PVOID Context)
1207 {
1208  m_SCECallBack = (HD_INIT_CALLBACK*)CallBack;
1210 }
1211 
1212 BOOLEAN
1213 NTAPI
1215  IN PKINTERRUPT Interrupt,
1217 {
1219  USHORT Status, Acknowledge;
1220 
1221  //
1222  // get context
1223  //
1225 
1226  //
1227  // read register
1228  //
1229  Status = This->ReadRegister16(UHCI_USBSTS);
1230  DPRINT("InterruptServiceRoutine %x\n", Status);
1231 
1232  //
1233  // check if the interrupt signaled are from us
1234  //
1235  if ((Status & This->m_InterruptMask) == 0)
1236  {
1237  if (Status != 0)
1238  {
1239  //
1240  // FIXME: received unexpected interrupt
1241  //
1242  DPRINT1("[USBUHCI] Unexpected interrupt %x\n", Status);
1243  This->WriteRegister16(UHCI_USBSTS, Status);
1244  }
1245 
1246  //
1247  // shared interrupt
1248  //
1249  return FALSE;
1250  }
1251 
1252  //
1253  // check for the interrupt cause
1254  //
1255  Acknowledge = 0;
1256 
1257  if (Status & UHCI_USBSTS_USBINT)
1258  {
1259  //
1260  // transfer finished
1261  //
1262  Acknowledge |= UHCI_USBSTS_USBINT;
1263  }
1264 
1265  if (Status & UHCI_USBSTS_ERRINT)
1266  {
1267  //
1268  // error interrupt
1269  //
1270  Acknowledge |= UHCI_USBSTS_ERRINT;
1271  DPRINT("[UHCI] Error interrupt\n");
1272  }
1273 
1274  if (Status & UHCI_USBSTS_RESDET)
1275  {
1276  //
1277  // resume detected
1278  //
1279  DPRINT("[UHCI] Resume detected\n");
1280  Acknowledge |= UHCI_USBSTS_RESDET;
1281  }
1282 
1283  if (Status & UHCI_USBSTS_HOSTERR)
1284  {
1285  //
1286  // host system error
1287  //
1288  DPRINT("[UHCI] Host System Error\n");
1289  Acknowledge |= UHCI_USBSTS_HOSTERR;
1290  }
1291 
1292  if (Status & UHCI_USBSTS_HCPRERR)
1293  {
1294  //
1295  // processing error
1296  //
1297  DPRINT("[UHCI] Process Error\n");
1298  Acknowledge |= UHCI_USBSTS_HCPRERR;
1299  }
1300 
1301  if (Status & UHCI_USBSTS_HCHALT)
1302  {
1303  //
1304  // controller halted
1305  //
1306  DPRINT("[UHCI] Host controller halted\n");
1307 
1308  //
1309  // disable interrupts
1310  //
1311  This->WriteRegister16(UHCI_USBINTR, 0);
1312  This->m_InterruptMask = 0;
1313  }
1314 
1315  //
1316  // do we have something to acknowledge
1317  //
1318  if (Acknowledge)
1319  {
1320  //
1321  // acknowledge interrupt
1322  //
1323  This->WriteRegister16(UHCI_USBSTS, Acknowledge);
1324 
1325  //
1326  // queue dpc
1327  //
1328  KeInsertQueueDpc(&This->m_IntDpcObject, UlongToPtr(Status), NULL);
1329  }
1330 
1331  //
1332  // interrupt handled
1333  //
1334  return TRUE;
1335 }
1336 
1337 
1338 VOID
1340  IN ULONG Register,
1341  IN UCHAR Value)
1342 {
1343  WRITE_PORT_UCHAR((PUCHAR)((PUCHAR)m_Base + Register), Value);
1344 }
1345 
1346 
1347 VOID
1349  ULONG Register,
1350  USHORT Value)
1351 {
1352  WRITE_PORT_USHORT((PUSHORT)((PUCHAR)m_Base + Register), Value);
1353 }
1354 
1355 
1356 VOID
1358  ULONG Register,
1359  ULONG Value)
1360 {
1361  WRITE_PORT_ULONG((PULONG)((PUCHAR)m_Base + Register), Value);
1362 }
1363 
1364 
1365 UCHAR
1367  ULONG Register)
1368 {
1369  return READ_PORT_UCHAR((PUCHAR)((PUCHAR)m_Base + Register));
1370 }
1371 
1372 
1373 USHORT
1375  ULONG Register)
1376 {
1377  return READ_PORT_USHORT((PUSHORT)((PUCHAR)m_Base + Register));
1378 }
1379 
1380 
1381 ULONG
1383  ULONG Register)
1384 {
1385  return READ_PORT_ULONG((PULONG)((PUCHAR)m_Base + Register));
1386 }
1387 
1388 VOID
1389 CUSBHardwareDevice::GetQueueHead(
1390  IN ULONG QueueHeadIndex,
1391  OUT PUHCI_QUEUE_HEAD *OutQueueHead)
1392 {
1393  //
1394  // sanity check
1395  //
1396  ASSERT(QueueHeadIndex < 5);
1397 
1398  //
1399  // store queue head
1400  //
1401  *OutQueueHead = m_QueueHead[QueueHeadIndex];
1402 }
1403 
1404 VOID
1405 NTAPI
1407  IN PKDPC Dpc,
1411 {
1413  ULONG Status;
1414 
1415  //
1416  // get parameters
1417  //
1419 
1420  DPRINT("UhciDeferredRoutine\n");
1421 
1422  //
1423  // get status
1424  //
1427  {
1428  //
1429  // a transfer finished, inform the queue
1430  //
1431  This->m_UsbQueue->TransferInterrupt(Status & UHCI_USBSTS_USBINT);
1432  return;
1433  }
1434 
1435  //
1436  // other event
1437  //
1438  DPRINT1("[USBUHCI] Status %x not handled\n", Status);
1439 }
1440 
1441 VOID
1442 NTAPI
1444  IN PKDPC Dpc,
1448 {
1450  USHORT PortStatus = 0;
1451  USHORT PortChange = 0;
1452 
1453  // get parameters
1455 
1456  // check port 0
1457  This->GetPortStatus(0, &PortStatus, &PortChange);
1458  if (PortChange)
1459  {
1460  // invoke status change work item routine
1462  return;
1463  }
1464 
1465  // check port 1
1466  This->GetPortStatus(1, &PortStatus, &PortChange);
1467  if (PortChange)
1468  {
1469  // invoke status change work item routine
1471  }
1472 }
1473 
1474 
1475 VOID
1476 NTAPI
1478  PVOID Context)
1479 {
1480  //
1481  // cast to hardware object
1482  //
1484 
1485  //
1486  // is there a callback
1487  //
1488  if (This->m_SCECallBack)
1489  {
1490  //
1491  // issue callback
1492  //
1493  This->m_SCECallBack(This->m_SCEContext);
1494  }
1495 
1496 }
1497 
1498 NTSTATUS
1499 NTAPI
1501  PUSBHARDWAREDEVICE *OutHardware)
1502 {
1504 
1506 
1507  if (!This)
1509 
1510  This->AddRef();
1511 
1512  // return result
1513  *OutHardware = (PUSBHARDWAREDEVICE)This;
1514 
1515  return STATUS_SUCCESS;
1516 }
#define USB_PORT_STATUS_LOW_SPEED
Definition: usb200.h:157
#define UHCI_PORTSC_LOWSPEED
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_In_opt_ ULONG _Out_ PULONG Value
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#define UHCI_USBINTR_SHORT
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CPPORT Port[4]
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#define IN
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#define PORT_RESET
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IN PVOID CallBackContext
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IUSBHardwareDevice * PUSBHARDWAREDEVICE
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_In_ BOOLEAN Release
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#define STATUS_NOT_IMPLEMENTED
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#define PCI_LEGSUP
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#define TD_TERMINATE
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VOID NTAPI StatusChangeWorkItemRoutine(PVOID Context)
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uint32_t ULONG_PTR
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struct _CM_PARTIAL_RESOURCE_DESCRIPTOR::@375::@378 Interrupt
#define NUMBER_OF_FRAMES
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_In_ NDIS_HANDLE _In_ PNDIS_REQUEST Request
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union _CM_PARTIAL_RESOURCE_DESCRIPTOR::@375 u
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#define UHCI_PORTSC_RESET
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#define STDMETHODIMP
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CUSBHardwareDevice(IUnknown *OuterUnknown)
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Status
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unsigned int ULONG
Definition: retypes.h:1
BOOLEAN NTAPI InterruptServiceRoutine(IN PKINTERRUPT Interrupt, IN PVOID ServiceContext)
Definition: hardware.cpp:1242
#define UNIMPLEMENTED
Definition: debug.h:114
void WRITE_PORT_UCHAR(PUCHAR Address, UCHAR Value)
Definition: mach.c:532
#define RtlZeroMemory(Destination, Length)
Definition: typedefs.h:261
PUHCI_TRANSFER_DESCRIPTOR m_StrayDescriptor
Definition: hardware.cpp:125
#define UHCI_USBCMD_GRESET
Definition: hardware.h:39
USHORT ReadRegister16(ULONG Register)
Definition: hardware.cpp:1374
PDRIVER_OBJECT m_DriverObject
Definition: hardware.cpp:78
USHORT NTAPI READ_PORT_USHORT(IN PUSHORT Port)
Definition: portio.c:63
#define UHCI_PORTSC_SUSPEND
Definition: hardware.h:70
VOID NTAPI KeInitializeDpc(IN PKDPC Dpc, IN PKDEFERRED_ROUTINE DeferredRoutine, IN PVOID DeferredContext)
Definition: dpc.c:711
#define UHCI_SOFMOD
Definition: hardware.h:32
return STATUS_SUCCESS
Definition: btrfs.c:2966
#define UHCI_USBCMD
Definition: hardware.h:27
PDEVICE_OBJECT m_PhysicalDeviceObject
Definition: hardware.cpp:79
unsigned short * PUSHORT
Definition: retypes.h:2
VOID NTAPI KeStallExecutionProcessor(IN ULONG MicroSeconds)
Definition: ntoskrnl.c:99
_Must_inspect_result_ _In_ PFILE_OBJECT _In_opt_ PLARGE_INTEGER _In_ ULONG _In_ FLT_IO_OPERATION_FLAGS _Out_opt_ PULONG BytesRead
Definition: fltkernel.h:1255
ULONG LinkPhysical
Definition: hardware.h:170
PUHCI_QUEUE_HEAD m_QueueHead[5]
Definition: hardware.cpp:123
LONGLONG QuadPart
Definition: typedefs.h:112
ULONG ReadRegister32(ULONG Register)
Definition: hardware.cpp:1382
NTSTATUS SetPortFeature(IN PDEVICE_OBJECT RootHubDeviceObject, IN ULONG PortId, IN ULONG Feature)
Definition: fdo.c:93
#define PCI_COMMON_HDR_LENGTH
Definition: iotypes.h:3238
#define IMP_IUHCIHARDWAREDEVICE
Definition: interfaces.h:48
STDMETHODIMP_(ULONG) Release()
Definition: hardware.cpp:57
PULONG MinorVersion OPTIONAL
Definition: CrossNt.h:68
_In_opt_ PVOID DeferredContext
Definition: ketypes.h:675
#define UHCI_USBINTR_IOC
Definition: hardware.h:57