mmu.c File Reference

#include <freeldr.h>
#include "ppcmmu/mmu.h"

Include dependency graph for mmu.c:

Go to the source code of this file.

Functions
int	GetMSR ()
int	GetDEC ()
	__asm__ ("\t.globl GetPhys\n" "GetPhys:\t\n" "mflr 0\n\t" "stwu 0,-16(1)\n\t" "mfmsr 5\n\t" "andi. 6,5,0xffef\n\t" "mtmsr 6\n\t" "isync\n\t" "sync\n\t" "lwz 3,0(3)\n\t" "mtmsr 5\n\t" "isync\n\t" "sync\n\t" "lwz 0,0(1)\n\t" "addi 1,1,16\n\t" "mtlr 0\n\t" "blr")
	__asm__ ("\t.globl GetPhysHalf\n" "GetPhysHalf:\t\n" "mflr 0\n\t" "stwu 0,-16(1)\n\t" "mfmsr 5\n\t" "andi. 6,5,0xffef\n\t" "mtmsr 6\n\t" "isync\n\t" "sync\n\t" "lhz 3,0(3)\n\t" "mtmsr 5\n\t" "isync\n\t" "sync\n\t" "lwz 0,0(1)\n\t" "addi 1,1,16\n\t" "mtlr 0\n\t" "blr")
	__asm__ ("\t.globl GetPhysByte\n" "GetPhysByte:\t\n" "mflr 0\n\t" "stwu 0,-16(1)\n\t" "mfmsr 5\n\t" "andi. 6,5,0xffef\n\t" "mtmsr 6\n\t" "isync\n\t" "sync\n\t" "lbz 3,0(3)\n\t" "mtmsr 5\n\t" "isync\n\t" "sync\n\t" "lwz 0,0(1)\n\t" "addi 1,1,16\n\t" "mtlr 0\n\t" "blr")
	__asm__ ("\t.globl SetPhys\n" "SetPhys:\t\n" "mflr 0\n\t" "stwu 0,-16(1)\n\t" "mfmsr 5\n\t" "andi. 6,5,0xffef\n\t" "mtmsr 6\n\t" "sync\n\t" "eieio\n\t" "stw 4,0(3)\n\t" "dcbst 0,3\n\t" "mtmsr 5\n\t" "sync\n\t" "eieio\n\t" "mr 3,4\n\t" "lwz 0,0(1)\n\t" "addi 1,1,16\n\t" "mtlr 0\n\t" "blr")
	__asm__ ("\t.globl SetPhysHalf\n" "SetPhysHalf:\t\n" "mflr 0\n\t" "stwu 0,-16(1)\n\t" "mfmsr 5\n\t" "andi. 6,5,0xffef\n\t" "mtmsr 6\n\t" "sync\n\t" "eieio\n\t" "sth 4,0(3)\n\t" "dcbst 0,3\n\t" "mtmsr 5\n\t" "sync\n\t" "eieio\n\t" "mr 3,4\n\t" "lwz 0,0(1)\n\t" "addi 1,1,16\n\t" "mtlr 0\n\t" "blr")
	__asm__ ("\t.globl SetPhysByte\n" "SetPhysByte:\t\n" "mflr 0\n\t" "stwu 0,-16(1)\n\t" "mfmsr 5\n\t" "andi. 6,5,0xffef\n\t" "mtmsr 6\n\t" "sync\n\t" "eieio\n\t" "stb 4,0(3)\n\t" "dcbst 0,3\n\t" "mtmsr 5\n\t" "sync\n\t" "eieio\n\t" "mr 3,4\n\t" "lwz 0,0(1)\n\t" "addi 1,1,16\n\t" "mtlr 0\n\t" "blr")
int	GetSR (int n)
void	GetBat (int bat, int inst, int *batHi, int *batLo)
void	SetBat (int bat, int inst, int batHi, int batLo)
int	GetSDR1 ()
void	SetSDR1 (int sdr)
int	BatHit (int bath, int batl, int virt)
int	BatTranslate (int bath, int batl, int virt)
int	PpcVirt2phys (int virt, int inst)
BOOLEAN	InsertPageEntry (int virt, int phys, int slot, int _sdr1)

Function Documentation

__asm__() [1/6]

__asm__	(	"\t.globl GetPhys\n" "GetPhys:\t\n" "mflr 0\n\t" "stwu	0,
		-16(1)\n\t" "mfmsr 5\n\t" "andi.	6,
		5	,
		0xffef\n\t" "mtmsr 6\n\t" "isync\n\t" "sync\n\t" "lwz	3,
		0(3)\n\t" "mtmsr 5\n\t" "isync\n\t" "sync\n\t" "lwz	0,
		0(1)\n\t" "addi	1,
		1	,
		16\n\t" "mtlr 0\n\t" "blr"
	)

Referenced by __addfsbyte(), __addfsdword(), __addfsword(), __break(), __cpuid(), __cpuidex(), __debugbreak(), __declspec(), __DestructExceptionObject(), __emul(), __emulu(), __fp_unordered_compare(), __fpclassify(), __fpclassifyf(), __fpclassifyl(), __halt(), __inbyte(), __inbytestring(), __incfsbyte(), __incfsdword(), __incfsword(), __indword(), __indwordstring(), __int2c(), __invlpg(), __inword(), __inwordstring(), __isnan(), __isnanf(), __isnanl(), __lidt(), __ll_lshift(), __ll_rshift(), __movsb(), __movsd(), __movsw(), __nop(), __outbyte(), __outbytestring(), __outdword(), __outdwordstring(), __outword(), __outwordstring(), __rdtsc(), __readcr0(), __readcr2(), __readcr3(), __readcr4(), __readcr8(), __readdr(), __readeflags(), __readfsbyte(), __readfsdword(), __readfsword(), __readmsr(), __readpmc(), __readsdr1(), __segmentlimit(), __sidt(), __signbit(), __signbitf(), __signbitl(), __stack_chk_fail(), __stosb(), __stosd(), __stosw(), __ud2(), __ull_rshift(), __wbinvd(), __writecr0(), __writecr3(), __writecr4(), __writecr8(), __writedr(), __writeeflags(), __writefsbyte(), __writefsdword(), __writefsword(), __writemsr(), __writesdr1(), __yield(), _BitScanForward(), _BitScanReverse(), _bittest(), _bittestandcomplement(), _bittestandreset(), _bittestandset(), _byteswap_uint64(), _byteswap_ulong(), _byteswap_ushort(), _clearfp(), _control87(), _disable(), _enable(), _fpreset(), _InterlockedAddLargeStatistic(), _interlockedbittestandreset(), _interlockedbittestandset(), _InterlockedCompareExchange(), _InterlockedCompareExchange16(), _InterlockedCompareExchange64(), _InterlockedCompareExchange8(), _InterlockedCompareExchangePointer(), _InterlockedExchange(), _InterlockedExchange16(), _InterlockedExchange8(), _InterlockedExchangeAdd(), _InterlockedExchangeAdd16(), _InterlockedExchangeAdd8(), _InterlockedExchangePointer(), _lrintf(), _lrotl(), _lrotr(), _mm_getcsr(), _mm_lfence(), _mm_mfence(), _mm_pause(), _mm_setcsr(), _mm_sfence(), _mmumain(), _ReadWriteBarrier(), _rotl(), _rotl16(), _rotl8(), _rotr(), _rotr16(), _rotr8(), _SEH2Except(), _SEH2Finally(), _SEH2GlobalUnwind(), _sgdt(), _statusfp(), ArchTrapNoProcess(), atomic_add(), atomic_add_negative(), atomic_dec(), atomic_dec_and_test(), atomic_inc(), atomic_inc_and_test(), atomic_sub(), atomic_sub_and_test(), BlpArchInitialize(), call_test(), callkernel(), COMMAND_PROTOTYPE(), d3d_fpu_setup(), DbgBreakPoint(), DbgBreakPointWithStatus(), DebugService(), DIB_16BPP_ColorFill(), DIB_16BPP_HLine(), DIB_24BPP_ColorFill(), do_x86cpuid(), FrLdrStartup(), GetBat(), GetDEC(), GetGDTPtr(), GetLinearAddress(), GetMSR(), GetSDR1(), GetSR(), HalSweepDcache(), have_x86cpuid(), InitPICE(), InvalidateLB(), KeArmCacheRegisterGet(), KeArmControlRegisterGet(), KeArmControlRegisterSet(), KeArmDomainRegisterSet(), KeArmFaultAddressRegisterGet(), KeArmFaultStatusRegisterGet(), KeArmFlushIcache(), KeArmFlushTlb(), KeArmHaltProcessor(), KeArmIdCodeRegisterGet(), KeArmInstructionFaultStatusRegisterGet(), KeArmInvalidateAllCaches(), KeArmInvalidateTlbEntry(), KeArmLockdownRegisterGet(), KeArmLockdownRegisterSet(), KeArmStatusRegisterGet(), KeArmTranslationTableRegisterGet(), KeArmTranslationTableRegisterSet(), KeArmWaitForInterrupt(), KeFlushProcessTb(), KeGetCurrentProcessorNumber(), KeMemoryBarrier(), KeSweepICache(), KiDecrementerTrap(), KiInitializeContextThread(), KiIret(), KiIsNpxErrataPresent(), KiSetupDecrementerTrap(), KiSwapContext(), KiSwitchToBootStack(), KiSystemStartupReal(), KiThreadStartup(), llrint(), llrintf(), llrintl(), logb(), logbf(), logbl(), lrint(), lrintf(), lrintl(), main(), MiFlushTlb(), MiFlushTlbIpiRoutine(), mmuaddpage(), mmudelpage(), mmunitest(), NmiClearFlag(), NtCurrentTeb(), pice_ioctl(), PiceKbdIsr(), PPCMMU(), PpcPrepGetMemoryMap(), ptegreload(), RestoreIdt(), rint(), rintf(), rintl(), RtlUlongByteSwap(), RtlWalkFrameChain(), set_fpu_control_word(), SetBat(), SetGlobalInt(), SetHardwareBreakPoint(), SetHardwareBreakPoints(), SetSDR1(), setup_fpu(), sync(), TakeIdtSnapshot(), TestSSEExceptions(), trapcallback(), VarCyFromR8(), wined3d_pause(), and ZSTD_cpuid().

__asm__() [2/6]

__asm__	(	"\t.globl GetPhysHalf\n" "GetPhysHalf:\t\n" "mflr 0\n\t" "stwu	0,
		-16(1)\n\t" "mfmsr 5\n\t" "andi.	6,
		5	,
		0xffef\n\t" "mtmsr 6\n\t" "isync\n\t" "sync\n\t" "lhz	3,
		0(3)\n\t" "mtmsr 5\n\t" "isync\n\t" "sync\n\t" "lwz	0,
		0(1)\n\t" "addi	1,
		1	,
		16\n\t" "mtlr 0\n\t" "blr"
	)

__asm__() [3/6]

__asm__	(	"\t.globl GetPhysByte\n" "GetPhysByte:\t\n" "mflr 0\n\t" "stwu	0,
		-16(1)\n\t" "mfmsr 5\n\t" "andi.	6,
		5	,
		0xffef\n\t" "mtmsr 6\n\t" "isync\n\t" "sync\n\t" "lbz	3,
		0(3)\n\t" "mtmsr 5\n\t" "isync\n\t" "sync\n\t" "lwz	0,
		0(1)\n\t" "addi	1,
		1	,
		16\n\t" "mtlr 0\n\t" "blr"
	)

__asm__() [4/6]

__asm__	(	"\t.globl SetPhys\n" "SetPhys:\t\n" "mflr 0\n\t" "stwu	0,
		-16(1)\n\t" "mfmsr 5\n\t" "andi.	6,
		5	,
		0xffef\n\t" "mtmsr 6\n\t" "sync\n\t" "eieio\n\t" "stw	4,
		0(3)\n\t" "dcbst	0,
		3\n\t" "mtmsr 5\n\t" "sync\n\t" "eieio\n\t" "mr	3,
		4\n\t" "lwz	0,
		0(1)\n\t" "addi	1,
		1	,
		16\n\t" "mtlr 0\n\t" "blr"
	)

__asm__() [5/6]

__asm__	(	"\t.globl SetPhysHalf\n" "SetPhysHalf:\t\n" "mflr 0\n\t" "stwu	0,
		-16(1)\n\t" "mfmsr 5\n\t" "andi.	6,
		5	,
		0xffef\n\t" "mtmsr 6\n\t" "sync\n\t" "eieio\n\t" "sth	4,
		0(3)\n\t" "dcbst	0,
		3\n\t" "mtmsr 5\n\t" "sync\n\t" "eieio\n\t" "mr	3,
		4\n\t" "lwz	0,
		0(1)\n\t" "addi	1,
		1	,
		16\n\t" "mtlr 0\n\t" "blr"
	)

__asm__() [6/6]

__asm__	(	"\t.globl SetPhysByte\n" "SetPhysByte:\t\n" "mflr 0\n\t" "stwu	0,
		-16(1)\n\t" "mfmsr 5\n\t" "andi.	6,
		5	,
		0xffef\n\t" "mtmsr 6\n\t" "sync\n\t" "eieio\n\t" "stb	4,
		0(3)\n\t" "dcbst	0,
		3\n\t" "mtmsr 5\n\t" "sync\n\t" "eieio\n\t" "mr	3,
		4\n\t" "lwz	0,
		0(1)\n\t" "addi	1,
		1	,
		16\n\t" "mtlr 0\n\t" "blr"
	)

BatHit()

int BatHit ( int  bath, int  batl, int  virt  )

inline

Definition at line 308 of file mmu.c.

                                                  {
    int mask = 0xfffe0000 & ~((batl & 0x3f) << 17);
    return (batl & 0x40) && ((virt & mask) == (bath & mask));
}

Referenced by PpcVirt2phys().

BatTranslate()

int BatTranslate ( int  bath, int  batl, int  virt  )

inline

Definition at line 313 of file mmu.c.

                                                        {
    return (virt & 0x007fffff) | (batl & 0xfffe0000);
}

Referenced by PpcVirt2phys().

GetBat()

void GetBat ( int  bat, int  inst, int *  batHi, int *  batLo  )

inline

Definition at line 191 of file mmu.c.

                                                                {
    register int bh asm("r3"), bl asm("r4");
    if( inst ) {
    switch( bat ) {
    case 0:
        __asm__("mfibatu 3,0");
        __asm__("mfibatl 4,0");
        break;
    case 1:
        __asm__("mfibatu 3,1");
        __asm__("mfibatl 4,1");
        break;
    case 2:
        __asm__("mfibatu 3,2");
        __asm__("mfibatl 4,2");
        break;
    case 3:
        __asm__("mfibatu 3,3");
        __asm__("mfibatl 4,3");
        break;
    }
    } else {
    switch( bat ) {
    case 0:
        __asm__("mfdbatu 3,0");
        __asm__("mfdbatl 4,0");
        break;
    case 1:
        __asm__("mfdbatu 3,1");
        __asm__("mfdbatl 4,1");
        break;
    case 2:
        __asm__("mfdbatu 3,2");
        __asm__("mfdbatl 4,2");
        break;
    case 3:
        __asm__("mfdbatu 3,3");
        __asm__("mfdbatl 4,3");
        break;
    }
    }
    *batHi = bh;
    *batLo = bl;
}

Referenced by PPCMMU(), and PpcVirt2phys().

GetDEC()

int GetDEC ( void  )

inline

Definition at line 10 of file mmu.c.

                    {
    register int res asm ("r3");
    __asm__("mfdec 3");
    return res;
}

GetMSR()

int GetMSR ( void  )

inline

Definition at line 4 of file mmu.c.

                    {
    register int res asm ("r3");
    __asm__("mfmsr 3");
    return res;
}

Referenced by PpcVirt2phys().

GetSDR1()

int GetSDR1 ( void  )

inline

Definition at line 282 of file mmu.c.

                     {
    register int res asm("r3");
    __asm__("mfsdr1 3");
    return res;
}

Referenced by InsertPageEntry(), and PpcVirt2phys().

GetSR()

int GetSR ( int  n )

inline

Definition at line 136 of file mmu.c.

                        {
    register int res asm ("r3");
    switch( n ) {
    case 0:
    __asm__("mfsr 3,0");
    break;
    case 1:
    __asm__("mfsr 3,1");
    break;
    case 2:
    __asm__("mfsr 3,2");
    break;
    case 3:
    __asm__("mfsr 3,3");
    break;
    case 4:
    __asm__("mfsr 3,4");
    break;
    case 5:
    __asm__("mfsr 3,5");
    break;
    case 6:
    __asm__("mfsr 3,6");
    break;
    case 7:
    __asm__("mfsr 3,7");
    break;
    case 8:
    __asm__("mfsr 3,8");
    break;
    case 9:
    __asm__("mfsr 3,9");
    break;
    case 10:
    __asm__("mfsr 3,10");
    break;
    case 11:
    __asm__("mfsr 3,11");
    break;
    case 12:
    __asm__("mfsr 3,12");
    break;
    case 13:
    __asm__("mfsr 3,13");
    break;
    case 14:
    __asm__("mfsr 3,14");
    break;
    case 15:
    __asm__("mfsr 3,15");
    break;
    }
    return res;
}

Referenced by InsertPageEntry(), mmusetvsid(), and PpcVirt2phys().

InsertPageEntry()

BOOLEAN InsertPageEntry	(	int	virt,
		int	phys,
		int	slot,
		int	_sdr1
	)

Definition at line 373 of file mmu.c.

                                                                   {
    int i, ptehi, ptelo;
    int sdr1 = _sdr1 ? _sdr1 : GetSDR1();
    int sr = GetSR( (virt >> 28) & 0xf );
    int vsid = sr & 0xfffffff;
    int physbase = sdr1 & ~0xffff;
    int hashmask = ((sdr1 & 0x1ff) << 10) | 0x3ff;
    int valo = (vsid << 28) | (virt & 0xfffffff);
    int hash = (vsid & 0x7ffff) ^ ((valo >> 12) & 0xffff);
    int ptegaddr = ((hashmask & hash) * 64) + physbase;

    for( i = 0; i < 8; i++ ) {
    ptehi = GetPhys( ptegaddr + (i * 8) );

    if( (slot != i) && (ptehi & 0x80000000) ) continue;

    ptehi = (1 << 31) | (vsid << 7) | ((virt >> 22) & 0x3f);
    ptelo = phys & ~0xfff;

    SetPhys( ptegaddr + (i * 8), ptehi );
    SetPhys( ptegaddr + (i * 8) + 4, ptelo );

    return TRUE;
    }

    return FALSE;
}

PpcVirt2phys()

int PpcVirt2phys	(	int	virt,
		int	inst
	)

Definition at line 318 of file mmu.c.

                                       {
    int msr = GetMSR();
    int txmask = inst ? 0x20 : 0x10;
    int i, bath, batl, sr, sdr1, physbase, valo;
    int hash, hashmask, ptehi, ptelo, ptegaddr;
    //int vahi, npteg;
    int vsid, pteh, ptevsid, pteapi;

    if( msr & txmask ) {
    sr = GetSR( virt >> 28 );
    vsid = sr & 0xfffffff;
    //vahi = vsid >> 4;
    valo = (vsid << 28) | (virt & 0xfffffff);
    if( sr & 0x80000000 ) {
        return valo;
    }

    for( i = 0; i < 4; i++ ) {
        GetBat( i, inst, &bath, &batl );
        if( BatHit( bath, batl, virt ) ) {
        return BatTranslate( bath, batl, virt );
        }
    }

    sdr1 = GetSDR1();

    physbase = sdr1 & ~0xffff;
    hashmask = ((sdr1 & 0x1ff) << 10) | 0x3ff;
    hash = (vsid & 0x7ffff) ^ ((valo >> 12) & 0xffff);
    //npteg = hashmask + 1;

    for( pteh = 0; pteh < 0x80; pteh += 64, hash ^= 0x7ffff ) {
        ptegaddr = ((hashmask & hash) * 64) + physbase;

        for( i = 0; i < 8; i++ ) {
        ptehi = GetPhys( ptegaddr + (i * 8) );
        ptelo = GetPhys( ptegaddr + (i * 8) + 4 );

        ptevsid = (ptehi >> 7) & 0xffffff;
        pteapi = ptehi & 0x3f;

        if( (ptehi & 64) != pteh ) continue;
        if( ptevsid != (vsid & 0xffffff) ) continue;
        if( pteapi != ((virt >> 22) & 0x3f) ) continue;

        return (ptelo & 0xfffff000) | (virt & 0xfff);
        }
    }
    return -1;
    } else {
    return virt;
    }
}

SetBat()

void SetBat ( int  bat, int  inst, int  batHi, int  batLo  )

inline

Definition at line 236 of file mmu.c.

                                                              {
    register int bh asm("r3"), bl asm("r4");
    bh = batHi;
    bl = batLo;
    if( inst ) {
    switch( bat ) {
    case 0:
        __asm__("mtibatu 0,3");
        __asm__("mtibatl 0,4");
        break;
    case 1:
        __asm__("mtibatu 1,3");
        __asm__("mtibatl 1,4");
        break;
    case 2:
        __asm__("mtibatu 2,3");
        __asm__("mtibatl 2,4");
        break;
    case 3:
        __asm__("mtibatu 3,3");
        __asm__("mtibatl 3,4");
        break;
    }
    } else {
    switch( bat ) {
    case 0:
        __asm__("mtdbatu 0,3");
        __asm__("mtdbatl 0,4");
        break;
    case 1:
        __asm__("mtdbatu 1,3");
        __asm__("mtdbatl 1,4");
        break;
    case 2:
        __asm__("mtdbatu 2,3");
        __asm__("mtdbatl 2,4");
        break;
    case 3:
        __asm__("mtdbatu 3,3");
        __asm__("mtdbatl 3,4");
        break;
    }
    }
    __asm__("isync\n\tsync");
}

Referenced by _mmumain(), and PPCMMU().

SetSDR1()

void SetSDR1 ( int  sdr )

inline

Definition at line 288 of file mmu.c.

                               {
#if 0
    int i,j;
#endif
    __asm__("mtsdr1 3");
#if 0
    __asm__("sync");
    __asm__("isync");
    __asm__("ptesync");

    for( i = 0; i < 256; i++ ) {
    j = i << 12;
    __asm__("tlbie %0,0" : : "r" (j));
    }
    __asm__("eieio");
    __asm__("tlbsync");
    __asm__("ptesync");
#endif
}