ReactOS  0.4.14-dev-49-gfb4591c
apic.h
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1 /*
2  *
3  */
4 
5 #pragma once
6 
7 #define APIC_DEFAULT_BASE 0xFEE00000 /* Default Local APIC Base Register Address */
8 
9 /* APIC Register Address Map */
10 #define APIC_ID 0x0020 /* Local APIC ID Register (R/W) */
11 #define APIC_VER 0x0030 /* Local APIC Version Register (R) */
12 #define APIC_TPR 0x0080 /* Task Priority Register (R/W) */
13 #define APIC_APR 0x0090 /* Arbitration Priority Register (R) */
14 #define APIC_PPR 0x00A0 /* Processor Priority Register (R) */
15 #define APIC_EOI 0x00B0 /* EOI Register (W) */
16 #define APIC_LDR 0x00D0 /* Logical Destination Register (R/W) */
17 #define APIC_DFR 0x00E0 /* Destination Format Register (0-27 R, 28-31 R/W) */
18 #define APIC_SIVR 0x00F0 /* Spurious Interrupt Vector Register (0-3 R, 4-9 R/W) */
19 #define APIC_ISR 0x0100 /* Interrupt Service Register 0-255 (R) */
20 #define APIC_TMR 0x0180 /* Trigger Mode Register 0-255 (R) */
21 #define APIC_IRR 0x0200 /* Interrupt Request Register 0-255 (r) */
22 #define APIC_ESR 0x0280 /* Error Status Register (R) */
23 #define APIC_ICR0 0x0300 /* Interrupt Command Register 0-31 (R/W) */
24 #define APIC_ICR1 0x0310 /* Interrupt Command Register 32-63 (R/W) */
25 #define APIC_LVTT 0x0320 /* Local Vector Table (Timer) (R/W) */
26 #define APIC_LVTTHMR 0x0330
27 #define APIC_LVTPC 0x0340 /* Performance Counter LVT (R/W) */
28 #define APIC_LINT0 0x0350 /* Local Vector Table (LINT0) (R/W) */
29 #define APIC_LINT1 0x0360 /* Local Vector Table (LINT1) (R/W) */
30 #define APIC_LVT3 0x0370 /* Local Vector Table (Error) (R/W) */
31 #define APIC_ICRT 0x0380 /* Initial Count Register for Timer (R/W) */
32 #define APIC_CCRT 0x0390 /* Current Count Register for Timer (R) */
33 #define APIC_TDCR 0x03E0 /* Timer Divide Configuration Register (R/W) */
34 
35 #define APIC_ID_MASK (0xF << 24)
36 #define GET_APIC_ID(x) (((x) & APIC_ID_MASK) >> 24)
37 #define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFF)
38 #define APIC_VER_MASK 0xFF00FF
39 #define GET_APIC_VERSION(x) ((x) & 0xFF)
40 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFF)
41 
42 #define APIC_TPR_PRI 0xFF
43 #define APIC_TPR_INT 0xF0
44 #define APIC_TPR_SUB 0xF
45 #define APIC_TPR_MAX 0xFF /* Maximum priority */
46 #define APIC_TPR_MIN 0x20 /* Minimum priority */
47 
48 #define APIC_LDR_MASK (0xFF << 24)
49 
50 #define APIC_SIVR_ENABLE (0x1 << 8)
51 #define APIC_SIVR_FOCUS (0x1 << 9)
52 
53 #define APIC_ESR_MASK (0xFE << 0) /* Error Mask */
54 
55 #define APIC_ICR0_VECTOR (0xFF << 0) /* Vector */
56 #define APIC_ICR0_DM (0x7 << 8) /* Delivery Mode */
57 #define APIC_ICR0_DESTM (0x1 << 11) /* Destination Mode */
58 #define APIC_ICR0_DS (0x1 << 12) /* Delivery Status */
59 #define APIC_ICR0_LEVEL (0x1 << 14) /* Level */
60 #define APIC_ICR0_TM (0x1 << 15) /* Trigger Mode */
61 #define APIC_ICR0_DESTS (0x3 << 18) /* Destination Shorthand */
62 
63 /* Delivery Modes */
64 #define APIC_DM_FIXED (0x0 << 8)
65 #define APIC_DM_LOWEST (0x1 << 8)
66 #define APIC_DM_SMI (0x2 << 8)
67 #define APIC_DM_REMRD (0x3 << 8)
68 #define APIC_DM_NMI (0x4 << 8)
69 #define APIC_DM_INIT (0x5 << 8)
70 #define APIC_DM_STARTUP (0x6 << 8)
71 #define APIC_DM_EXTINT (0x7 << 8)
72 #define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7)
73 #define SET_APIC_DELIVERY_MODE(x,y) (((x) & ~0x700) | ((y) << 8))
74 
75 /* Destination Shorthand values */
76 #define APIC_ICR0_DESTS_FIELD (0x0 << 0)
77 #define APIC_ICR0_DESTS_SELF (0x1 << 18)
78 #define APIC_ICR0_DESTS_ALL (0x2 << 18)
79 #define APIC_ICR0_DESTS_ALL_BUT_SELF (0x3 << 18)
80 
81 #define APIC_ICR0_LEVEL_DEASSERT (0x0 << 14) /* Deassert level */
82 #define APIC_ICR0_LEVEL_ASSERT (0x1 << 14) /* Assert level */
83 
84 #define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
85 #define SET_APIC_DEST_FIELD(x) (((x) & 0xFF) << 24)
86 
87 #define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3)
88 #define SET_APIC_TIMER_BASE(x) ((x) << 18)
89 #define APIC_TIMER_BASE_CLKIN 0x0
90 #define APIC_TIMER_BASE_TMBASE 0x1
91 #define APIC_TIMER_BASE_DIV 0x2
92 
93 #define APIC_LVT_VECTOR (0xFF << 0) /* Vector */
94 #define APIC_LVT_DS (0x1 << 12) /* Delivery Status */
95 #define APIC_LVT_REMOTE_IRR (0x1 << 14) /* Remote IRR */
96 #define APIC_LVT_LEVEL_TRIGGER (0x1 << 15) /* Lvel Triggered */
97 #define APIC_LVT_MASKED (0x1 << 16) /* Mask */
98 #define APIC_LVT_PERIODIC (0x1 << 17) /* Timer Mode */
99 
100 #define APIC_LVT3_DM (0x7 << 8)
101 #define APIC_LVT3_IIPP (0x1 << 13)
102 #define APIC_LVT3_TM (0x1 << 15)
103 #define APIC_LVT3_MASKED (0x1 << 16)
104 #define APIC_LVT3_OS (0x1 << 17)
105 
106 #define APIC_TDCR_TMBASE (0x1 << 2)
107 #define APIC_TDCR_MASK 0x0F
108 #define APIC_TDCR_2 0x00
109 #define APIC_TDCR_4 0x01
110 #define APIC_TDCR_8 0x02
111 #define APIC_TDCR_16 0x03
112 #define APIC_TDCR_32 0x08
113 #define APIC_TDCR_64 0x09
114 #define APIC_TDCR_128 0x0A
115 #define APIC_TDCR_1 0x0B
116 
117 #define APIC_LVT_VECTOR (0xFF << 0) /* Vector */
118 #define APIC_LVT_DS (0x1 << 12) /* Delivery Status */
119 #define APIC_LVT_REMOTE_IRR (0x1 << 14) /* Remote IRR */
120 #define APIC_LVT_LEVEL_TRIGGER (0x1 << 15) /* Lvel Triggered */
121 #define APIC_LVT_MASKED (0x1 << 16) /* Mask */
122 #define APIC_LVT_PERIODIC (0x1 << 17) /* Timer Mode */
123 
124 #define APIC_LVT3_DM (0x7 << 8)
125 #define APIC_LVT3_IIPP (0x1 << 13)
126 #define APIC_LVT3_TM (0x1 << 15)
127 #define APIC_LVT3_MASKED (0x1 << 16)
128 #define APIC_LVT3_OS (0x1 << 17)
129 
130 #define APIC_TDCR_TMBASE (0x1 << 2)
131 #define APIC_TDCR_MASK 0x0F
132 #define APIC_TDCR_2 0x00
133 #define APIC_TDCR_4 0x01
134 #define APIC_TDCR_8 0x02
135 #define APIC_TDCR_16 0x03
136 #define APIC_TDCR_32 0x08
137 #define APIC_TDCR_64 0x09
138 #define APIC_TDCR_128 0x0A
139 #define APIC_TDCR_1 0x0B
140 
141 #define APIC_TARGET_SELF 0x100
142 #define APIC_TARGET_ALL 0x200
143 #define APIC_TARGET_ALL_BUT_SELF 0x300
144 
145 #define APIC_INTEGRATED(version) (version & 0xF0)
146 
147 typedef enum {
148  amPIC = 0, /* IMCR and PIC compatibility mode */
149  amVWIRE /* Virtual Wire compatibility mode */
150 } APIC_MODE;
151 
152 #ifdef CONFIG_SMP
153 #define MAX_CPU 32
154 #else
155 #define MAX_CPU 1
156 #endif
157 
158 /*
159  * Local APIC timer IRQ vector is on a different priority level,
160  * to work around the 'lost local interrupt if more than 2 IRQ
161  * sources per level' errata.
162  */
163 #define LOCAL_TIMER_VECTOR 0xEF
164 
165 #define IPI_VECTOR 0xFB
166 #define ERROR_VECTOR 0xFE
167 #define SPURIOUS_VECTOR 0xFF /* Must be 0xXF */
168 
169 /* CPU flags */
170 #define CPU_USABLE 0x01 /* 1 if the CPU is usable (ie. can be used) */
171 #define CPU_ENABLED 0x02 /* 1 if the CPU is enabled */
172 #define CPU_BSP 0x04 /* 1 if the CPU is the bootstrap processor */
173 #define CPU_TSC 0x08 /* 1 if the CPU has a time stamp counter */
174 
175 typedef struct _CPU_INFO
176 {
177  UCHAR Flags; /* CPU flags */
178  UCHAR APICId; /* Local APIC ID */
179  UCHAR APICVersion; /* Local APIC version */
180 // UCHAR MaxLVT; /* Number of LVT registers */
181  ULONG BusSpeed; /* BUS speed */
182  ULONG CoreSpeed; /* Core speed */
183  UCHAR Padding[16-12]; /* Padding to 16-byte */
184 } CPU_INFO, *PCPU_INFO;
185 
186 extern ULONG CPUCount; /* Total number of CPUs */
187 extern ULONG BootCPU; /* Bootstrap processor */
188 extern ULONG OnlineCPUs; /* Bitmask of online CPUs */
189 extern CPU_INFO CPUMap[MAX_CPU]; /* Map of all CPUs in the system */
190 
191 /* Prototypes */
192 
193 __inline VOID APICWrite(ULONG Offset, ULONG Value);
194 __inline ULONG APICRead(ULONG Offset);
199 __inline VOID APICSendEOI(VOID);
202 
203 static __inline ULONG ThisCPU(VOID)
204 {
205  return (APICRead(APIC_ID) & APIC_ID_MASK) >> 24;
206 }
207 
208 /* EOF */
_In_opt_ ULONG _Out_ PULONG Value
Definition: rtlfuncs.h:2343
__inline VOID APICSendEOI(VOID)
ULONG CoreSpeed
Definition: apic.h:182
_In_ ULONG Mode
Definition: hubbusif.h:303
#define APIC_ID
Definition: apic.h:10
Definition: apic.h:148
UCHAR Padding[16-12]
Definition: apic.h:183
VOID HaliInitBSP(VOID)
Definition: apic.c:886
#define MAX_CPU
Definition: apic.h:155
#define APIC_ID_MASK
Definition: apic.h:35
struct _CPU_INFO CPU_INFO
CPU_INFO CPUMap[MAX_CPU]
Definition: apic.c:40
__inline VOID APICWrite(ULONG Offset, ULONG Value)
VOID APICSendIPI(ULONG Target, ULONG Mode)
VOID APICSyncArbIDs(VOID)
ULONG OnlineCPUs
Definition: apic.c:39
struct _CPU_INFO * PCPU_INFO
VOID APICCalibrateTimer(ULONG CPU)
Definition: apic.c:794
VOID HaliStartApplicationProcessor(ULONG Cpu, ULONG Stack)
_In_ ULONG _In_ ULONG Offset
Definition: ntddpcm.h:101
UCHAR APICId
Definition: apic.h:178
ULONG BootCPU
Definition: apic.c:38
_Must_inspect_result_ typedef _In_ ULONG _In_ BOOLEAN Target
Definition: iotypes.h:1068
UCHAR APICVersion
Definition: apic.h:179
unsigned char UCHAR
Definition: xmlstorage.h:181
ULONG BusSpeed
Definition: apic.h:181
__inline ULONG APICRead(ULONG Offset)
static __inline ULONG ThisCPU(VOID)
Definition: apic.h:203
ULONG CPUCount
Definition: apic.c:37
unsigned int ULONG
Definition: retypes.h:1
UCHAR Flags
Definition: apic.h:177
Definition: apic.h:149
VOID APICSetup(VOID)
Definition: apic.c:482
APIC_MODE
Definition: apic.h:147