ReactOS  0.4.14-dev-583-g2a1ba2c
apic.h File Reference
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Classes

union  _CPU_INFO
 

Macros

#define APIC_DEFAULT_BASE   0xFEE00000 /* Default Local APIC Base Register Address */
 
#define APIC_ID   0x0020 /* Local APIC ID Register (R/W) */
 
#define APIC_VER   0x0030 /* Local APIC Version Register (R) */
 
#define APIC_TPR   0x0080 /* Task Priority Register (R/W) */
 
#define APIC_APR   0x0090 /* Arbitration Priority Register (R) */
 
#define APIC_PPR   0x00A0 /* Processor Priority Register (R) */
 
#define APIC_EOI   0x00B0 /* EOI Register (W) */
 
#define APIC_LDR   0x00D0 /* Logical Destination Register (R/W) */
 
#define APIC_DFR   0x00E0 /* Destination Format Register (0-27 R, 28-31 R/W) */
 
#define APIC_SIVR   0x00F0 /* Spurious Interrupt Vector Register (0-3 R, 4-9 R/W) */
 
#define APIC_ISR   0x0100 /* Interrupt Service Register 0-255 (R) */
 
#define APIC_TMR   0x0180 /* Trigger Mode Register 0-255 (R) */
 
#define APIC_IRR   0x0200 /* Interrupt Request Register 0-255 (r) */
 
#define APIC_ESR   0x0280 /* Error Status Register (R) */
 
#define APIC_ICR0   0x0300 /* Interrupt Command Register 0-31 (R/W) */
 
#define APIC_ICR1   0x0310 /* Interrupt Command Register 32-63 (R/W) */
 
#define APIC_LVTT   0x0320 /* Local Vector Table (Timer) (R/W) */
 
#define APIC_LVTTHMR   0x0330
 
#define APIC_LVTPC   0x0340 /* Performance Counter LVT (R/W) */
 
#define APIC_LINT0   0x0350 /* Local Vector Table (LINT0) (R/W) */
 
#define APIC_LINT1   0x0360 /* Local Vector Table (LINT1) (R/W) */
 
#define APIC_LVT3   0x0370 /* Local Vector Table (Error) (R/W) */
 
#define APIC_ICRT   0x0380 /* Initial Count Register for Timer (R/W) */
 
#define APIC_CCRT   0x0390 /* Current Count Register for Timer (R) */
 
#define APIC_TDCR   0x03E0 /* Timer Divide Configuration Register (R/W) */
 
#define APIC_ID_MASK   (0xF << 24)
 
#define GET_APIC_ID(x)   (((x) & APIC_ID_MASK) >> 24)
 
#define GET_APIC_LOGICAL_ID(x)   (((x)>>24)&0xFF)
 
#define APIC_VER_MASK   0xFF00FF
 
#define GET_APIC_VERSION(x)   ((x) & 0xFF)
 
#define GET_APIC_MAXLVT(x)   (((x) >> 16) & 0xFF)
 
#define APIC_TPR_PRI   0xFF
 
#define APIC_TPR_INT   0xF0
 
#define APIC_TPR_SUB   0xF
 
#define APIC_TPR_MAX   0xFF /* Maximum priority */
 
#define APIC_TPR_MIN   0x20 /* Minimum priority */
 
#define APIC_LDR_MASK   (0xFF << 24)
 
#define APIC_SIVR_ENABLE   (0x1 << 8)
 
#define APIC_SIVR_FOCUS   (0x1 << 9)
 
#define APIC_ESR_MASK   (0xFE << 0) /* Error Mask */
 
#define APIC_ICR0_VECTOR   (0xFF << 0) /* Vector */
 
#define APIC_ICR0_DM   (0x7 << 8) /* Delivery Mode */
 
#define APIC_ICR0_DESTM   (0x1 << 11) /* Destination Mode */
 
#define APIC_ICR0_DS   (0x1 << 12) /* Delivery Status */
 
#define APIC_ICR0_LEVEL   (0x1 << 14) /* Level */
 
#define APIC_ICR0_TM   (0x1 << 15) /* Trigger Mode */
 
#define APIC_ICR0_DESTS   (0x3 << 18) /* Destination Shorthand */
 
#define APIC_DM_FIXED   (0x0 << 8)
 
#define APIC_DM_LOWEST   (0x1 << 8)
 
#define APIC_DM_SMI   (0x2 << 8)
 
#define APIC_DM_REMRD   (0x3 << 8)
 
#define APIC_DM_NMI   (0x4 << 8)
 
#define APIC_DM_INIT   (0x5 << 8)
 
#define APIC_DM_STARTUP   (0x6 << 8)
 
#define APIC_DM_EXTINT   (0x7 << 8)
 
#define GET_APIC_DELIVERY_MODE(x)   (((x) >> 8) & 0x7)
 
#define SET_APIC_DELIVERY_MODE(x, y)   (((x) & ~0x700) | ((y) << 8))
 
#define APIC_ICR0_DESTS_FIELD   (0x0 << 0)
 
#define APIC_ICR0_DESTS_SELF   (0x1 << 18)
 
#define APIC_ICR0_DESTS_ALL   (0x2 << 18)
 
#define APIC_ICR0_DESTS_ALL_BUT_SELF   (0x3 << 18)
 
#define APIC_ICR0_LEVEL_DEASSERT   (0x0 << 14) /* Deassert level */
 
#define APIC_ICR0_LEVEL_ASSERT   (0x1 << 14) /* Assert level */
 
#define GET_APIC_DEST_FIELD(x)   (((x) >> 24) & 0xFF)
 
#define SET_APIC_DEST_FIELD(x)   (((x) & 0xFF) << 24)
 
#define GET_APIC_TIMER_BASE(x)   (((x) >> 18) & 0x3)
 
#define SET_APIC_TIMER_BASE(x)   ((x) << 18)
 
#define APIC_TIMER_BASE_CLKIN   0x0
 
#define APIC_TIMER_BASE_TMBASE   0x1
 
#define APIC_TIMER_BASE_DIV   0x2
 
#define APIC_LVT_VECTOR   (0xFF << 0) /* Vector */
 
#define APIC_LVT_DS   (0x1 << 12) /* Delivery Status */
 
#define APIC_LVT_REMOTE_IRR   (0x1 << 14) /* Remote IRR */
 
#define APIC_LVT_LEVEL_TRIGGER   (0x1 << 15) /* Lvel Triggered */
 
#define APIC_LVT_MASKED   (0x1 << 16) /* Mask */
 
#define APIC_LVT_PERIODIC   (0x1 << 17) /* Timer Mode */
 
#define APIC_LVT3_DM   (0x7 << 8)
 
#define APIC_LVT3_IIPP   (0x1 << 13)
 
#define APIC_LVT3_TM   (0x1 << 15)
 
#define APIC_LVT3_MASKED   (0x1 << 16)
 
#define APIC_LVT3_OS   (0x1 << 17)
 
#define APIC_TDCR_TMBASE   (0x1 << 2)
 
#define APIC_TDCR_MASK   0x0F
 
#define APIC_TDCR_2   0x00
 
#define APIC_TDCR_4   0x01
 
#define APIC_TDCR_8   0x02
 
#define APIC_TDCR_16   0x03
 
#define APIC_TDCR_32   0x08
 
#define APIC_TDCR_64   0x09
 
#define APIC_TDCR_128   0x0A
 
#define APIC_TDCR_1   0x0B
 
#define APIC_LVT_VECTOR   (0xFF << 0) /* Vector */
 
#define APIC_LVT_DS   (0x1 << 12) /* Delivery Status */
 
#define APIC_LVT_REMOTE_IRR   (0x1 << 14) /* Remote IRR */
 
#define APIC_LVT_LEVEL_TRIGGER   (0x1 << 15) /* Lvel Triggered */
 
#define APIC_LVT_MASKED   (0x1 << 16) /* Mask */
 
#define APIC_LVT_PERIODIC   (0x1 << 17) /* Timer Mode */
 
#define APIC_LVT3_DM   (0x7 << 8)
 
#define APIC_LVT3_IIPP   (0x1 << 13)
 
#define APIC_LVT3_TM   (0x1 << 15)
 
#define APIC_LVT3_MASKED   (0x1 << 16)
 
#define APIC_LVT3_OS   (0x1 << 17)
 
#define APIC_TDCR_TMBASE   (0x1 << 2)
 
#define APIC_TDCR_MASK   0x0F
 
#define APIC_TDCR_2   0x00
 
#define APIC_TDCR_4   0x01
 
#define APIC_TDCR_8   0x02
 
#define APIC_TDCR_16   0x03
 
#define APIC_TDCR_32   0x08
 
#define APIC_TDCR_64   0x09
 
#define APIC_TDCR_128   0x0A
 
#define APIC_TDCR_1   0x0B
 
#define APIC_TARGET_SELF   0x100
 
#define APIC_TARGET_ALL   0x200
 
#define APIC_TARGET_ALL_BUT_SELF   0x300
 
#define APIC_INTEGRATED(version)   (version & 0xF0)
 
#define MAX_CPU   1
 
#define LOCAL_TIMER_VECTOR   0xEF
 
#define IPI_VECTOR   0xFB
 
#define ERROR_VECTOR   0xFE
 
#define SPURIOUS_VECTOR   0xFF /* Must be 0xXF */
 
#define CPU_USABLE   0x01 /* 1 if the CPU is usable (ie. can be used) */
 
#define CPU_ENABLED   0x02 /* 1 if the CPU is enabled */
 
#define CPU_BSP   0x04 /* 1 if the CPU is the bootstrap processor */
 
#define CPU_TSC   0x08 /* 1 if the CPU has a time stamp counter */
 

Typedefs

typedef struct _CPU_INFO CPU_INFO
 
typedef struct _CPU_INFOPCPU_INFO
 

Enumerations

enum  APIC_MODE { amPIC = 0, amVWIRE, amPIC = 0, amVWIRE }
 

Functions

__inline VOID APICWrite (ULONG Offset, ULONG Value)
 
__inline ULONG APICRead (ULONG Offset)
 
VOID APICSendIPI (ULONG Target, ULONG Mode)
 
VOID APICSetup (VOID)
 
VOID HaliInitBSP (VOID)
 
VOID APICSyncArbIDs (VOID)
 
__inline VOID APICSendEOI (VOID)
 
VOID APICCalibrateTimer (ULONG CPU)
 
VOID HaliStartApplicationProcessor (ULONG Cpu, ULONG Stack)
 
static __inline ULONG ThisCPU (VOID)
 

Variables

ULONG CPUCount
 
ULONG BootCPU
 
ULONG OnlineCPUs
 
CPU_INFO CPUMap [MAX_CPU]
 

Macro Definition Documentation

◆ APIC_APR

#define APIC_APR   0x0090 /* Arbitration Priority Register (R) */

Definition at line 13 of file apic.h.

◆ APIC_CCRT

#define APIC_CCRT   0x0390 /* Current Count Register for Timer (R) */

Definition at line 32 of file apic.h.

◆ APIC_DEFAULT_BASE

#define APIC_DEFAULT_BASE   0xFEE00000 /* Default Local APIC Base Register Address */

Definition at line 7 of file apic.h.

◆ APIC_DFR

#define APIC_DFR   0x00E0 /* Destination Format Register (0-27 R, 28-31 R/W) */

Definition at line 17 of file apic.h.

◆ APIC_DM_EXTINT

#define APIC_DM_EXTINT   (0x7 << 8)

Definition at line 71 of file apic.h.

◆ APIC_DM_FIXED

#define APIC_DM_FIXED   (0x0 << 8)

Definition at line 64 of file apic.h.

◆ APIC_DM_INIT

#define APIC_DM_INIT   (0x5 << 8)

Definition at line 69 of file apic.h.

◆ APIC_DM_LOWEST

#define APIC_DM_LOWEST   (0x1 << 8)

Definition at line 65 of file apic.h.

◆ APIC_DM_NMI

#define APIC_DM_NMI   (0x4 << 8)

Definition at line 68 of file apic.h.

◆ APIC_DM_REMRD

#define APIC_DM_REMRD   (0x3 << 8)

Definition at line 67 of file apic.h.

◆ APIC_DM_SMI

#define APIC_DM_SMI   (0x2 << 8)

Definition at line 66 of file apic.h.

◆ APIC_DM_STARTUP

#define APIC_DM_STARTUP   (0x6 << 8)

Definition at line 70 of file apic.h.

◆ APIC_EOI

#define APIC_EOI   0x00B0 /* EOI Register (W) */

Definition at line 15 of file apic.h.

◆ APIC_ESR

#define APIC_ESR   0x0280 /* Error Status Register (R) */

Definition at line 22 of file apic.h.

◆ APIC_ESR_MASK

#define APIC_ESR_MASK   (0xFE << 0) /* Error Mask */

Definition at line 53 of file apic.h.

◆ APIC_ICR0

#define APIC_ICR0   0x0300 /* Interrupt Command Register 0-31 (R/W) */

Definition at line 23 of file apic.h.

◆ APIC_ICR0_DESTM

#define APIC_ICR0_DESTM   (0x1 << 11) /* Destination Mode */

Definition at line 57 of file apic.h.

◆ APIC_ICR0_DESTS

#define APIC_ICR0_DESTS   (0x3 << 18) /* Destination Shorthand */

Definition at line 61 of file apic.h.

◆ APIC_ICR0_DESTS_ALL

#define APIC_ICR0_DESTS_ALL   (0x2 << 18)

Definition at line 78 of file apic.h.

◆ APIC_ICR0_DESTS_ALL_BUT_SELF

#define APIC_ICR0_DESTS_ALL_BUT_SELF   (0x3 << 18)

Definition at line 79 of file apic.h.

◆ APIC_ICR0_DESTS_FIELD

#define APIC_ICR0_DESTS_FIELD   (0x0 << 0)

Definition at line 76 of file apic.h.

◆ APIC_ICR0_DESTS_SELF

#define APIC_ICR0_DESTS_SELF   (0x1 << 18)

Definition at line 77 of file apic.h.

◆ APIC_ICR0_DM

#define APIC_ICR0_DM   (0x7 << 8) /* Delivery Mode */

Definition at line 56 of file apic.h.

◆ APIC_ICR0_DS

#define APIC_ICR0_DS   (0x1 << 12) /* Delivery Status */

Definition at line 58 of file apic.h.

◆ APIC_ICR0_LEVEL

#define APIC_ICR0_LEVEL   (0x1 << 14) /* Level */

Definition at line 59 of file apic.h.

◆ APIC_ICR0_LEVEL_ASSERT

#define APIC_ICR0_LEVEL_ASSERT   (0x1 << 14) /* Assert level */

Definition at line 82 of file apic.h.

◆ APIC_ICR0_LEVEL_DEASSERT

#define APIC_ICR0_LEVEL_DEASSERT   (0x0 << 14) /* Deassert level */

Definition at line 81 of file apic.h.

◆ APIC_ICR0_TM

#define APIC_ICR0_TM   (0x1 << 15) /* Trigger Mode */

Definition at line 60 of file apic.h.

◆ APIC_ICR0_VECTOR

#define APIC_ICR0_VECTOR   (0xFF << 0) /* Vector */

Definition at line 55 of file apic.h.

◆ APIC_ICR1

#define APIC_ICR1   0x0310 /* Interrupt Command Register 32-63 (R/W) */

Definition at line 24 of file apic.h.

◆ APIC_ICRT

#define APIC_ICRT   0x0380 /* Initial Count Register for Timer (R/W) */

Definition at line 31 of file apic.h.

◆ APIC_ID

#define APIC_ID   0x0020 /* Local APIC ID Register (R/W) */

Definition at line 10 of file apic.h.

◆ APIC_ID_MASK

#define APIC_ID_MASK   (0xF << 24)

Definition at line 35 of file apic.h.

◆ APIC_INTEGRATED

#define APIC_INTEGRATED (   version)    (version & 0xF0)

Definition at line 145 of file apic.h.

◆ APIC_IRR

#define APIC_IRR   0x0200 /* Interrupt Request Register 0-255 (r) */

Definition at line 21 of file apic.h.

◆ APIC_ISR

#define APIC_ISR   0x0100 /* Interrupt Service Register 0-255 (R) */

Definition at line 19 of file apic.h.

◆ APIC_LDR

#define APIC_LDR   0x00D0 /* Logical Destination Register (R/W) */

Definition at line 16 of file apic.h.

◆ APIC_LDR_MASK

#define APIC_LDR_MASK   (0xFF << 24)

Definition at line 48 of file apic.h.

◆ APIC_LINT0

#define APIC_LINT0   0x0350 /* Local Vector Table (LINT0) (R/W) */

Definition at line 28 of file apic.h.

◆ APIC_LINT1

#define APIC_LINT1   0x0360 /* Local Vector Table (LINT1) (R/W) */

Definition at line 29 of file apic.h.

◆ APIC_LVT3

#define APIC_LVT3   0x0370 /* Local Vector Table (Error) (R/W) */

Definition at line 30 of file apic.h.

◆ APIC_LVT3_DM [1/2]

#define APIC_LVT3_DM   (0x7 << 8)

Definition at line 124 of file apic.h.

◆ APIC_LVT3_DM [2/2]

#define APIC_LVT3_DM   (0x7 << 8)

Definition at line 124 of file apic.h.

◆ APIC_LVT3_IIPP [1/2]

#define APIC_LVT3_IIPP   (0x1 << 13)

Definition at line 125 of file apic.h.

◆ APIC_LVT3_IIPP [2/2]

#define APIC_LVT3_IIPP   (0x1 << 13)

Definition at line 125 of file apic.h.

◆ APIC_LVT3_MASKED [1/2]

#define APIC_LVT3_MASKED   (0x1 << 16)

Definition at line 127 of file apic.h.

◆ APIC_LVT3_MASKED [2/2]

#define APIC_LVT3_MASKED   (0x1 << 16)

Definition at line 127 of file apic.h.

◆ APIC_LVT3_OS [1/2]

#define APIC_LVT3_OS   (0x1 << 17)

Definition at line 128 of file apic.h.

◆ APIC_LVT3_OS [2/2]

#define APIC_LVT3_OS   (0x1 << 17)

Definition at line 128 of file apic.h.

◆ APIC_LVT3_TM [1/2]

#define APIC_LVT3_TM   (0x1 << 15)

Definition at line 126 of file apic.h.

◆ APIC_LVT3_TM [2/2]

#define APIC_LVT3_TM   (0x1 << 15)

Definition at line 126 of file apic.h.

◆ APIC_LVT_DS [1/2]

#define APIC_LVT_DS   (0x1 << 12) /* Delivery Status */

Definition at line 118 of file apic.h.

◆ APIC_LVT_DS [2/2]

#define APIC_LVT_DS   (0x1 << 12) /* Delivery Status */

Definition at line 118 of file apic.h.

◆ APIC_LVT_LEVEL_TRIGGER [1/2]

#define APIC_LVT_LEVEL_TRIGGER   (0x1 << 15) /* Lvel Triggered */

Definition at line 120 of file apic.h.

◆ APIC_LVT_LEVEL_TRIGGER [2/2]

#define APIC_LVT_LEVEL_TRIGGER   (0x1 << 15) /* Lvel Triggered */

Definition at line 120 of file apic.h.

◆ APIC_LVT_MASKED [1/2]

#define APIC_LVT_MASKED   (0x1 << 16) /* Mask */

Definition at line 121 of file apic.h.

◆ APIC_LVT_MASKED [2/2]

#define APIC_LVT_MASKED   (0x1 << 16) /* Mask */

Definition at line 121 of file apic.h.

◆ APIC_LVT_PERIODIC [1/2]

#define APIC_LVT_PERIODIC   (0x1 << 17) /* Timer Mode */

Definition at line 122 of file apic.h.

◆ APIC_LVT_PERIODIC [2/2]

#define APIC_LVT_PERIODIC   (0x1 << 17) /* Timer Mode */

Definition at line 122 of file apic.h.

◆ APIC_LVT_REMOTE_IRR [1/2]

#define APIC_LVT_REMOTE_IRR   (0x1 << 14) /* Remote IRR */

Definition at line 119 of file apic.h.

◆ APIC_LVT_REMOTE_IRR [2/2]

#define APIC_LVT_REMOTE_IRR   (0x1 << 14) /* Remote IRR */

Definition at line 119 of file apic.h.

◆ APIC_LVT_VECTOR [1/2]

#define APIC_LVT_VECTOR   (0xFF << 0) /* Vector */

Definition at line 117 of file apic.h.

◆ APIC_LVT_VECTOR [2/2]

#define APIC_LVT_VECTOR   (0xFF << 0) /* Vector */

Definition at line 117 of file apic.h.

◆ APIC_LVTPC

#define APIC_LVTPC   0x0340 /* Performance Counter LVT (R/W) */

Definition at line 27 of file apic.h.

◆ APIC_LVTT

#define APIC_LVTT   0x0320 /* Local Vector Table (Timer) (R/W) */

Definition at line 25 of file apic.h.

◆ APIC_LVTTHMR

#define APIC_LVTTHMR   0x0330

Definition at line 26 of file apic.h.

◆ APIC_PPR

#define APIC_PPR   0x00A0 /* Processor Priority Register (R) */

Definition at line 14 of file apic.h.

◆ APIC_SIVR

#define APIC_SIVR   0x00F0 /* Spurious Interrupt Vector Register (0-3 R, 4-9 R/W) */

Definition at line 18 of file apic.h.

◆ APIC_SIVR_ENABLE

#define APIC_SIVR_ENABLE   (0x1 << 8)

Definition at line 50 of file apic.h.

◆ APIC_SIVR_FOCUS

#define APIC_SIVR_FOCUS   (0x1 << 9)

Definition at line 51 of file apic.h.

◆ APIC_TARGET_ALL

#define APIC_TARGET_ALL   0x200

Definition at line 142 of file apic.h.

◆ APIC_TARGET_ALL_BUT_SELF

#define APIC_TARGET_ALL_BUT_SELF   0x300

Definition at line 143 of file apic.h.

◆ APIC_TARGET_SELF

#define APIC_TARGET_SELF   0x100

Definition at line 141 of file apic.h.

◆ APIC_TDCR

#define APIC_TDCR   0x03E0 /* Timer Divide Configuration Register (R/W) */

Definition at line 33 of file apic.h.

◆ APIC_TDCR_1 [1/2]

#define APIC_TDCR_1   0x0B

Definition at line 139 of file apic.h.

◆ APIC_TDCR_1 [2/2]

#define APIC_TDCR_1   0x0B

Definition at line 139 of file apic.h.

◆ APIC_TDCR_128 [1/2]

#define APIC_TDCR_128   0x0A

Definition at line 138 of file apic.h.

◆ APIC_TDCR_128 [2/2]

#define APIC_TDCR_128   0x0A

Definition at line 138 of file apic.h.

◆ APIC_TDCR_16 [1/2]

#define APIC_TDCR_16   0x03

Definition at line 135 of file apic.h.

◆ APIC_TDCR_16 [2/2]

#define APIC_TDCR_16   0x03

Definition at line 135 of file apic.h.

◆ APIC_TDCR_2 [1/2]

#define APIC_TDCR_2   0x00

Definition at line 132 of file apic.h.

◆ APIC_TDCR_2 [2/2]

#define APIC_TDCR_2   0x00

Definition at line 132 of file apic.h.

◆ APIC_TDCR_32 [1/2]

#define APIC_TDCR_32   0x08

Definition at line 136 of file apic.h.

◆ APIC_TDCR_32 [2/2]

#define APIC_TDCR_32   0x08

Definition at line 136 of file apic.h.

◆ APIC_TDCR_4 [1/2]

#define APIC_TDCR_4   0x01

Definition at line 133 of file apic.h.

◆ APIC_TDCR_4 [2/2]

#define APIC_TDCR_4   0x01

Definition at line 133 of file apic.h.

◆ APIC_TDCR_64 [1/2]

#define APIC_TDCR_64   0x09

Definition at line 137 of file apic.h.

◆ APIC_TDCR_64 [2/2]

#define APIC_TDCR_64   0x09

Definition at line 137 of file apic.h.

◆ APIC_TDCR_8 [1/2]

#define APIC_TDCR_8   0x02

Definition at line 134 of file apic.h.

◆ APIC_TDCR_8 [2/2]

#define APIC_TDCR_8   0x02

Definition at line 134 of file apic.h.

◆ APIC_TDCR_MASK [1/2]

#define APIC_TDCR_MASK   0x0F

Definition at line 131 of file apic.h.

◆ APIC_TDCR_MASK [2/2]

#define APIC_TDCR_MASK   0x0F

Definition at line 131 of file apic.h.

◆ APIC_TDCR_TMBASE [1/2]

#define APIC_TDCR_TMBASE   (0x1 << 2)

Definition at line 130 of file apic.h.

◆ APIC_TDCR_TMBASE [2/2]

#define APIC_TDCR_TMBASE   (0x1 << 2)

Definition at line 130 of file apic.h.

◆ APIC_TIMER_BASE_CLKIN

#define APIC_TIMER_BASE_CLKIN   0x0

Definition at line 89 of file apic.h.

◆ APIC_TIMER_BASE_DIV

#define APIC_TIMER_BASE_DIV   0x2

Definition at line 91 of file apic.h.

◆ APIC_TIMER_BASE_TMBASE

#define APIC_TIMER_BASE_TMBASE   0x1

Definition at line 90 of file apic.h.

◆ APIC_TMR

#define APIC_TMR   0x0180 /* Trigger Mode Register 0-255 (R) */

Definition at line 20 of file apic.h.

◆ APIC_TPR

#define APIC_TPR   0x0080 /* Task Priority Register (R/W) */

Definition at line 12 of file apic.h.

◆ APIC_TPR_INT

#define APIC_TPR_INT   0xF0

Definition at line 43 of file apic.h.

◆ APIC_TPR_MAX

#define APIC_TPR_MAX   0xFF /* Maximum priority */

Definition at line 45 of file apic.h.

◆ APIC_TPR_MIN

#define APIC_TPR_MIN   0x20 /* Minimum priority */

Definition at line 46 of file apic.h.

◆ APIC_TPR_PRI

#define APIC_TPR_PRI   0xFF

Definition at line 42 of file apic.h.

◆ APIC_TPR_SUB

#define APIC_TPR_SUB   0xF

Definition at line 44 of file apic.h.

◆ APIC_VER

#define APIC_VER   0x0030 /* Local APIC Version Register (R) */

Definition at line 11 of file apic.h.

◆ APIC_VER_MASK

#define APIC_VER_MASK   0xFF00FF

Definition at line 38 of file apic.h.

◆ CPU_BSP

#define CPU_BSP   0x04 /* 1 if the CPU is the bootstrap processor */

Definition at line 172 of file apic.h.

◆ CPU_ENABLED

#define CPU_ENABLED   0x02 /* 1 if the CPU is enabled */

Definition at line 171 of file apic.h.

◆ CPU_TSC

#define CPU_TSC   0x08 /* 1 if the CPU has a time stamp counter */

Definition at line 173 of file apic.h.

◆ CPU_USABLE

#define CPU_USABLE   0x01 /* 1 if the CPU is usable (ie. can be used) */

Definition at line 170 of file apic.h.

◆ ERROR_VECTOR

#define ERROR_VECTOR   0xFE

Definition at line 166 of file apic.h.

◆ GET_APIC_DELIVERY_MODE

#define GET_APIC_DELIVERY_MODE (   x)    (((x) >> 8) & 0x7)

Definition at line 72 of file apic.h.

◆ GET_APIC_DEST_FIELD

#define GET_APIC_DEST_FIELD (   x)    (((x) >> 24) & 0xFF)

Definition at line 84 of file apic.h.

◆ GET_APIC_ID

#define GET_APIC_ID (   x)    (((x) & APIC_ID_MASK) >> 24)

Definition at line 36 of file apic.h.

◆ GET_APIC_LOGICAL_ID

#define GET_APIC_LOGICAL_ID (   x)    (((x)>>24)&0xFF)

Definition at line 37 of file apic.h.

◆ GET_APIC_MAXLVT

#define GET_APIC_MAXLVT (   x)    (((x) >> 16) & 0xFF)

Definition at line 40 of file apic.h.

◆ GET_APIC_TIMER_BASE

#define GET_APIC_TIMER_BASE (   x)    (((x) >> 18) & 0x3)

Definition at line 87 of file apic.h.

◆ GET_APIC_VERSION

#define GET_APIC_VERSION (   x)    ((x) & 0xFF)

Definition at line 39 of file apic.h.

◆ IPI_VECTOR

#define IPI_VECTOR   0xFB

Definition at line 165 of file apic.h.

◆ LOCAL_TIMER_VECTOR

#define LOCAL_TIMER_VECTOR   0xEF

Definition at line 163 of file apic.h.

◆ MAX_CPU

#define MAX_CPU   1

Definition at line 155 of file apic.h.

◆ SET_APIC_DELIVERY_MODE

#define SET_APIC_DELIVERY_MODE (   x,
  y 
)    (((x) & ~0x700) | ((y) << 8))

Definition at line 73 of file apic.h.

◆ SET_APIC_DEST_FIELD

#define SET_APIC_DEST_FIELD (   x)    (((x) & 0xFF) << 24)

Definition at line 85 of file apic.h.

◆ SET_APIC_TIMER_BASE

#define SET_APIC_TIMER_BASE (   x)    ((x) << 18)

Definition at line 88 of file apic.h.

◆ SPURIOUS_VECTOR

#define SPURIOUS_VECTOR   0xFF /* Must be 0xXF */

Definition at line 167 of file apic.h.

Typedef Documentation

◆ CPU_INFO

◆ PCPU_INFO

Enumeration Type Documentation

◆ APIC_MODE

Enumerator
amPIC 
amVWIRE 
amPIC 
amVWIRE 

Definition at line 147 of file apic.h.

147  {
148  amPIC = 0, /* IMCR and PIC compatibility mode */
149  amVWIRE /* Virtual Wire compatibility mode */
150 } APIC_MODE;
Definition: apic.h:148
Definition: apic.h:149
APIC_MODE
Definition: apic.h:147

Function Documentation

◆ APICCalibrateTimer()

VOID APICCalibrateTimer ( ULONG  CPU)

Definition at line 794 of file apic.c.

795 {
796  ULARGE_INTEGER t1, t2;
797  LONG tt1, tt2;
798  BOOLEAN TSCPresent;
799 
800  DPRINT("Calibrating APIC timer for CPU %d\n", CPU);
801 
802  APICSetupLVTT(1000000000);
803 
804  TSCPresent = KeGetCurrentPrcb()->FeatureBits & KF_RDTSC ? TRUE : FALSE;
805 
806  /*
807  * The timer chip counts down to zero. Let's wait
808  * for a wraparound to start exact measurement:
809  * (the current tick might have been already half done)
810  */
811  //WaitFor8254Wraparound();
812 
813  /*
814  * We wrapped around just now. Let's start
815  */
816  if (TSCPresent)
817  {
818  t1.QuadPart = (LONGLONG)__rdtsc();
819  }
820  tt1 = APICRead(APIC_CCRT);
821 
822  //WaitFor8254Wraparound();
823 
824 
825  tt2 = APICRead(APIC_CCRT);
826  if (TSCPresent)
827  {
828  t2.QuadPart = (LONGLONG)__rdtsc();
829  CPUMap[CPU].CoreSpeed = (HZ * (ULONG)(t2.QuadPart - t1.QuadPart));
830  DPRINT("CPU clock speed is %ld.%04ld MHz.\n",
831  CPUMap[CPU].CoreSpeed/1000000,
832  CPUMap[CPU].CoreSpeed%1000000);
833  KeGetCurrentPrcb()->MHz = CPUMap[CPU].CoreSpeed/1000000;
834  }
835 
836  CPUMap[CPU].BusSpeed = (HZ * (long)(tt1 - tt2) * APIC_DIVISOR);
837 
838  /* Setup timer for normal operation */
839 // APICSetupLVTT((CPUMap[CPU].BusSpeed / 1000000) * 100); // 100ns
840  APICSetupLVTT((CPUMap[CPU].BusSpeed / 1000000) * 10000); // 10ms
841 // APICSetupLVTT((CPUMap[CPU].BusSpeed / 1000000) * 100000); // 100ms
842 
843  DPRINT("Host bus clock speed is %ld.%04ld MHz.\n",
844  CPUMap[CPU].BusSpeed/1000000,
845  CPUMap[CPU].BusSpeed%1000000);
846 }
#define TRUE
Definition: types.h:120
ULONG CoreSpeed
Definition: apic.h:182
#define KF_RDTSC
Definition: ketypes.h:144
FORCEINLINE struct _KPRCB * KeGetCurrentPrcb(VOID)
Definition: ketypes.h:1062
PPC_QUAL unsigned long long __rdtsc(void)
Definition: intrin_ppc.h:688
ULONGLONG QuadPart
Definition: ms-dtyp.idl:185
long LONG
Definition: pedump.c:60
unsigned char BOOLEAN
void DPRINT(...)
Definition: polytest.cpp:61
VOID APICSetupLVTT(ULONG ClockTicks)
Definition: apic.c:770
int64_t LONGLONG
Definition: typedefs.h:66
#define APIC_DIVISOR
Definition: apic.c:76
ULONG BusSpeed
Definition: apic.h:181
#define APIC_CCRT
Definition: apic.h:32
__inline ULONG APICRead(ULONG Offset)
CPU_INFO CPUMap[MAX_CPU]
Definition: apic.c:40
#define long
Definition: qsort.c:33
#define HZ
Definition: apic.c:75
unsigned int ULONG
Definition: retypes.h:1

Referenced by HalInitializeProcessor().

◆ APICRead()

◆ APICSendEOI()

__inline VOID APICSendEOI ( VOID  )

◆ APICSendIPI()

VOID APICSendIPI ( ULONG  Target,
ULONG  Mode 
)

Referenced by HalRequestIpi().

◆ APICSetup()

VOID APICSetup ( VOID  )

Definition at line 482 of file apic.c.

483 {
484  ULONG CPU, tmp;
485 
486  CPU = ThisCPU();
487 
488 // APICDump();
489 
490  DPRINT1("CPU%d:\n", CPU);
491  DPRINT1(" Physical APIC id: %d\n", GET_APIC_ID(APICRead(APIC_ID)));
492  DPRINT1(" Logical APIC id: %d\n", GET_APIC_LOGICAL_ID(APICRead(APIC_LDR)));
493  DPRINT1("%08x %08x %08x\n", APICRead(APIC_ID), APICRead(APIC_LDR), APICRead(APIC_DFR));
494 
495  /*
496  * Intel recommends to set DFR, LDR and TPR before enabling
497  * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
498  * document number 292116). So here it goes...
499  */
500 
501  /*
502  * Put the APIC into flat delivery mode.
503  * Must be "all ones" explicitly for 82489DX.
504  */
505  APICWrite(APIC_DFR, 0xFFFFFFFF);
506 
507  /*
508  * Set up the logical destination ID.
509  */
510  tmp = APICRead(APIC_LDR);
511  tmp &= ~APIC_LDR_MASK;
512  /*
513  * FIXME:
514  * This works only up to 8 CPU's
515  */
516  tmp |= (1 << (KeGetCurrentProcessorNumber() + 24));
517  APICWrite(APIC_LDR, tmp);
518 
519 
520  DPRINT1("CPU%d:\n", CPU);
521  DPRINT1(" Physical APIC id: %d\n", GET_APIC_ID(APICRead(APIC_ID)));
522  DPRINT1(" Logical APIC id: %d\n", GET_APIC_LOGICAL_ID(APICRead(APIC_LDR)));
523  DPRINT1("%08x %08x %08x\n", APICRead(APIC_ID), APICRead(APIC_LDR), APICRead(APIC_DFR));
524  DPRINT1("%d\n", CPUMap[CPU].APICId);
525 
526  /* Accept only higher interrupts */
527  APICWrite(APIC_TPR, 0xef);
528 
529  /* Enable local APIC */
530  tmp = APICRead(APIC_SIVR);
531  tmp &= ~0xff;
532  tmp |= APIC_SIVR_ENABLE;
533 
534 #if 0
535  tmp &= ~APIC_SIVR_FOCUS;
536 #else
537  tmp |= APIC_SIVR_FOCUS;
538 #endif
539 
540  /* Set spurious interrupt vector */
541  tmp |= SPURIOUS_VECTOR;
542  APICWrite(APIC_SIVR, tmp);
543 
544  /*
545  * Set up LVT0, LVT1:
546  *
547  * set up through-local-APIC on the BP's LINT0. This is not
548  * strictly necessery in pure symmetric-IO mode, but sometimes
549  * we delegate interrupts to the 8259A.
550  */
552  if (CPU == BootCPU && (APICMode == amPIC || !tmp))
553  {
554  tmp = APIC_DM_EXTINT;
555  DPRINT1("enabled ExtINT on CPU#%d\n", CPU);
556  }
557  else
558  {
560  DPRINT1("masked ExtINT on CPU#%d\n", CPU);
561  }
562  APICWrite(APIC_LINT0, tmp);
563 
564  /*
565  * Only the BSP should see the LINT1 NMI signal, obviously.
566  */
567  if (CPU == BootCPU)
568  {
569  tmp = APIC_DM_NMI;
570  }
571  else
572  {
574  }
575  if (!APIC_INTEGRATED(CPUMap[CPU].APICVersion))
576  {
577  /* 82489DX */
578  tmp |= APIC_LVT_LEVEL_TRIGGER;
579  }
580  APICWrite(APIC_LINT1, tmp);
581 
582  if (APIC_INTEGRATED(CPUMap[CPU].APICVersion))
583  {
584  /* !82489DX */
585  if (APICGetMaxLVT() > 3)
586  {
587  /* Due to the Pentium erratum 3AP */
588  APICWrite(APIC_ESR, 0);
589  }
590 
591  tmp = APICRead(APIC_ESR);
592  DPRINT("ESR value before enabling vector: 0x%X\n", tmp);
593 
594  /* Enable sending errors */
595  tmp = ERROR_VECTOR;
596  APICWrite(APIC_LVT3, tmp);
597 
598  /*
599  * Spec says clear errors after enabling vector
600  */
601  if (APICGetMaxLVT() > 3)
602  {
603  APICWrite(APIC_ESR, 0);
604  }
605  tmp = APICRead(APIC_ESR);
606  DPRINT("ESR value after enabling vector: 0x%X\n", tmp);
607  }
608 }
#define APIC_LDR_MASK
Definition: apic.h:48
#define APIC_LDR
Definition: apic.h:16
#define ERROR_VECTOR
Definition: apic.h:166
#define GET_APIC_LOGICAL_ID(x)
Definition: apic.h:37
#define APIC_ID
Definition: apic.h:10
#define APIC_DM_EXTINT
Definition: apic.h:71
Definition: apic.h:148
__inline VOID APICWrite(ULONG Offset, ULONG Value)
#define APIC_DM_NMI
Definition: apic.h:68
ULONG APICGetMaxLVT(VOID)
Definition: apic.c:99
#define APIC_LVT_MASKED
Definition: apic.h:121
#define APIC_TPR
Definition: apic.h:12
FORCEINLINE ULONG KeGetCurrentProcessorNumber(VOID)
Definition: ke.h:325
#define APIC_LVT_LEVEL_TRIGGER
Definition: apic.h:120
void DPRINT(...)
Definition: polytest.cpp:61
#define APIC_DFR
Definition: apic.h:17
#define APIC_INTEGRATED(version)
Definition: apic.h:145
#define APIC_LINT1
Definition: apic.h:29
ULONG BootCPU
Definition: apic.c:38
#define APIC_ESR
Definition: apic.h:22
#define APIC_LVT3
Definition: apic.h:30
__inline ULONG APICRead(ULONG Offset)
#define APIC_SIVR_FOCUS
Definition: apic.h:51
CPU_INFO CPUMap[MAX_CPU]
Definition: apic.c:40
#define SPURIOUS_VECTOR
Definition: apic.h:167
static __inline ULONG ThisCPU(VOID)
Definition: apic.h:203
#define DPRINT1
Definition: precomp.h:8
#define APIC_SIVR
Definition: apic.h:18
ULONG APICMode
Definition: apic.c:49
unsigned int ULONG
Definition: retypes.h:1
#define APIC_SIVR_ENABLE
Definition: apic.h:50
#define APIC_LINT0
Definition: apic.h:28
#define GET_APIC_ID(x)
Definition: apic.h:36

Referenced by HalInitializeProcessor().

◆ APICSyncArbIDs()

VOID APICSyncArbIDs ( VOID  )

Referenced by HalAllProcessorsStarted().

◆ APICWrite()

◆ HaliInitBSP()

VOID HaliInitBSP ( VOID  )

Definition at line 886 of file apic.c.

887 {
888 #ifdef CONFIG_SMP
889  PUSHORT ps;
890 #endif
891 
892  static BOOLEAN BSPInitialized = FALSE;
893 
894  /* Only initialize the BSP once */
895  if (BSPInitialized)
896  {
897  ASSERT(FALSE);
898  return;
899  }
900 
901  BSPInitialized = TRUE;
902 
903  /* Setup interrupt handlers */
907 #ifdef CONFIG_SMP
909 #endif
910  DPRINT("APIC is mapped at 0x%X\n", APICBase);
911 
912  if (VerifyLocalAPIC())
913  {
914  DPRINT("APIC found\n");
915  }
916  else
917  {
918  DPRINT("No APIC found\n");
919  ASSERT(FALSE);
920  }
921 
922  if (APICMode == amPIC)
923  {
924  EnableApicMode();
925  }
926 
927  APICSetup();
928 
929 #ifdef CONFIG_SMP
930  /* BIOS data segment */
931  BIOSBase = (PULONG)BIOS_AREA;
932 
933  /* Area for communicating with the APs */
934  CommonBase = (PULONG)COMMON_AREA;
935 
936  /* Copy bootstrap code to common area */
937  memcpy((PVOID)((ULONG_PTR)CommonBase + PAGE_SIZE),
938  &APstart,
939  (ULONG_PTR)&APend - (ULONG_PTR)&APstart + 1);
940 
941  /* Set shutdown code */
942  CMOS_WRITE(0xF, 0xA);
943 
944  /* Set warm reset vector */
945  ps = (PUSHORT)((ULONG_PTR)BIOSBase + 0x467);
946  *ps = (COMMON_AREA + PAGE_SIZE) & 0xF;
947 
948  ps = (PUSHORT)((ULONG_PTR)BIOSBase + 0x469);
949  *ps = (COMMON_AREA + PAGE_SIZE) >> 4;
950 #endif
951 
952  /* Calibrate APIC timer */
954 }
#define ERROR_VECTOR
Definition: apic.h:166
#define TRUE
Definition: types.h:120
#define IPI_VECTOR
Definition: apic.h:165
VOID MpsSpuriousInterrupt(VOID)
Definition: apic.h:148
VOID MpsTimerInterrupt(VOID)
uint32_t ULONG_PTR
Definition: typedefs.h:63
VOID EnableApicMode(VOID)
Definition: apic.c:174
#define LOCAL_TIMER_VECTOR
Definition: apic.h:163
#define BIOS_AREA
Definition: apic.c:72
unsigned char BOOLEAN
BOOLEAN VerifyLocalAPIC(VOID)
Definition: apic.c:350
#define CMOS_WRITE(address, value)
Definition: apic.c:83
void DPRINT(...)
Definition: polytest.cpp:61
VOID SetInterruptGate(ULONG index, ULONG_PTR address)
Definition: apic.c:849
CHAR * APstart
ULONG BootCPU
Definition: apic.c:38
ASSERT((InvokeOnSuccess||InvokeOnError||InvokeOnCancel) ?(CompletionRoutine !=NULL) :TRUE)
#define memcpy(s1, s2, n)
Definition: mkisofs.h:878
#define PAGE_SIZE
Definition: env_spec_w32.h:49
VOID APICCalibrateTimer(ULONG CPU)
Definition: apic.c:794
VOID MpsIpiInterrupt(VOID)
CHAR * APend
PULONG APICBase
Definition: apic.c:47
#define SPURIOUS_VECTOR
Definition: apic.h:167
unsigned int * PULONG
Definition: retypes.h:1
#define COMMON_AREA
Definition: apic.c:73
ULONG APICMode
Definition: apic.c:49
unsigned short * PUSHORT
Definition: retypes.h:2
VOID MpsErrorInterrupt(VOID)
VOID APICSetup(VOID)
Definition: apic.c:482

Referenced by HalInitializeProcessor().

◆ HaliStartApplicationProcessor()

VOID HaliStartApplicationProcessor ( ULONG  Cpu,
ULONG  Stack 
)

Referenced by HalStartNextProcessor().

◆ ThisCPU()

static __inline ULONG ThisCPU ( VOID  )
static

Definition at line 203 of file apic.h.

204 {
205  return (APICRead(APIC_ID) & APIC_ID_MASK) >> 24;
206 }
#define APIC_ID
Definition: apic.h:10
#define APIC_ID_MASK
Definition: apic.h:35
__inline ULONG APICRead(ULONG Offset)

Referenced by APICDump(), APICSetup(), HalInitializeProcessor(), MpsErrorHandler(), MpsSpuriousHandler(), and MpsTimerHandler().

Variable Documentation

◆ BootCPU

ULONG BootCPU

Definition at line 38 of file apic.c.

Referenced by HaliMPProcessorInfo().

◆ CPUCount

ULONG CPUCount

Definition at line 37 of file apic.c.

Referenced by HalAllProcessorsStarted(), HaliMPProcessorInfo(), and HalStartNextProcessor().

◆ CPUMap

CPU_INFO CPUMap[MAX_CPU]

Definition at line 40 of file apic.c.

Referenced by HaliMPProcessorInfo(), and HalInitializeProcessor().

◆ OnlineCPUs

ULONG OnlineCPUs

Definition at line 39 of file apic.c.

Referenced by HalAllProcessorsStarted(), HalInitializeProcessor(), and HalStartNextProcessor().